JP7145826B2 - Seb耐性評価方法およびseb耐性評価装置 - Google Patents
Seb耐性評価方法およびseb耐性評価装置 Download PDFInfo
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Description
(参考例)
参考文献1(N. Kaminski and A. Kopta, ABB application note 5SYA 2042-04,“Failure rates of HiPak modules due to cosmic rays”)には、SEBによる偶発的破壊の故障確率P(VDC, Tvj, h)を式(1)によって求めることが記載されている。
たとえば、ユーザが、正孔のキャリアライフタイムτp、電子のキャリアライフタイムτnを指定することができる。
本実施の形態では、演算部116は、半導体素子のモデルへの印加電圧および励起光源のエネルギーを変えながら、半導体素子のモデルの内部の最高温度Tmaxの時間変化を求めて、最高温度が閾値TTHに到達したときの励起光源のエネルギーEを半導体素子が不可逆現象を起こす励起光源のエネルギーETHとして特定する。演算部116は、半導体素子のモデル内部の温度の伝導を時間的および空間的に計算することによって、半導体素子のモデル内部の最高温度Tmaxを求めることができる。
本実施の形態では、SEB耐性の評価対象の半導体素子が、実施の形態1および2と相違する。
本実施の形態では、SEB耐性の評価対象の半導体素子が、実施の形態1~3よりも複雑である。
実施の形態1において説明したSEB耐性の評価方法は、ダイオード、IGBTおよびMOSFETなどのトランジスタなどの通電およびスイッチング動作をするセル部分だけでなく、半導体チップを構成する周辺部分にも適用することができる。周辺部分とは、たとえば、ガードリング、FLR(Field Limiting Ring)、VLD(Variation of Lateral Dropping)などの終端構造、ゲートバッド、ゲート配線などである。これによって、半導体チップにおける弱点、弱点が占める比率などに基づいて、半導体チップの総合的なSEB耐性を評価することができる。
本発明は、上記の実施形態に限定されるものではなく、たとえば、以下のような変形例も含む。
図2および図10のステップS103の励起光源の配置は、ステップS101において、半導体素子のモデルの作成した段階で実行されるものとしてもよい。
図2および図10のステップS111~S114の処理は、ユーザ自身が机上計算することによって実施することとしてもよい。たとえば、ユーザが、表計算ソフトウェアを用いることによって、光の強度と中性子の衝突確率の換算処理を実行することとしてもよい。
実施の形態1~5で説明したSEB耐性評価装置は、相当する動作をデジタル回路のハードウェアまたはソフトウェアで構成することができる。SEB耐性評価装置の機能をソフトウェアを用いて実現する場合には、SEB耐性評価装置は、例えば、図16に示すようにプロセッサ1000とメモリ2000とを備え、メモリ2000に記憶されたプログラムをプロセッサ1000が実行するようにすることができる。
Claims (11)
- コンピュータシミュレーションによって、半導体素子のSEB(Single Event Burnout)耐性を評価するSEB耐性評価方法であって、
前記半導体素子のモデル内に励起光源を配置するステップと、
前記半導体素子のモデルへの印加電圧および前記励起光源のエネルギーを変えながら、前記半導体素子が熱暴走する前記励起光源のエネルギーを求めるステップとを備えたSEB耐性評価方法。 - 前記励起光源のエネルギーを求めるステップは、
前記半導体素子のモデルへの印加電圧および前記励起光源のエネルギーを変えながら、前記半導体素子のモデルの主電極間の漏れ電流の時間変化を求めるステップと、
前記漏れ電流が閾値に到達したときの前記励起光源のエネルギーを前記半導体素子が熱暴走するエネルギーとして特定するステップとを含む、請求項1記載のSEB耐性評価方法。 - 前記励起光源のエネルギーを求めるステップは、
前記半導体素子のモデルへの印加電圧および前記励起光源のエネルギーを変えながら、前記半導体素子のモデルの最高温度の時間変化を求めるステップと、
前記最高温度が閾値に到達したときの前記励起光源のエネルギーを前記半導体素子が熱暴走するエネルギーとして特定するステップとを含む、請求項1記載のSEB耐性評価方法。 - 前記印加電圧と、前記半導体素子が熱暴走する励起光源のエネルギーとの対応関係を表わす情報を生成するステップをさらに備えた、請求項2または3記載のSEB耐性評価方法。
- 前記半導体素子が熱暴走する励起光源のエネルギーを中性子の微分フラックスに変換するステップと、
前記微分フラックスを前記半導体素子の平均故障回数に変換するステップと、
前記印加電圧と前記励起光源のエネルギーの対応関係を前記印加電圧と前記平均故障回数との対応関係に変換するステップとをさらに備えた、請求項4記載のSEB耐性評価方法。 - 前記印加電圧と前記平均故障回数との対応関係を表わす曲線を表示するステップをさらに備えた、請求項5記載のSEB耐性評価方法。
- 前記配置するステップは、前記半導体素子のモデルのpn接合部分に前記励起光源を配置するステップを含む、請求項1記載のSEB耐性評価方法。
- 前記半導体素子は、高耐圧縦型ダイオードである、請求項1~7のいずれか1項に記載のSEB耐性評価方法。
- 前記半導体素子は、スイッチング素子である、請求項1~7のいずれか1項に記載のSEB耐性評価方法。
- 前記半導体素子は、終端構造部分またはペリフェラル部分を含む、請求項1~7のいずれか1項に記載のSEB耐性評価方法。
- コンピュータシミュレーションによって、半導体素子のSEB(Single Event Burnout)耐性を評価するSEB耐性評価装置であって、
前記半導体素子のモデル内に励起光源を配置する光源配置部と、
前記半導体素子のモデルへの印加電圧および前記励起光源のエネルギーを変えながら、前記半導体素子が熱暴走する前記励起光源のエネルギーを求める演算部とを備えたSEB耐性評価装置。
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