CN108352384A - 用于改善脉冲宽度可伸缩性的高电压双极结构 - Google Patents
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Abstract
在用于集成电路中的静电放电ESD管理的双极晶体管(200)的所描述实例中,所述双极晶体管(200)在被配置用于ESD保护的双极晶体管单元中实现垂直电流。所述双极晶体管(200)包括选择性嵌入P型浮动掩埋层PBL(230)。在ESD事件期间,所述双极晶体管(200)的基极(260)以极小电流量延伸到所述PBL层(230)。所述PBL层(230)可提供较多孔以支持所述电流,引起所述双极晶体管(200)的降低的保持电压。通过选择性添加所述PBL层(230),所述双极晶体管(200)在较长脉冲宽度下的电流可伸缩性可显著改善。
Description
技术领域
本发明大体上涉及半导体装置,且更具体地说,涉及管理半导体装置中的静电放电(ESD)。
背景技术
一般来说,垂直NPN半导体结构用于高电压应用中的ESD保护,这是因为垂直NPN结构提供有效的电流处置能力。为管理较大半导体装置中的ESD,击穿电流需要可与装置和半导体结构的大小成比例伸缩,包含对于长脉冲宽度。通常,较大半导体结构形成局部化的电流丝,其可阻止所述半导体结构实现较长脉冲宽度的电流可伸缩性。
发明内容
在所描述的半导体装置的实例中,半导体装置包含衬底、形成于衬底中的N型掩埋层、形成于N型掩埋层上方的N阱层、形成于N阱层内的P阱层,和形成于N阱层内在N型掩埋层上方且在P阱层下方的P型掩埋层。
根据集成电路的另一实例,所述集成电路包含衬底,其中N型掩埋层定位于衬底中,N阱层定位于N型掩埋层上方,P阱层形成于N阱层内,且P型掩埋层形成于N阱层内在N型掩埋层的上方且在P阱层的下方。双极晶体管包含定位于扩散于P阱层中的P+区域中的基极、定位于扩散于P阱层中的N+区域中的发射极,和定位于N型掩埋层中的集电极。
根据静电放电装置的另一实例,静电放电装置包含形成于衬底中的双极晶体管,其中N型掩埋层定位于衬底中,N阱层定位于N型掩埋层上方,P阱层形成于N阱层内,且P型掩埋层形成于N阱层内在N型掩埋层的上方且在P阱层的下方。双极晶体管包含定位于扩散于P阱层中的P+区域中的基极、定位于扩散于P阱层中的N+区域中的发射极,和定位于N型掩埋层中的集电极。
附图说明
图1A说明标准NPN半导体单元的截面图。
图1B说明标准NPN半导体单元的发射线脉冲宽度测量值。
图2A说明根据一实施例的NPN双极晶体管单元结构的实例截面图。
图2B说明根据一实施例的PNP双极晶体管单元结构的实例截面图。
图2C说明根据一实施例的集成电路中的用于对P型掩埋双极NPN电晶体进行ESD管理的实例实施方案电路。
图2D说明对根据一实施例的具有P型掩埋层的实例NPN双极晶体管单元结构进行的实例发射线脉冲宽度测量值。
图3A说明根据一实施例的实例NPN双极晶体管单元结构的实例技术计算机辅助设计(TCAD)模拟温度曲线。
图3B说明根据一实施例的实例NPN双极晶体管单元结构的TCAD电子密度曲线。
具体实施方式
以下描述提供用于实施主题的不同特征的许多不同实施例或实例。这些描述仅出于说明的目的。
根据一实施例,公开用于ESD管理的具有较长脉冲宽度可伸缩性的双极晶体管。双极晶体管能够均一NPN单元中的电流来进行ESD保护。双极晶体管包含选择性嵌入的P型掩埋层。将浮动P-区域添加到标准NPN单元的N阱与N型掩埋层(NBL)之间。N阱为轻掺杂的,且其在低电压下被耗尽,导致从NPN单元的浮动p型掩埋区域穿通到基极。这使得柯克效应降低,其降低电流的非均一性,引起较少丝化现象。通过选择性浮动P型掩埋区域,NPN单元在较长脉冲宽度长度(例如,200ns、500ns和更长)下的脉冲宽度可伸缩性可针对ESD事件显著改善。
图1A展示标准NPN半导体单元100的截面图。NPN单元100包含衬底110、N型掩埋层120、N阱130,和P阱140。单元100进一步包含P+基极150和P+基极170,和N+发射极160。NBL120的连接形成衬底110中的NPN单元100的集电极180。通常,将电阻器(例如,20kΩ电阻器)连接于单指NPN的基极150和基极170与发射极160之间。N型槽与P阱140之间的橫向间距影响结构的击穿电压和触发电压。对层之间的橫向接合处冲击离子化将孔电流的部分提供到P+基极150/170。
若干平行电流路径可能为从P+基极150/170到发射极区160。这些电流路径可为垂直的或非垂直的,例如在各种层之间为对角或橫向。当NPN单元100开启时,大多数电流沿垂直路径从NBL 120(集电极)行进到发射极160。由于较长基极宽度和基极接触点的位置,相对较少电流流动穿过非垂直NPN。由于熟知的柯克效应将峰值场的位置推向NBL 120,可形成丝。在NPN单元100在突返模式中触发之后,大多数电流通过一路径从NBL 120行进到具有较大面积的发射极160。由于较长基极宽度和基极接触点的位置,通过橫向NPN单元的电流为较不利的。理想地,可操纵的垂直路径的最大电流量可使用已知的Wunsch钟形曲线预测。
图1B展示标准NPN单元100的发射线脉冲宽度(TLP)测量值。电压和电流测量在脉冲的末端进行。通过10ns上升时间和长于200ns的脉冲,所述结构往往会比预期更早发生故障。对于100ns TLP曲线,存在略微低于1A的导通电阻的变化,其指示存在至少两个电流路径。如所说明,另一明显变化为结构的保持电压对于较长脉冲移位到较小值,其指示形成丝。
对于200ns和更长的脉冲宽度,第二突返发生于仅略微高于第一突返的电流电平的电流电平处。这进一步说明电流丝已形成于装置中。对于大于100ns的脉冲宽度,NPN单元100在低于将通过已知Wunsch钟形关系来预测的电流电平处进入第二击穿,其可能是因为对于较短脉冲宽度的有效镇流。因此,对于ESD事件,常规结构对于较长脉冲宽度(例如,100ns和更长)为不可伸缩的。
图2A展示根据一实施例的NPN双极晶体管单元结构200的实例截面图。NPN单元200建立在衬底210上。N型掩埋层(NBL)220扩散于衬底210中。可使用各种已知加工技术将NBL220扩散于衬底210中。NBL 220提供用于双极晶体管的低电阻集电极。P阱250提供用于形成P+基极260和N+发射极270的位置。将浮动P型掩埋层(PBL)230选择性添加到NBL 220与P阱250之间的N阱240中。NBL 220的连接形成用于衬底210中的NPN双极晶体管的集电极连接280。当相比于较深P阱配置时,选择性添加浮动PBL 230降低与NPN单元200相关联的寄生电容。
浮动PBL 230允许通过控制(a)P阱250与N型槽之间的空间或者(b)浮动PBL 230与N型槽之间的空间来独立调谐击穿电压。在ESD事件期间,集电极上的高电压使得P阱250-N阱240与PBL 230-N阱240之间的耗尽区域扩大,其使得P阱250和PBL 230穿通到彼此。这使得集电极基极耗尽区域边界从P阱250-N阱240接合处移动到PBL 230-NBL 220接合处。在例如PBL 250的缺少P型掩埋层的晶体管中,在高电流下,由于基极推出效应,P阱与NBL之间的所有N阱区域被耗尽,这使得触发电压升高,产生强突返行为,例如从32V到23V,如图1B所示。强突返和固有非均一性高电流基极推出效应使得电流变得非均一,从而引起丝状传导。根据一实施例,通过添加P型掩埋层(例如,PBL 250),基极推出的量显著减少,其产生较均一的电流且产生有效的ESD管理。
各种层的特定形状和宽度出于举例的目的示出。然而,各种层的形状和宽度可经调整以确定NPN晶体管单元的特定击穿电压。举例来说,根据一实施例,PBL 230的宽度可大体上发射极270的宽度相同(例如,在发射极270的宽度的10%范围内)。PBL 230和发射极270的宽度中的容限可基于PBL掩模与近表面掺杂之间的排列。根据另一实施例,P阱250的宽度可经横向扩展以调节P阱与N型槽之间的空间,因此提供特定击穿电压。根据又一实施例,P阱250的宽度可小于PBL 230。此外,各种层的形状和宽度可单独地或以其组合修改以针对给定应用提供所要的击穿电压。
根据另一实施例,可调谐N阱240(例如,P阱250下方的区域)中的掺杂含量或PBL层230(例如,更接近N阱240的顶部区域)的掺杂含量,从而使得P阱250可在地狱双极装置的保持电压的电压下“穿通”PBL层230,产生有效的ESD控制。掺杂含量可基于半导体装置的给定几何构型而选择。上文所定义的所选择区域中的掺杂含量可经调整以允许ESD电流以最小电阻朝向PBL层230“穿通”P阱250,因此允许垂直电流而不影响NPN晶体管单元200的其余部分。根据另一实施例,PBL层230可选择性植入在给定衬底210中的任何处,以在低于保持电压的电压下将电流引导到所选择的方向,因此改善NPN晶体管单元200的ESD弹性特征。
特定掺杂剂类型出于举例的目的示出。然而,可将每一层(例如,P衬底、PNP晶体管中的N型掩埋层等)的导电率和掺杂剂类型颠倒以提供单元的相反极性。举例来说,所有N型掺杂剂可用P型掺杂剂替换,且所有P型掺杂剂可用N型掺杂剂替换,以通过在装置内将电流引导到垂直方向上来实现类似ESD事件管理,因此提供改善的脉冲宽度可伸缩性。
图2B展示根据一实施例的PNP双极晶体管单元结构205的实例截面图。PNP双极晶体管单元205的结构和功能类似于NPN双极晶体管单元200,除将PNP双极晶体管单元205中的掺杂剂颠倒以提供PNP晶体管单元结构之外。PNP单元205包含衬底215、P型掩埋层(PBL)225和N阱255,其提供N+基极265和P+发射极275。将浮动N型掩埋层(NBL)235选择性添加到在PBL 225上方且在N阱255的下方的P阱245中。PBL 225的连接在衬底215中形成PNP双极晶体管单元205的集电极285。如本文以上所述,PNP晶体管205的功能性方面类似于NPN晶体管单元200,其中颠倒掺杂剂且颠倒极性。
出于举例目的,PBL 230(NBL 220)展示于整个NBL 220的上方。然而,PBL 230(NBL220)还可被选择性放置在NBL 220的部分上。举例来说,PBL 230(NBL 220)可仅部分被放置在N型槽280(P型槽)下方且在NBL 220(PBL 225)上方,而在N型收器(P型槽)中具有断层。此外,还可根据NPN(PNP)单元的特定实施方案来调整PBL 230(NBL 220)的大小。可实施例如图2A和图2B中说明的一个的P型掩埋(正型掩埋)双极NPN(PNP)晶体管单元结构以管理半导体装置中的ESD击穿电流。举例来说,例如图2A中所说明的一个的P型掩埋双极NPN晶体管可与装置电路并联连接以为所述装置电路提供ESD保护。
图2C展示根据一实施例的集成电路中的用于对P型掩埋双极NPN电晶体进行ESD管理的实例实施方案电路207。电路207包含P型掩埋NPN双极晶体管286,例如图2A中所说明的NPN单元200。NPN双极晶体管286可与需要ESD保护的装置电路288并联连接。装置电路288可为与可用作装置电路288的外部组件的包含NPN双极晶体管286或NPN双极晶体管286的一个集成在同一衬底中的任何电路。NPN双极晶体管286包含集电极C、基极B,和发射极E。NPN双极晶体管286的集电极C与装置电路288连接在衬垫290上。衬垫290为电路207的ESD衬垫,且其可经放置以接收且吸收电路207的ESD电流注入。NPN双极晶体管286的基极B与发射极E连接在衬垫292处。基极B可与发射极E直接连接或者任选地通过适合的电阻器R连接。在ESD事件期间,NPN双极晶体管286通过快速击穿来吸收静电电荷电流以为ESD电流提供最低电阻垂直电流路径,因此避免装置电路288被ESD充电电流引起潜在损坏。
图2D展示根据一实施例的实例发射线脉冲宽度(TLP)测量值(例如,具有P型掩埋层的NPN双极晶体管单元结构的测量值,例如NPN单元结构200的测量值)。如所说明,随着脉冲宽度增大,将装置的基极仅推按到P型掩埋层,例如如图2A所示的PBL 230,其产生有效的垂直电流。
图3A展示根据一实施例的实例NPN双极晶体管单元200的TCAD模拟温度曲线。如所说明,NPN双极晶体管单元200中的大量电流流动穿过垂直NPN结构,产生平衡的温度曲线。这展示了所要的垂直方向中的电流。
图3B展示根据一实施例的晶体管200的实例TCAD电子密度曲线。如所说明,大部分电子流在发射极的下方,其表明NPN双极晶体管的区域经最佳地用于传导电流和散热。
如上文所述,在常规ESD实施方案中,静电电荷电流可非均一地流动,产生降低的ESD鲁棒性,尤其对于较长脉冲宽度。根据上文解释的各种实施例,可通过选择性植入P型掩埋(或N型掩埋)层来使得静电电荷电流更均一,从而提高装置的鲁棒性。
本公开容易地用作设计或修改用于相同目的的其它工艺和结构和实现本文中所介绍的各种实施例的相同优点的根据。此类等效构造并不脱离本公开的精神和范围。在不脱离本公开的精神和范围的情况下,可对本文做出各种改变、替代和更改。
虽然已以针对结构特征或方法动作的措辞描述本主题,但是上文所描述的特定特征和动作是作为实施方案的的实例形式公开。本文提供实施例的各种操作。描述一些或所有所述操作的次序不应解释为暗示这些操作必然依赖于次序。应理解替代排序具有本说明书的益处。此外,在一些实施例中,一些操作为任选的(而非必需的)。
尤其对于通过上述组件(例如,元件、资源)来进行的各种功能来说,除非另外指明,否则用以描述此类组件的术语意欲对应于进行所描述组件的指定功能(例如,功能上等效的)的任何组件,即使结构上不等效于所公开的结构。此外,虽然可能已相对于若干实施方案中的仅一个来公开本公开的特定特征,但是可将此类特征与另一实施方案的一或多个其它特征组合为对于给定应用所要的且有利的。
对所描述的实施例的修改是可能的,且在权利要求书的范围内的其它实施例是可能的。
Claims (17)
1.一种半导体装置,其包括:
衬底;
形成于所述衬底中的N型掩埋层;
形成于所述N型掩埋层上方的N阱层;
形成于所述N阱层内的P阱层;和
形成于所述N阱层内在所述N型掩埋层的上方且在所述P阱层下方的P型掩埋层。
2.根据权利要求1所述的半导体装置,其进一步包括:
扩散于所述P阱层中且形成双极晶体管的基极的P+区域;和
扩散于所述P阱层中且形成所述双极晶体管的发射极的N+区域。
3.根据权利要求2所述的半导体装置,其中所述N型掩埋层形成所述双极晶体管的集电极。
4.根据权利要求1所述的半导体装置,其中所述P型掩埋层的宽度大体上与所述P阱层的宽度相同。
5.根据权利要求2所述的半导体装置,其中所述P型掩埋层的宽度大体上与所述双极晶体管的所述发射极的宽度相同。
6.根据权利要求4所述的半导体装置,其中所述P型掩埋层的宽度对应于所述双极晶体管的击穿电压。
7.根据权利要求1所述的半导体装置,其中所述P型掩埋层的宽度大于所述P阱层的宽度。
8.一种集成电路,其包括:
衬底;
定位于所述衬底中的N型掩埋层;
定位于所述N型掩埋层上方的N阱层;
定位于所述N阱层内的P阱层;
定位于所述N阱层内在所述N型掩埋层的上方且在所述P阱层下方的P型掩埋层;和
双极晶体管,其包含:扩散于所述P阱层中的P+区域中的基极;扩散于所述P阱层中的所述N+区域中的发射极;和延伸到所述N型掩埋层的集电极。
9.根据权利要求8所述的集成电路,其中所述P型掩埋层的宽度大体上与所述P阱层的宽度相同。
10.根据权利要求8所述的集成电路,其中所述P型掩埋层的宽度大体上与所述N+区域的宽度相同。
11.根据权利要求8所述的集成电路,其中所述P型掩埋层的宽度对应于所述双极晶体管的击穿电压。
12.根据权利要求8所述的集成电路,其中所述P型掩埋层的宽度大于所述P阱层的宽度。
13.一种静电放电装置,其包括:
衬底;
定位于所述衬底中的N型掩埋层;
定位于所述N型掩埋层上方的N阱层;
定位于所述N阱层内的P阱层;
定位于所述N阱层内在所述N型掩埋层的上方且在所述P阱层下方的P型掩埋层;和
具有双极晶体管的双极互补金属氧化物半导体BiCMOS电路,所述双极晶体管具有:扩散于所述P阱层中的P+区域中的基极;扩散于所述P阱层中的所述N+区域中的发射极;和延伸到所述N型掩埋层的集电极。
14.根据权利要求13所述的静电放电装置,其中所述P型掩埋层的宽度大体上与所述P阱层的宽度相同。
15.根据权利要求13所述的静电放电装置,其中所述P型掩埋层的宽度大体上与所述双极晶体管的所述N+区域的宽度相同。
16.根据权利要求13所述的静电放电电路,其中所述P型掩埋层的宽度对应于所述双极晶体管的击穿电压。
17.根据权利要求13所述的静电放电装置,其中所述P型掩埋层的宽度大于所述P阱层的宽度。
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