CN108346667B - 一种ltps背板制作方法以及ltps背板结构 - Google Patents
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- 238000000638 solvent extraction Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
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- 238000001816 cooling Methods 0.000 description 1
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- 239000000463 material Substances 0.000 description 1
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- 238000012986 modification Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
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Abstract
本发明涉及LTPS制作技术领域,尤其涉及一种LTPS背板制作方法,包括以下步骤:将所述基板分为驱动区域和显示区域;在所述基板上淀积SiNX层,再蚀刻显示区域的SiNX层;在所述基板上再淀积SiNX层,令所述基板上的驱动区域和显示区域覆盖形成台阶状的SiNX层;在所述基板上淀积SiO2层,再蚀刻驱动区域的SiO2层;在所述基板上淀积SiO2层,令所述基板上的SiO2层呈平整的端面,令驱动区域SiNX/SiO2膜厚比大于显示区域SiNX/SiO2膜厚比。本发明的发明目的在于提供一种LTPS背板制作方法,采用本发明提供的技术方案解决了现有LTPS无法同时满足外围驱动区域的TFT具有良好的开关特性和像素显示区域的TFT具有较佳的均匀性和可靠性的技术问题。
Description
技术领域
本发明涉及LTPS制作技术领域,尤其涉及一种LTPS背板制作方法以及LTPS背板结构。
背景技术
低温多晶硅技术LTPS(Low Temperature Poly-silicon)最初是为了降低Note-PC显示屏的能耗,令Note-PC显得更薄更轻而研发的技术。
在LTPS的制造中,通常希望外围驱动区域的TFT具有较好的开关比,较小的亚阈值摆幅,从而获得良好的开关特性,这可以通过较大的多晶硅晶粒而获得;同时希望像素显示区域的TFT具有较小的漏电流,较佳的可靠性和均匀性,这需要通过相对较小的多晶硅晶粒而达到。
因为晶粒的增大往往使得多晶硅表面粗糙,导致漏电流增大,栅极与沟道间绝缘性变差且均匀性不佳。因此,通常的ELC一次结晶难以同时优化驱动区域和显示区域的TFT特性。
发明内容
本发明的发明目的在于提供一种LTPS背板制作方法以及LTPS背板结构,采用本发明提供的技术方案解决了现有LTPS无法同时满足外围驱动区域的TFT具有良好的开关特性和像素显示区域的TFT具有较佳的可靠性的技术问题。
为了解决上述技术问题,本发明一方面提供一种LTPS背板制作方法,包括以下步骤:
1)、将基板分为驱动区域和显示区域;
2)、在所述基板上淀积SiNX层,再蚀刻显示区域的SiNx层;
3)、在所述基板上再淀积SiNX层,令所述基板上的驱动区域和显示区域覆盖形成台阶状的SiNX层;
4)、在所述基板上淀积SiO2层,再蚀刻驱动区域的SiO2层;
5)、在所述基板上淀积SiO2层,令所述基板上的SiO2层呈平整的端面,令驱动区域SiNX/SiO2膜厚比大于显示区域SiNX/SiO2膜厚比。
优选的,在步骤2和4中,采用PEVCD工艺完成SiNX层和SiO2层的淀积。
优选的,在步骤2和4中,采用成像、湿刻或干刻工艺完成蚀刻。
优选的,步骤5中在所述基板的SiO2层形成平整的端面后,在SiO2层沉积一层非晶硅层;通过去氢、ELC晶化后在驱动区域和显示区域形成晶粒大小不同的多晶硅。
优选的,重复一遍步骤1-5。
基于上述任一项所述制作方法,本发明另一方面还提供一种LTPS背板结构,包括具有驱动区域和显示区域的基板;在所述驱动区域和显示区域上均自下而上依次形成有SiNX层和SiO2层,且所述驱动区域的SiNX/SiO2膜厚比大于显示区域的SiNX/SiO2膜厚比。
优选的,在所述SiO2层的上方形成有多晶硅层。
由上可知,应用本发明可以得到以下有益效果:本发明针对TFT的SiNX/SiO2双层缓冲层结构,在驱动区域和显示区域采用不同厚度比例的SiNX/SiO2膜层结构,在ELC一次结晶工艺不做调整的情况下,同时满足驱动区域的TFT具有较好的开关比,较大的迁移率,从而获得良好的开关特性,以及显示区域的TFT具有较小的漏电流,较佳的可靠性,同时优化驱动区域和显示区域的TFT特性,以达到不同区域对TFT特性的不同要求。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对本发明实施例或现有技术的描述中所需要使用的附图作简单地介绍。显而易见地,下面描述中的附图仅仅是本发明的一部分实施例,对于本领域普通技术人员来讲,在不付出创造性劳动性的前提下,还可以根据这些附图获得其他的附图。
图1为本发明实施例工艺演化图;
图2为本发明实施例制作方法流程框图。
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述。显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
在LTPS的制造中,通常希望外围驱动区域的TFT具有较好的开关比,从而获得良好的开关特性,这可以通过较大的多晶硅晶粒而获得;同时希望像素显示区域的TFT具有较小的漏电流,较佳的可靠性,这需要通过相对较小的多晶硅晶粒而达到。因为晶粒的增大往往使得多晶硅表面粗糙,导致漏电流增大,栅极与沟道间绝缘性变差。因此,通常的ELC一次结晶难以同时优化驱动区域和显示区域的TFT特性。
为了解决上述技术问题,本实施例提供一种LTPS背板制作方法,在ELC一次结晶工艺不做调整的情况下,仅改变SiNX/SiO2双层缓冲结构,无需增加新的工艺、材料或设备,即可同时优化驱动区域和显示区域的TFT特性,以达到不同区域对TFT特性的不同要求。
请参见图1-2,具体包括以下步骤:
S101、将基板分为驱动区域和显示区域。
由于本发明的发明目的在于同时优化驱动区域和显示区域的TFT特性,以达到不同区域对TFT特性的不同要求,即需要同时在驱动区域和显示区域上完成不同的TFT特性优化工序,因此在该步骤中预先对基板进行分区,分为驱动区域和显示区域。
在分区过程中,根据LTPS背板产品的要求进行分区,分区在不破坏基板上顶面的基础上完成,可通过辅具完成驱动区域和显示区域的分区。
在分区完成后,需要依次在基板上形成SiNX/SiO2双层缓冲结构以及非晶硅淀积与晶化工序。
据此,本实施例提供的技术方案还包括以下步骤:
SiNX/SiO2双层缓冲结构的形成:
S102、在基板上淀积SiNX层,再蚀刻显示区域的SiNX层。
作为一种实施方式,利用PEVCD工艺,在基板上淀积SiNX层。
作为另一种实施方式,再利用成像、湿刻或干刻工艺,将显示区域的SiNX层全部蚀刻掉,形成结构如图1所示,从上到下依次为SiNX和基板。
S103、在基板上再淀积SiNX层,令基板上的驱动区域和显示区域覆盖形成台阶状的SiNX层。
该步骤完成后,使得基板上的驱动区域和显示区域均覆盖有SiNX层,区别在于驱动区域上的SiNX层厚度大于显示区域上的SiNX层厚度。
S104、在基板上淀积SiO2层,再蚀刻驱动区域的SiO2层。
在优选的一种实施方式中,采用与步骤S102相同的方式淀积SiO2层以及蚀刻掉驱动区域的SiO2层。
S105、在基板上淀积SiO2层,令基板上的SiO2层呈平整的端面。
由于在S104中将驱动区域的SiO2层蚀刻掉,在蚀刻掉驱动区域的SiO2层后,需再次淀积一层SiO2,最终形成的结构如图1所示,从上到下依次为:SiO2、SiNX和基板,并且驱动区域的SiNX/SiO2膜厚比大于显示区域的SiNX/SiO2膜厚比。
在完成SiNX/SiO2双层缓冲结构后,还需进行非晶硅淀积与晶化工序,还包括以下步骤:
S106、在步骤S105中在基板的SiO2层形成平整的端面后,在SiO2层沉积一层非晶硅层;通过去氢、ELC晶化后在驱动区域和显示区域形成晶粒大小不同的多晶硅。
根据得到的多晶粒大小,分别调整驱动区域与显示区域的SiNX/SiO2膜厚比,再重复一遍步骤S101-S106,最终能够同时优化驱动区域和显示区域的TFT特性。
基于上述LTPS背板制作方法,本实施例还提供一种LTPS背板结构,包括具有驱动区域和显示区域的基板;在驱动区域和显示区域上均自下而上依次形成有SiNX层和SiO2层,且驱动区域的SiNX/SiO2膜厚比大于显示区域的SiNX/SiO2膜厚比。
在一个实施方式中,在SiO2层的上方形成有多晶硅层。
通过本实施例提供的制作方法得到的LTPS背板,在LTPS背板中的SiNX/SiO2双层缓冲层不仅能阻挡来自基板的污染物,而且在激光晶化中扮演着重要角色。其中SiNx能降低热传导,减缓ELC时被激光加热的硅的冷却速度,有助于形成比较大的结晶晶粒;而SiO2虽然湿润角远大于SiNX,不利于形成较大的晶粒,但却更有助于形成<100>晶格方向的均匀薄膜。综上,通过调整SiNX/SiO2的膜厚比可以影响ELC的晶化效果。
本发明针对TFT的SiNX/SiO2双层缓冲层结构,在驱动区域和显示区域采用不同厚度比例的SiNX/SiO2膜层结构,保持驱动区域的SiNX/SiO2膜厚比大于显示区域的SiNX/SiO2膜厚比,可以使得驱动区域得到更大的晶粒,而显示区域晶粒更为均匀,结晶后的表面更为平整。在ELC一次结晶工艺不做调整的情况下,同时满足驱动区域的TFT具有较好的开关比,较大的迁移率,从而获得良好的开关特性,以及显示区域的TFT具有较小的漏电流,较佳的可靠性,同时优化驱动区域和显示区域的TFT特性,以达到不同区域对TFT特性的不同要求。
以上所述的实施方式,并不构成对该技术方案保护范围的限定。任何在上述实施方式的精神和原则之内所作的修改、等同替换和改进等,均应包含在该技术方案的保护范围之内。
Claims (7)
1.一种LTPS背板制作方法,其特征在于:包括以下步骤:
1)、将基板分为驱动区域和显示区域;
2)、在所述基板上淀积SiNX层,再蚀刻显示区域的SiNX层;
3)、在所述基板上再淀积SiNX层,令所述基板上的驱动区域和显示区域覆盖形成台阶状的SiNX层;
4)、在所述基板上淀积SiO2层,再蚀刻驱动区域的SiO2层;
5)、在所述基板上淀积SiO2层,令所述基板上的SiO2层呈平整的端面,令驱动区域SiNX/SiO2膜厚比大于显示区域SiNX/SiO2膜厚比。
2.根据权利要求1所述的一种LTPS背板制作方法,其特征在于:在步骤2和4中,采用PEVCD工艺完成SiNX层和SiO2层的淀积。
3.根据权利要求2所述的一种LTPS背板制作方法,其特征在于:在步骤2和4中,采用成像、湿刻或干刻工艺完成蚀刻。
4.根据权利要求3所述的一种LTPS背板制作方法,其特征在于:步骤5中在所述基板的SiO2层形成平整的端面后,在SiO2层沉积一层非晶硅层;通过去氢、ELC晶化后在驱动区域和显示区域形成晶粒大小不同的多晶硅。
5.根据权利要求4所述的一种LTPS背板制作方法,其特征在于:重复一遍步骤1-5。
6.一种基于权利要求1-5中任一项所述的LTPS背板制作方法的LTPS背板结构,其特征在于:包括具有驱动区域和显示区域的基板;在所述驱动区域和显示区域上均自下而上依次形成有SiNx层和SiO2层,且所述驱动区域的SiNX/SiO2膜厚比大于显示区域的SiNX/SiO2膜厚比。
7.根据权利要求6所述的LTPS背板结构,其特征在于:在所述SiO2层的上方形成有多晶硅层。
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