CN108321082A - 半导体装置的制造方法 - Google Patents

半导体装置的制造方法 Download PDF

Info

Publication number
CN108321082A
CN108321082A CN201711383678.2A CN201711383678A CN108321082A CN 108321082 A CN108321082 A CN 108321082A CN 201711383678 A CN201711383678 A CN 201711383678A CN 108321082 A CN108321082 A CN 108321082A
Authority
CN
China
Prior art keywords
layer
high concentration
light absorbing
absorbing layer
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201711383678.2A
Other languages
English (en)
Inventor
西胁刚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyota Motor Corp
Original Assignee
Toyota Motor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyota Motor Corp filed Critical Toyota Motor Corp
Publication of CN108321082A publication Critical patent/CN108321082A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02592—Microstructure amorphous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
    • H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
    • H01L27/0652—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
    • H01L27/0664—Vertical bipolar transistor in combination with diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
    • H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Ceramic Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Optics & Photonics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Electromagnetism (AREA)
  • Recrystallisation Techniques (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本发明提供一种半导体装置的制造方法，抑制在向半导体基板的表面照射光来激活杂质时半导体基板背面的温度上升。在光吸收层形成工序中，在具有表面和背面的半导体基板的表面上或内部形成光吸收率高于相邻半导体层的光吸收率的光吸收层。在此，以使光吸收层分布在比背面接近表面的范围内的方式形成光吸收层。在高浓度层形成工序中，通过向半导体基板注入杂质而形成杂质浓度上升的高浓度层。在加热工序中，通过对高浓度层进行加热而激活高浓度层内的杂质。光吸收层形成工序和高浓度层形成工序以使光吸收层与高浓度层至少局部重叠的方式实施。在对高浓度层进行加热的工序中，通过从表面侧朝着高浓度层照射光而对高浓度层进行加热。

Description

半导体装置的制造方法
技术领域
本说明书公开的技术涉及半导体装置的制造方法。
背景技术
专利文献1公开了一种技术，向半导体基板的表面注入杂质，然后向该表面照射激光，由此激活注入到半导体基板上的杂质。而且，在该技术中，通过向半导体基板的表面照射脉冲宽度不同的两种激光，来抑制半导体基板的背面(被照射光的半导体基板的与表面相反一侧的面)的温度上升。
在先技术文献
专利文献1：日本特开2014-036110号公报
发明内容
发明要解决的课题
近年来，半导体基板越发薄型化。因此，在通过照射光来激活半导体基板内的杂质时，背面的温度容易上升。因此，在本说明书中，提供另一种技术，在向半导体基板的表面照射光来激活杂质时，能够良好地抑制半导体基板的背面的温度上升。
用于解决课题的方案
本说明书公开的半导体装置的制造方法具有光吸收层形成工序、高浓度层形成工序及加热工序。在上述光吸收层形成工序中，在具有表面和背面的半导体基板的上述表面上或内部形成光吸收率高于相邻半导体层的光吸收率的光吸收层。在此，以在形成了上述光吸收层之后的上述半导体基板中上述光吸收层分布在比上述背面接近上述表面的范围内的方式来形成上述光吸收层。在上述高浓度层形成工序中，通过向上述半导体基板注入杂质而形成杂质浓度上升的高浓度层。在上述加热工序中，通过对上述高浓度层进行加热而激活上述高浓度层内的杂质。上述光吸收层形成工序和上述高浓度层形成工序以使上述光吸收层与上述高浓度层至少局部重叠的方式实施。在对上述高浓度层进行加热的工序中，通过从上述表面侧朝着上述高浓度层照射光而对上述高浓度层进行加热。
另外，光吸收层可以形成在原来的半导体基板(形成光吸收层之前的半导体基板)的表面上，也可以形成在原来的半导体基板的内部。在原来的半导体基板的表面上形成光吸收层的情况下，将光吸收层和原来的半导体基板整体称为形成了光吸收层之后的半导体基板。即，形成了光吸收层之后的半导体基板包含光吸收层。
另外，光吸收层形成工序和高浓度层形成工序哪个先实施均可。在光吸收层形成工序之后实施高浓度层形成工序的情况下，高浓度层只要是与光吸收层至少局部重叠的范围即可，可以形成于任意范围。例如，高浓度层可以仅形成于光吸收层的内部，高浓度层也可以横跨光吸收层的内部和外部地形成。而且，在高浓度层形成工序之后实施光吸收层形成工序的情况下，光吸收层只要是与高浓度层至少局部重叠的范围即可，可以形成于任意范围。例如，光吸收层可以仅形成于高浓度层的内部，光吸收层也可以横跨高浓度层的内部和外部地形成。
在该制造方法中，在加热工序中，从半导体基板的表面侧朝着高浓度层照射光。照射的光在光吸收层中被高效地吸收，光吸收层被高效地加热。由于光吸收层与高浓度层至少局部重叠，因此高浓度层也被高效地加热。这样，高浓度层被高效地加热，激活了高浓度层内的杂质。而且，光吸收层中的光的吸收率高，因此到达比光吸收层靠背面侧的位置的光较少。因此，抑制了比光吸收层靠背面侧的位置的温度上升。因此，能抑制半导体基板的背面的温度上升。因此，根据该制造方法，能够在抑制背面的温度上升的同时，激活高浓度层内的杂质。
附图说明
图1是半导体装置的剖视图。
图2是形成了上表面侧的构造之后的半导体基板的剖视图。
图3是高浓度层形成工序的说明图(下表面附近的放大剖视图。)。
图4是表示高浓度层内的n型杂质浓度分布的曲线图。
图5是非晶层形成工序的说明图(下表面附近的放大剖视图)。
图6是非晶层形成工序的说明图(下表面附近的放大剖视图)。
图7是高浓度层形成工序的说明图(下表面附近的放大剖视图)。
具体实施方式
【实施例】
图1示出通过后述的实施例1、2的制造方法制造的半导体装置10。半导体装置10具有：半导体基板12、上部电极14及下部电极16。半导体基板12由单晶硅构成。上部电极14与半导体基板12的上表面12a相接。下部电极16与半导体基板12的下表面12b相接。半导体基板12具有作为IGBT(绝缘栅双极型晶体管)进行动作的IGBT区域20和作为二极管进行动作的二极管区域40。在IGBT区域20内的IGBT进行动作时，上部电极14作为发射极发挥作用，下部电极16作为集电极发挥作用。在二极管区域40内的二极管进行动作时，上部电极14作为阳极发挥作用，下部电极16作为阴极发挥作用。在IGBT区域20的内部的上表面12a侧的范围设有n型的源区、p型的体区、沟槽栅电极等。在二极管区域40的内部的上表面12a侧的范围设有p型的阳极区等。IGBT区域20和二极管区域40的上表面12a侧的构造是以往公知的，因此省略详细的说明。
在半导体基板12的内部的下表面12b侧的范围设有漂移层27、缓冲层28、集电层30及阴极层44。漂移层27是n型杂质浓度低的n型层。漂移层27横跨IGBT区域20和二极管区域40地分布。缓冲层28是n型杂质浓度高于漂移层27的n型层。缓冲层28配置在漂移层27的下侧。缓冲层28横跨IGBT区域20和二极管区域40地分布。集电层30是p型层。集电层30配置在IGBT区域20内的缓冲层28的下侧。集电层30在下表面12b与下部电极16进行欧姆接触。阴极层44是n型杂质浓度高于缓冲层28的n型层。阴极层44配置在二极管区域40内的缓冲层28的下侧。阴极层44在下表面12b与下部电极16进行欧姆接触。
【实施例1】
接下来，说明实施例1的制造方法。首先，准备由n型的单晶硅构成的半导体基板12。接下来，如图2所示，通过以往公知的方法，形成半导体装置10的上表面12a侧的构造。接下来，在上部电极14的表面粘贴保护带60。接下来，通过对半导体基板12的下表面12b进行研磨而使半导体基板12薄型化。在该阶段，半导体基板12的厚度成为140μm以下。而且，在该阶段，漂移层27露出于半导体基板12的下表面12b。
接下来，如图3所示，将n型杂质(在本实施方式中为磷)从下表面12b向半导体基板12的内部进行离子注入。在此，以使n型杂质的平均停止位置为距下表面12b约2μm的深度的方式注入n型杂质。由此，在半导体基板12的内部形成n型杂质浓度比注入前上升的高浓度层70。图4示出高浓度层70的内部及其周边的n型杂质浓度分布。图4的纵轴所示的n型杂质浓度与通过n型杂质注入而上升的n型杂质的上升量大致相等。如图4所示，以深度约2μm的位置为中心，在从深度约1μm至深度约3μm的范围内形成高浓度层70。而且，在深度约2μm的位置形成高浓度层70的n型杂质浓度的峰值P1。以下，将高浓度层70中的具有峰值P1的10％以上的n型杂质浓度的层称为主要层72。
接下来，如图5所示，从下表面12b向半导体基板12的内部注入非活性离子(在本实施例中为硅)。在此，以使注入的非活性离子的平均停止位置为距下表面12b约2μm的深度的方式注入非活性离子。在非活性离子的停止位置形成晶体缺陷。在此，以8×1014cm-2以上的剂量注入非活性离子。当这样以高剂量注入非活性离子时，在该平均停止位置周边，半导体基板(即，单晶硅)的晶体性被破坏，而形成非晶层76(即，非晶硅)。非晶层76具有比与非晶层76相邻的半导体层(具有晶体性的半导体层)高的光吸收率。而且，非晶层76具有比与非晶层76相邻的半导体层(具有晶体性的半导体层)低的导热率。如图4、5所示，非晶层76以与n型杂质浓度的峰值P1的深度重叠的方式形成。而且，非晶层76以其整体包含于高浓度层70的主要层72的方式形成。
接下来，向相当于阴极层44的范围内注入n型杂质(在本实施例中为硼)，向相当于集电层30的范围内注入p型杂质(在本实施例中为磷)。
接下来，向半导体基板12的下表面12b照射IR激光(红外线激光)。IR激光是波长为约808nm的激光。室温下的IR激光对于单晶硅的穿透深度为约10.7μm。另外，穿透深度是当将表面的激光的能量设为1时，激光的能量衰减至1/e(e≈2.718)的深度。IR激光的穿透深度比非晶层76的深度(约2μm)长，因此向下表面12b照射的激光到达非晶层76。
如上所述，非晶层76的光吸收率高。因此，在非晶层76中高效地吸收激光，非晶层76被高效地加热。因此，与非晶层76重叠的范围中的高浓度层70被高效地加热。而且，与非晶层76相邻的范围中的高浓度层70也由于来自非晶层76的导热或激光的吸收而被加热。因此，高浓度层70整体被加热至高温。
另外，由于在非晶层76内激光被吸收，因此在非晶层76内激光急剧衰减。因此，激光几乎不会到达比非晶层76靠上表面12a侧的位置。而且，由于非晶层76的导热率低，因此热量难以传递到比非晶层76靠上表面12a侧的位置。因此，抑制了上表面12a的温度上升。
这样，通过设置非晶层76，能够抑制上表面12a的温度上升，并且能够有效地对非晶层76及高浓度层70进行加热。通过抑制上表面12a的温度上升，能抑制保护带60和上部电极14的劣化。而且，通过抑制上表面12a的温度上升，能抑制上表面12a侧的范围的半导体层内的杂质扩散，能够以稳定的特性制造半导体装置10。而且，当非晶层76被加热时，非晶层76进行结晶。非晶层76的大致整体在IR激光的照射中进行结晶。而且，在高浓度层70内，通过加热而在电学性质上激活n型杂质。由此，形成n型的缓冲层28。
接下来，通过向半导体基板12的下表面12b照射绿色激光而对半导体基板12的下表面12b附近的范围进行加热。绿色激光是波长为约532nm的激光。室温下的绿色激光对于单晶硅的穿透深度为约0.96μm。绿色激光对于单晶硅的穿透深度较短，因此下表面12b附近的表层部被高效地加热。由此，激活被注入到该表层部的p型杂质和n型杂质。由此，形成集电层30和阴极层44。
然后，以覆盖下表面12b的方式形成下部电极16，并去除保护带60从而完成图1的半导体装置10。由于保护带60未曝露在高温下，因此保护带60未产生性质变化。因此，能够良好地去除保护带60。
另外，在上述实施例1中，以使n型杂质浓度的峰值P1的位置与非晶层76的位置重叠且非晶层76包含于高浓度层70的主要层72的方式形成了非晶层76。然而，只要形成为非晶层76的至少一部分与高浓度层70的至少一部分重叠即可，形成非晶层76的范围可以适当变更。只要形成为非晶层76的至少一部分与高浓度层70的至少一部分重叠，就能够高效地对高浓度层70进行加热，并能够抑制上表面12a的温度上升。例如，可以将非晶层76设置在主要层72的外部的高浓度层70的内部。而且，例如，非晶层76也可以横跨高浓度层70的内部和高浓度层70的外部地设置。但是，当如实施例1那样以使n型杂质浓度的峰值P1的位置与非晶层76的位置重叠且非晶层76包含于高浓度层70的主要层72的方式形成非晶层76时，能够更高效地对高浓度层70进行加热。因此，能够以较少的能量加热高浓度层70，可以减少向半导体基板12赋予的热量，因此能够进一步抑制上表面12a的温度上升。
另外，在上述实施例1中，在形成了高浓度层70之后形成非晶层76，但也可以在形成了非晶层76之后形成高浓度层70。
【实施例2】
接下来，说明实施例2的制造方法。在实施例2的制造方法中，与实施例1的制造方法相同，得到图2的构造。接下来，如图6所示，在半导体基板12的下表面12b上生长由非晶硅构成的非晶层76。例如，能够通过LPCVD(Low Pressure Chemical Vapor Deposition：低压化学气相沉积法)、等离子体CVD或光CVD等生长非晶层76。在此，形成3μm以下厚度的非晶层76。另外，以下，将形成非晶层76前的半导体基板12和非晶层76一并称为半导体基板12。因此，将非晶层76的表面称为半导体基板12的下表面12b。
接下来，如图7所示，从下表面12b向非晶层76的内部注入n型杂质(在本实施方式中为磷)。在此，以使n型杂质的平均停止位置为距下表面12b约2μm的深度的方式注入n型杂质。由此，在非晶层76的内部形成n型杂质浓度高于注入前的高浓度层70。如图7所示，高浓度层70整体包含于非晶层76。
接下来，向非晶层76的表层部中的相当于阴极层44的范围注入n型杂质(在本实施例中为硼)，向非晶层76的表层部中的相当于集电层30的范围注入p型杂质(在本实施例中为磷)。
接下来，向半导体基板12的下表面12b照射IR激光(红外线激光)。在实施例2中，非晶层76露出于下表面12b，因此IR激光照射于非晶层76。由于非晶层76的光吸收率高，因此在非晶层76中激光被高效地吸收，非晶层76被高效地加热。因此，与非晶层76重叠的高浓度层70整体被高效地加热。
另外，在非晶层76内激光被吸收，因此在非晶层76内激光急剧衰减。因此，激光几乎不会到达比非晶层76靠上表面12a侧的位置。而且，由于非晶层76的导热率低，因此热量难以传递到比非晶层76靠上表面12a侧的位置。因此，能抑制上表面12a的温度上升。
这样，通过设置非晶层76，能够抑制上表面12a的温度上升，并能够高效地对非晶层76及高浓度层70进行加热。当非晶层76被加热时，非晶层76结晶化。而且，在高浓度层70内，通过加热而激活n型杂质。由此，形成n型的缓冲层28。
接下来，向半导体基板12的下表面12b照射绿色激光，由此对半导体基板12的下表面12b附近的范围进行加热。绿色激光对于单晶硅的穿透深度短，因此下表面12b附近的表层部被高效地加热。由此，激活注入到该表层部中的p型杂质和n型杂质。由此，形成集电层30和阴极层44。
然后，以覆盖下表面12b的方式形成下部电极16，并将保护带60去除，从而完成图1的半导体装置10。由于保护带60未曝露在高温下，因此保护带60未产生性质变化。因此，能够良好地去除保护带60。
另外，在上述实施例2中，高浓度层70整体包含于非晶层76的内部，但是高浓度层70也可以横跨非晶层70的内部和外部地分布。
另外，在上述实施例1、2中，通过激光对高浓度层70进行加热，但也可以通过激光以外的光对高浓度层70进行加热。
说明实施例的结构要素与权利要求的结构要素之间的关系。实施例中的半导体基板12的下表面12b是权利要求中的半导体基板的表面的一例。实施例中的半导体基板12的上表面12a是权利要求中的半导体基板的背面的一例。实施例中的非晶层76是权利要求中的光吸收层的一例。
以下列举本说明书公开的技术要素。另外，以下的各技术要素分别是独立地有用的要素。
在本说明书公开的一例的制造方法中，高浓度层具有主要层，该主要层具有高浓度层的杂质浓度上升量的峰值的10％以上的杂质浓度上升量。在此，可以是，形成光吸收层的工序和形成高浓度层的工序以使光吸收层与主要层至少局部地重叠的方式实施。
根据该结构，能够高效地对高浓度层的主要层进行加热。
在本说明书公开的一例的制造方法中，可以是，成光吸收层的工序和形成高浓度层的工序以使光吸收层的整体位于主要层内的方式实施。
根据该结构，能够更高效地对高浓度层的主要层进行加热。
在本说明书公开的一例的制造方法中，可以是，形成光吸收层的工序和形成高浓度层的工序以使高浓度层的杂质浓度上升量的峰值位置与光吸收层重叠的方式实施。
根据该结构，能够高效地对高浓度层的上述峰值的位置进行加热。
在本说明书公开的一例的制造方法中，可以是，光吸收层是通过向半导体基板注入非活性离子而使晶体缺陷密度上升的区域。
另外，作为非活性离子，可以使用例如硅、氦、氖、氩等。
在本说明书公开的一例的制造方法中，可以是，在对高浓度层进行加热的工序中，使光吸收层结晶。
根据该结构，能够制造出具有更良好的特性的半导体装置。
以上，详细地说明了实施方式，但是它们只不过是例示，对权利要求书没有限定作用。权利要求书记载的技术包括对以上例示的具体例进行了各种变形、变更的技术。本说明书或附图说明的技术要素是单独或者通过各种组合而发挥技术有用性的要素，不限定为申请时权利要求记载的组合。另外，本说明书或附图例示的技术是同时实现多个目的的技术，并且通过实现这些目的当中之一而具有技术有用性。
附图标记说明
10：半导体装置
12：半导体基板
14：上部电极
16：下部电极
20：IGBT区域
27：漂移层
28：缓冲层
30：集电层
40：二极管区域
44：阴极层
60：保护带
70：高浓度层
72：主要层
76：非晶层

Claims (8)

1.一种半导体装置的制造方法，包括：
在具有表面和背面的半导体基板的所述表面上或内部形成光吸收率高于相邻半导体层的光吸收率的光吸收层的工序，以在形成了所述光吸收层之后的所述半导体基板中所述光吸收层分布在比所述背面靠近所述表面的范围内的方式来形成所述光吸收层；
通过向所述半导体基板注入杂质而形成杂质浓度上升的高浓度层的工序；及
通过对所述高浓度层进行加热而激活所述高浓度层内的杂质的工序，
形成所述光吸收层的工序和形成所述高浓度层的工序以使所述光吸收层与所述高浓度层至少局部重叠的方式实施，
在对所述高浓度层进行加热的工序中，通过从所述表面侧朝着所述高浓度层照射光而对所述高浓度层进行加热。
2.根据权利要求1所述的半导体装置的制造方法，其中，
所述高浓度层具有主要层，所述主要层具有所述高浓度层的杂质浓度上升量的峰值的10％以上的杂质浓度上升量，
形成所述光吸收层的工序和形成所述高浓度层的工序以使所述光吸收层与所述主要层至少局部重叠的方式实施。
3.根据权利要求2所述的半导体装置的制造方法，其中，
形成所述光吸收层的工序和形成所述高浓度层的工序以使所述光吸收层整体位于所述主要层内的方式实施。
4.根据权利要求1～3中任一项所述的半导体装置的制造方法，其中，
形成所述光吸收层的工序和形成所述高浓度层的工序以使所述高浓度层的杂质浓度上升量的峰值的位置与所述光吸收层重叠的方式实施。
5.根据权利要求1～4中任一项所述的半导体装置的制造方法，其中，
所述光吸收层是通过向所述半导体基板注入非活性离子而使晶体缺陷密度上升的区域。
6.根据权利要求1～4中任一项所述的半导体装置的制造方法，其中，
所述光吸收层是在形成所述光吸收层之前的所述半导体基板的表面上生长而成的非晶层。
7.根据权利要求5或6所述的半导体装置的制造方法，其中，在对所述高浓度层进行加热的工序中，使所述光吸收层结晶。
8.根据权利要求1～7中任一项所述的半导体装置的制造方法，其中，
所述半导体基板是硅基板，
所述光吸收层是非晶硅层。
CN201711383678.2A 2016-12-22 2017-12-20 半导体装置的制造方法 Pending CN108321082A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2016-249472 2016-12-22
JP2016249472A JP2018107190A (ja) 2016-12-22 2016-12-22 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
CN108321082A true CN108321082A (zh) 2018-07-24

Family

ID=62510474

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201711383678.2A Pending CN108321082A (zh) 2016-12-22 2017-12-20 半导体装置的制造方法

Country Status (4)

Country Link
US (1) US10153168B2 (zh)
JP (1) JP2018107190A (zh)
CN (1) CN108321082A (zh)
DE (1) DE102017223597A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11205578B2 (en) * 2017-10-18 2021-12-21 Texas Instruments Incorporated Dopant anneal with stabilization step for IC with matched devices
US11652009B2 (en) * 2019-11-06 2023-05-16 International Business Machines Corporation Secure inspection and marking of semiconductor wafers for trusted manufacturing thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1452223A (zh) * 2002-04-16 2003-10-29 株式会社东芝 半导体装置及半导体装置的制造方法
JP2006344909A (ja) * 2005-06-10 2006-12-21 Sumitomo Heavy Ind Ltd レーザ照射装置及び半導体装置の製造方法
US20120178223A1 (en) * 2011-01-07 2012-07-12 Kabushiki Kaisha Toshiba Method of Manufacturing High Breakdown Voltage Semiconductor Device
CN103283006A (zh) * 2011-11-07 2013-09-04 松下电器产业株式会社 薄膜晶体管器件的制造方法、薄膜晶体管器件以及显示装置
JP2014195004A (ja) * 2013-03-29 2014-10-09 Sumitomo Heavy Ind Ltd 半導体素子の製造方法及び半導体素子の製造装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4455441B2 (ja) * 2005-07-27 2010-04-21 株式会社東芝 半導体装置の製造方法
JP2011243939A (ja) * 2010-01-20 2011-12-01 Panasonic Corp 窒化物半導体レーザ装置
JP6245678B2 (ja) 2012-08-08 2017-12-13 住友重機械工業株式会社 半導体装置の製造方法
US9679773B1 (en) * 2016-03-14 2017-06-13 Infineon Technologies Ag Method for thermal annealing and a semiconductor device formed by the method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1452223A (zh) * 2002-04-16 2003-10-29 株式会社东芝 半导体装置及半导体装置的制造方法
JP2006344909A (ja) * 2005-06-10 2006-12-21 Sumitomo Heavy Ind Ltd レーザ照射装置及び半導体装置の製造方法
US20120178223A1 (en) * 2011-01-07 2012-07-12 Kabushiki Kaisha Toshiba Method of Manufacturing High Breakdown Voltage Semiconductor Device
CN103283006A (zh) * 2011-11-07 2013-09-04 松下电器产业株式会社 薄膜晶体管器件的制造方法、薄膜晶体管器件以及显示装置
JP2014195004A (ja) * 2013-03-29 2014-10-09 Sumitomo Heavy Ind Ltd 半導体素子の製造方法及び半導体素子の製造装置

Also Published As

Publication number Publication date
JP2018107190A (ja) 2018-07-05
DE102017223597A1 (de) 2018-06-28
US20180182625A1 (en) 2018-06-28
US10153168B2 (en) 2018-12-11

Similar Documents

Publication Publication Date Title
US10847609B2 (en) Method of manufacturing a semiconductor device in which a lifetime of carriers is controlled
JP5741716B2 (ja) 半導体装置およびその製造方法
WO2016042954A1 (ja) 半導体装置および半導体装置の製造方法
JP6547724B2 (ja) 半導体装置の製造方法
JP2006351659A (ja) 半導体装置の製造方法
CN105280485B (zh) 制造包括场停止区的半导体器件的方法
JP2003059856A (ja) 半導体装置の製造方法
TWI331367B (en) Method of manufacturing semiconductor device
CN108321082A (zh) 半导体装置的制造方法
KR102478873B1 (ko) 디이프 접합 전자 소자 및 그의 제조 공정
JP4043865B2 (ja) レーザ照射を用いた半導体装置の製造方法
JP2001156299A (ja) 半導体装置及びその製造方法
US8324530B2 (en) Method for heating a wafer by means of a light flux
WO2011055691A1 (ja) 半導体装置の製造方法
US9564496B2 (en) Process for treating a substrate using a luminous flux of determined wavelength, and corresponding substrate
JP5751128B2 (ja) 半導体装置の製造方法
JP6756125B2 (ja) 半導体装置および半導体装置の製造方法
JP5675204B2 (ja) Ｉｇｂｔの製造方法
JP5751106B2 (ja) 半導体装置の製造方法
TWI521570B (zh) 半導體結構及其製造方法
TWI642092B (zh) 深接面電子裝置及其製造方法
JP2008135439A (ja) バイポーラ半導体装置とその製造方法
CN104716040B (zh) 有效降低功耗的igbt器件的制作方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20180724

WD01 Invention patent application deemed withdrawn after publication