CN108288610A - It a kind of design of novel chip tin tailing solder pad and its is applied in red adhesive process - Google Patents
It a kind of design of novel chip tin tailing solder pad and its is applied in red adhesive process Download PDFInfo
- Publication number
- CN108288610A CN108288610A CN201810357773.3A CN201810357773A CN108288610A CN 108288610 A CN108288610 A CN 108288610A CN 201810357773 A CN201810357773 A CN 201810357773A CN 108288610 A CN108288610 A CN 108288610A
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- Prior art keywords
- chip
- tin
- solder pad
- pin
- tailing solder
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13011—Shape comprising apertures or cavities, e.g. hollow bump
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13012—Shape in top view
- H01L2224/13015—Shape in top view comprising protrusions or indentations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13023—Disposition the whole bump connector protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1412—Layout
- H01L2224/14179—Corner adaptations, i.e. disposition of the bump connectors at the corners of the semiconductor or solid-state body
Abstract
The invention belongs to technical field of material, more particularly to a kind of novel chip tin tailing solder pad is designed and its is applied in red adhesive process.The design includes：(1) design (increase appropriate drag solder) of chip tin tailing solder pad size and length；(2) design of special fish shape and fish tail tin tailing solder pad；(3) chip center's stomata ensures that bottom does not generate air pressure generation offset when chip patch processing procedure；(4) chip pin tail portion square pads design.Present invention is generally directed to the encapsulation of the rectangular chip of intensive pin pitch and the red adhesive process of biserial pin integrated circuit chip-packaging structure and tin tailing solder pad design methods, rectangular chip applicatory and biserial pin integrated circuit chip pin quantitative range are wide, mainly ensure the reliability of rectangular chip wave-soldering by following method.
Description
Technical field
The invention belongs to technical field of material, more particularly to a kind of novel chip tin tailing solder pad designs and its in red glue
It is applied in technique.
Background technology
In electronics industry, in order to realize the function of circuit board, usually by with circuit printed circuit board and various electricity
Sub- component such as chip is electrically welded, and is formed with functional circuit board.Welding is the important procedure of circuit board, welding
Reliability is extremely important to the quality of circuit board.
However, with the development of science and technology, to obtain the market advantage, chip cost needs to reduce, and chip volume is increasingly
Small, pin number is more and more, causes current semicon industry chip pin pitch closer and closer；Using currently available technology, in wave
Peak welds in processing procedure, a problem that even tin, rosin joint often occurs, affects the quality and production efficiency of circuit board.
For example, CN104684250A discloses a kind of the ic chip package structure and encapsulation design of printed circuit board
Method, the encapsulating structure include the square patch IC chip of printed circuit board and installation on a printed circuit board, side
The pin of shape patch IC chip is welded with printed circuit board by wave-soldering mode, and the square patch ic core
The angle that the wherein a line of the four edges of piece is formed with wave-soldering chain moving direction is 30 ° to 60 °；In addition, in rectangular patch
Diagonally tin tailing solder pad is respectively set in piece IC chip four diagonal first diagonal, third diagonal sum the 4th.
CN104681458A discloses biserial pin integrated circuit chip-packaging structure and the encapsulation of a kind of printed circuit board
Design method, the encapsulating structure include the biserial pin integrated circuit core of printed circuit board and installation on a printed circuit board
Piece, biserial pin integrated circuit chip is parallel with wave-soldering chain moving direction on the side where each row pin, relative peaks
Chain moving direction is welded, biserial pin integrated circuit chip is respectively equipped with one and drags soldering in the end on side where each row pin
Disk.
Aforementioned two technical solution the problem is that：Red glue work is used in the following pin pitch chips of pin central span 0.65mm
Even weldering can not solve chip when skill.
Invention content
In view of the problems existing in the prior art, present invention is generally directed to the encapsulation of the red adhesive process of the rectangular chip of intensive pin pitch
And tin tailing solder pad method, rectangular chip pin number range applicatory is wide, is mainly ensured by following method rectangular
The reliability of chip wave-soldering：
(1) design (increase appropriate drag solder) of chip tin tailing solder pad size and length；
(2) design of special fish shape and fish tail tin tailing solder pad；
(3) chip center's stomata ensures that chip interior does not generate air pressure；
(4) chip pin tail portion square pads design.
Specifically, the present invention is achieved through the following technical solutions, a kind of novel chip tin tailing solder pad design, packet
It includes：
1.1 chips integrally use fish shape to design：Fin shape is made in the rectangular each side of chip, drags tin to act on to reach auxiliary
(preventing chip leading portion pad residual from even welding)；
1.2 chip directions are with stove direction excessively at 45 degree of angles, chip downsea peak direction 6mm (tin tailing solder pad body length) or more
Fish tail drags tin, ensures that chip drags tin smooth-going to cause flow-disturbing interference to prevent even to weld without other devices.
1.3 chip center are provided with stomata, preferably greater than or equal toStomata prevents chip from being generated after patch negative
Pressure causes chip offset bad.
Stomata is provided between the tail portion of 1.4 tin tailing solder pads, preferably greater than or equal toStomata, to reach exclusion plate face
Gas make scolding tin be more close to tin tailing solder pad enhancing drag tin ability.
Wherein, fin shape coring piece center pin, development length are on the inside of chip package to drawing outside soldering disk
Lateral extent is 4-6mm, is gradually smoothed out and is cut short to both ends with this；Chip most marginal position at least ensures on the inside of chip package to drawing tin
The outer lateral extent of pad is 2mm or more；It is that chip pin width is 0.8-1.0 times wide to draw the unification of soldering disk width requirement and width requirement
Degree.
One of the preferred embodiment of the present invention is：Chip pin width design：Chip pin pad width is set with circuit bottom copper
It is set to 0.25mm ± 0.02-0.04mm width, is met between chip pin width 0.22mm while as possible guarantee chip tin tailing solder pad
Away from and covering green oil process conditions.
One of the preferred embodiment of the present invention is：The main tin tailing solder pad setting in tail portion：Tin tailing solder pad design on the outside of chip pin
For downsea peak direction obtuse angle shape.
Ensure that main tin tailing solder pad rear side area plays to gradually increase more than front side with this and drags tin ability operation.Main tin tailing solder pad
Face chip pin side to be set as obtuse angle and can play abirritation preventing scolding tin from springing back.
One of the preferred embodiment of the present invention is：Chip pin is arranged with tin tailing solder pad spacing：The main tin tailing solder pad of chip and core
Piece pin pad keeps 0.25mm-0.3mm distances, and (wide with chip pin edge span, this sentences chip center's span
0.5mm pad spans are illustrated for 0.22mm).Keep tin tailing solder pad and chip by chip pin spacing almost equal by tin tailing solder pad as
Chip increase by one is used to ensure that without attribute pin drags tin ability.
One of the preferred embodiment of the present invention is：It is designed between chip pin pad and tin tailing solder pad：Chip pin pad with
Increase 0.45mm-0.5mm between chip tin tailing solder pad draws soldering disk, and it is chip pin width 1.5- to draw tin pad width
Between 2.5 times.Playing prevention chip drags tin residue problem, auxiliary to drag tin purpose.(chip pin width only 0.22mm or so, 2 times
Left and right, which is drawn soldering disk and not only can guarantee, draws tin operation and can prevent to draw that soldering disk is excessive that chip pin pad and back segment master is caused to drag tin
Pad large area, which is integrated, loses no attribute chip pin pad operation.)
One of the preferred embodiment of the present invention is：Draw soldering disk to be arranged in the position away from chip pin L feet center ± 0.3mm.
Smoothly draw tin purpose to reach to draw soldering disk and play in chip pin L Angle Positions.(chip connects welding position and sets at the angles L, this
Place, which increases to draw tin and make to draw tin and the angles L, becomes straight line effect.It can reach straight line and draw tin, enhancing chip drags tin ability)
One of the preferred embodiment of the present invention is：Solder is drawn in each chip tin tailing solder pad pin increase, and it is weldering to draw solder size
Between 0.8 to 1 times of disk size, length is gradually lengthened from homonymy chip pin both ends to center.
Preferred embodiments of the present invention are to draw the general middle pin longest of solder, and then both ends are gradually shortened, and prevent adjacent two
Connect tin between pad, guarantee smoothly drags tin.
One of the preferred embodiment of the present invention is：The preferred chip pin pitch of chip is greater than or equal to 0.5mm, such as size is
10*10*0.5mm (concrete model/encapsulation specification：Integrated circuit R-R5F562T7DDFM#V1 LQFP64).
The advantage of the present invention compared with the existing technology includes：
(1) rectangular chip or SOP biserial pin collection that any type is greater than or equal to 0.5mm pin pitchs be present invention can be suitably applied to
At circuit chip package structure solder wave process, pin number is unrestricted, and encapsulation is unrestricted, and chip volume is unrestricted,
Can Uniting at this class wrapper, verified for a long time through our company, 0.5% or less fraction defective after current such chip stove；
(2) connect the place of tin and rosin joint particular for currently available technology chip, pad design is more reasonable, parameter setting
Definitely, it refines；
(3) fish shape tin tailing solder pad and the design of fish tail tin tailing solder pad were more conducive to stove, and tin, chip pin end is dragged to increase
Add and draws tin and prevent end from connecting tin；
(4) increase along chip pin direction and draw solder, be more conducive between chip pin and drag tin, make adjacent leads
Between i.e. missing solder will not connect tin；
(5) design of chip center's stomata causes chip offset bad to prevent chip from generating negative pressure after patch；
(6) fraction defective it is low mean to reduce manually drag tin cost, manually drag tin itself that can cause to damage to chip, subtract
Few chip service life, directly affects product fraction defective.
Description of the drawings
Fig. 1 is chip structure and scale diagrams；
Fig. 2 be chip tin tailing solder pad of the present invention fish shape design diagram, wherein 1, along mistake the left front chip in stove direction draw tin
Part；2, chip crosses stove direction and meets wave crest angle (45 °)；3, draw tin part along chip before crossing the stove direction right side；4, chip bottom
Stomata；5, suitable tin tailing solder pad before crossing the stove direction right side；6, suitable to cross the left front tin tailing solder pad in stove direction；7, along crossing, stove direction is left back to draw tin portion
Point；8, suitable to cross the left back tin tailing solder pad in stove direction；9, tin tailing solder pad air hole；10, suitable tin tailing solder pad after crossing the stove direction right side；11, suitable
Draw tin part after crossing the stove direction right side；
Fig. 3 is chip pin pad width of the present invention and circuit bottom copper enlarged diagram；
Fig. 4 is the schematic diagram of the main tin tailing solder pad setting obtuse in tail portion of chip tin tailing solder pad of the present invention, wherein 4 (a), 4
(b), 4 (c) is respectively suitable crosses the left front tin tailing solder pad obtuse angle enlarged drawing in stove direction, suitable tin tailing solder pad obtuse angle amplification before crossing the stove direction right side
Figure, suitable tin tailing solder pad obtuse angle enlarged drawing after crossing stove direction；
Fig. 5 is the chip pin and tin tailing solder pad overall schematic of chip tin tailing solder pad of the present invention；
Fig. 6 design diagrams between the chip pin pad and tin tailing solder pad of chip tin tailing solder pad of the present invention, wherein 6 (a),
6 (b) is respectively that tin tailing solder pad draws tin part integral position schematic diagram with chip bonding pad, and tin tailing solder pad draws tin part with chip bonding pad
Width enlarged drawing；
Fig. 7 draws soldering disk to chip pin center schematic diagram, wherein 7 (a), 7 (b) point for chip tin tailing solder pad of the present invention
Not Wei tin tailing solder pad and chip bonding pad draw tin portion enlarged drawing, tin tailing solder pad draws tin portion enlarged drawing with chip bonding pad
(after stove)；
Fig. 8 is design sketch after chip stove.
Fig. 9 is that SOP encapsulation chips cross stove schematic diagram.
Figure 10 is that SOP encapsulates design sketch after chip stove.
Specific implementation mode
With reference to embodiment and attached drawing, the present invention is described in further detail, but the embodiment invented is not limited to
This.
Embodiment 1
Referring to Fig.1 shown in -7, a kind of novel chip tin tailing solder pad：
1.1 chips integrally use fish shape to design：Make fin shape in the rectangular each side of chip, wherein 1, left along stove direction is crossed
Preceding chip draws tin part；2, chip crosses stove direction and meets wave crest angle (45 °)；3, draw tin part along chip before crossing the stove direction right side；
4, chip bottom stomata；5, suitable tin tailing solder pad before crossing the stove direction right side；6, suitable to cross the left front tin tailing solder pad in stove direction；7, suitable to cross stove direction
It is left back to draw tin part；8, suitable to cross the left back tin tailing solder pad in stove direction；9, tin tailing solder pad air hole；10, suitable to cross the right rear dragging tin in stove direction
Pad；11, draw tin part behind the suitable stove direction right side excessively；
With stove direction excessively at 45 degree of angles, the chip downsea peak above fish tails of direction 6mm drag tin in 1.2 chip directions；
1.3 chip center are provided with stomata；
It is provided with stomata between the tail portion of 1.4 tin tailing solder pads.
The stomata isStomata.
The chip pin pad width is set as 0.25mm width with circuit bottom copper.
The tin tailing solder pad is designed as downsea peak direction obtuse angle shape on the outside of chip pin.
The main tin tailing solder pad of chip keeps 0.25mm distances with chip pin pad.
One 0.45mm's of increase draws soldering disk between the chip pin pad and chip tin tailing solder pad.
The soldering disk that draws is set to the position away from chip pin center ± 0.3mm.
Solder is drawn in each chip tin tailing solder pad pin increase.
The chip preferred size is 10*10*0.5mm.
Embodiment 2
With reference to shown in Fig. 9-10, a kind of novel chip tin tailing solder pad：
The main tin tailing solder pad of chip keeps 0.5mm distances with chip pin pad.
One 0.8mm's of increase draws soldering disk between the chip pin pad and chip tin tailing solder pad.
The soldering disk that draws is set to the position away from chip pin center ± 0.3mm.
The chip is preferably SOP encapsulation chips.
Embodiment 3
It is welded using the scheme of embodiment 1 or 2, the results are shown in Figure 8, this tin tailing solder pad and welding procedure are conducive to
Stove is crossed, tin is dragged, missing solder will not connect tin, and chip center's stomata design leads to chip to prevent chip from generating negative pressure after patch
Deviate bad, technique can be realized with simple operations, and product yield is high, increase chip service life.
The above embodiment is a preferred embodiment of the present invention, but embodiments of the present invention are not by above-described embodiment
Limitation, it is other it is any without departing from the spirit and principles of the present invention made by changes, modifications, substitutions, combinations, simplifications,
Equivalent substitute mode is should be, is included within the scope of the present invention.
Claims (10)
1. a kind of novel chip tin tailing solder pad design, which is characterized in that
1.1 chips integrally use fish shape to design：Make fin shape in the rectangular each side of chip；
With stove direction excessively at 45 degree of angles, the chip downsea peak above fish tails of direction 6mm drag tin in 1.2 chip directions；
1.3 chip center are provided with stomata；
It is provided with stomata between the tail portion of 1.4 tin tailing solder pads.
2. tin tailing solder pad design according to claim 1, which is characterized in that draw fin shape coring piece center
Foot, development length are that soldering disk is drawn, lateral extent is 4-6mm outside on the inside of chip package, are gradually smoothed out and are cut short to both ends with this；Core
Piece most marginal position at least ensures that lateral extent is 2mm or more outside to soldering disk is drawn on the inside of chip package；Draw soldering disk width requirement
Unified and width requirement is 0.8-1.0 times of width of chip pin width.
3. tin tailing solder pad according to claim 1 design, which is characterized in that the stomata be more than or equal toGas
Hole.
4. tin tailing solder pad design according to claim 1, which is characterized in that chip pin pad width is set with circuit bottom copper
It is set to 0.25mm ± 0.02-0.04 width.
5. tin tailing solder pad design according to claim 1, which is characterized in that tin tailing solder pad is designed as on the outside of chip pin
Downsea peak direction obtuse angle shape.
6. tin tailing solder pad design according to claim 1, which is characterized in that the main tin tailing solder pad of chip and chip pin pad
Keep 0.25mm-0.3mm distances.
7. tin tailing solder pad design according to claim 1, which is characterized in that between chip pin pad and chip tin tailing solder pad
One 0.4mm-0.5mm's of increase draws soldering disk, and it is 2 times or so of chip pin width to draw tin pad width, draws tin length of bonding pad
For 0.8 to 1.5 times of chip pin gap lengths (if chip pin pin pitch 0.5mm, spacing is between 0.4mm to 0.8mm).
8. tin tailing solder pad design according to claim 1, which is characterized in that draw soldering disk and be set to away from chip pin L feet
The position of place-centric ± 0.3mm.
9. tin tailing solder pad design according to claim 1, which is characterized in that tin is drawn in each chip tin tailing solder pad pin increase
Line draws solder size between 0.8 to 1 times of pad size, and length is gradually lengthened from homonymy chip pin both ends to center.
10. tin tailing solder pad design according to claim 1, which is characterized in that chip pin pitch is greater than or equal to 0.5mm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810357773.3A CN108288610A (en) | 2018-04-20 | 2018-04-20 | It a kind of design of novel chip tin tailing solder pad and its is applied in red adhesive process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810357773.3A CN108288610A (en) | 2018-04-20 | 2018-04-20 | It a kind of design of novel chip tin tailing solder pad and its is applied in red adhesive process |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108288610A true CN108288610A (en) | 2018-07-17 |
Family
ID=62834599
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810357773.3A Pending CN108288610A (en) | 2018-04-20 | 2018-04-20 | It a kind of design of novel chip tin tailing solder pad and its is applied in red adhesive process |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108288610A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115052433A (en) * | 2022-07-14 | 2022-09-13 | 苏州朋协智控科技有限公司 | Novel SMT (surface mount technology) chip mounting process for circuit board |
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| JPH05315733A (en) * | 1992-05-07 | 1993-11-26 | Sanyo Electric Co Ltd | Printed wiring board |
| JPH09181435A (en) * | 1995-12-27 | 1997-07-11 | Sharp Corp | Printed wiring board |
| CN1384697A (en) * | 2001-04-27 | 2002-12-11 | 松下电器产业株式会社 | Wire circuit board |
| CN101868123A (en) * | 2010-07-02 | 2010-10-20 | 深圳和而泰智能控制股份有限公司 | Printed circuit board and design method thereof |
| CN202488878U (en) * | 2011-12-19 | 2012-10-10 | 青岛海尔智能电子有限公司 | Diamond-shaped patch chip pad |
| JP2013225569A (en) * | 2012-04-20 | 2013-10-31 | Canon Inc | Printed wiring board and image forming apparatus |
| CN203722928U (en) * | 2013-11-27 | 2014-07-16 | 广东美的制冷设备有限公司 | Integrated circuit chip packaging structure of printed circuit board |
| CN104684250A (en) * | 2013-11-27 | 2015-06-03 | 广东美的制冷设备有限公司 | Package structure of integrated circuit chip of printed circuit board and package design method |
| CN204795857U (en) * | 2015-07-10 | 2015-11-18 | 深圳市科美集成电路有限公司 | Prevent even pad of tin |
-
2018
- 2018-04-20 CN CN201810357773.3A patent/CN108288610A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05315733A (en) * | 1992-05-07 | 1993-11-26 | Sanyo Electric Co Ltd | Printed wiring board |
| JPH09181435A (en) * | 1995-12-27 | 1997-07-11 | Sharp Corp | Printed wiring board |
| CN1384697A (en) * | 2001-04-27 | 2002-12-11 | 松下电器产业株式会社 | Wire circuit board |
| CN101868123A (en) * | 2010-07-02 | 2010-10-20 | 深圳和而泰智能控制股份有限公司 | Printed circuit board and design method thereof |
| CN202488878U (en) * | 2011-12-19 | 2012-10-10 | 青岛海尔智能电子有限公司 | Diamond-shaped patch chip pad |
| JP2013225569A (en) * | 2012-04-20 | 2013-10-31 | Canon Inc | Printed wiring board and image forming apparatus |
| CN203722928U (en) * | 2013-11-27 | 2014-07-16 | 广东美的制冷设备有限公司 | Integrated circuit chip packaging structure of printed circuit board |
| CN104684250A (en) * | 2013-11-27 | 2015-06-03 | 广东美的制冷设备有限公司 | Package structure of integrated circuit chip of printed circuit board and package design method |
| CN204795857U (en) * | 2015-07-10 | 2015-11-18 | 深圳市科美集成电路有限公司 | Prevent even pad of tin |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115052433A (en) * | 2022-07-14 | 2022-09-13 | 苏州朋协智控科技有限公司 | Novel SMT (surface mount technology) chip mounting process for circuit board |
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