CN215069966U - Novel semiconductor packaging structure - Google Patents
Novel semiconductor packaging structure Download PDFInfo
- Publication number
- CN215069966U CN215069966U CN202122733544.7U CN202122733544U CN215069966U CN 215069966 U CN215069966 U CN 215069966U CN 202122733544 U CN202122733544 U CN 202122733544U CN 215069966 U CN215069966 U CN 215069966U
- Authority
- CN
- China
- Prior art keywords
- lead frame
- packaging structure
- packaging
- chip
- adhesive layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 54
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 239000012790 adhesive layer Substances 0.000 claims abstract description 13
- 239000004020 conductor Substances 0.000 claims abstract description 9
- 230000005611 electricity Effects 0.000 abstract description 3
- 239000011248 coating agent Substances 0.000 abstract description 2
- 238000000576 coating method Methods 0.000 abstract description 2
- 230000000694 effects Effects 0.000 abstract description 2
- 238000012536 packaging technology Methods 0.000 abstract description 2
- 238000005538 encapsulation Methods 0.000 abstract 1
- 239000000047 product Substances 0.000 description 17
- 238000003466 welding Methods 0.000 description 12
- 238000000034 method Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 5
- 238000012423 maintenance Methods 0.000 description 4
- 239000002994 raw material Substances 0.000 description 4
- 238000005476 soldering Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000004033 plastic Substances 0.000 description 3
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
The utility model relates to an integrated packaging technology field, concretely relates to novel semiconductor packaging structure, including lead frame (1) the coating has adhesive layer (2) on lead frame (1) be fixed with chip (3) on adhesive layer (2), chip (2) with lead frame (1) is connected through conducting material (4) electricity, be connected with packaging body (5) on lead frame (1) and will chip (3) conducting material (4) with adhesive layer (2) are sealed in packaging body (5). The utility model discloses a novel semiconductor packaging structure, the size is little, and the radiating effect is good, the encapsulation of being convenient for, it is convenient to maintain.
Description
Technical Field
The utility model relates to an integrated packaging technology field especially relates to a novel semiconductor packaging structure.
Background
The principle of the package is that a semiconductor chip is fixed on a lead frame, bonding pads in the chip are respectively connected to the lead frame, plastic package is performed by plastic package materials (plastic, metal and ceramic), and finally cutting is completed to obtain a final product.
However, both current forms of packaging suffer from their own drawbacks:
the DIP-packaged form suffers from the following problems: (1) the ratio of the area of the chip to the packaging area is large, the molding size after packaging is large (2), the packaging efficiency is low, and the heat dissipation effect is poor (3).
The QFN package format suffers from the following problems: (1) reflow soldering is needed to be used for soldering, the problem that products (2) with low soldering temperature cannot be subjected to penetration soldering (3), maintenance is needed by using a special tool, and maintenance is difficult is solved.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to solve above-mentioned problem, provide a novel semiconductor packaging structure.
In order to achieve the above object, the utility model provides a novel semiconductor packaging structure, including the lead frame coat on the lead frame have the adhesive layer be fixed with the chip on the adhesive layer, the chip with the lead frame passes through the conducting material electricity and connects, it will to be connected with the packaging body on the lead frame the chip conducting material with the adhesive layer is sealed in the packaging body.
According to an aspect of the present invention, the lead frame lower end is connected to the pin.
According to an aspect of the utility model, pin front end closed angle structure.
According to an aspect of the present invention, the two sides, three sides or four sides of the lead frame are all connected with pins.
According to an aspect of the utility model, the packaging body includes upside packaging structure and downside packaging structure, upside packaging structure's side with downside packaging structure's side is connected.
According to an aspect of the present invention, the positioning groove is provided on the lead frame, and the lower side packaging structure is connected with the positioning groove in a matching manner.
The utility model discloses a semiconductor packaging structure has following advantage: the volume becomes smaller and the raw material used for a single product will be reduced. The raw materials can be selected from a wide range, and different materials can be used for completing the same function. The integration level is high, and the product of the same size can accomplish the product of several times DIP, realizes the same function, and the material that uses becomes fewly. The whole process is stable, and better product yield can be obtained.
Furthermore, the utility model discloses a semiconductor package structure welding performance is good, mainly shows following aspect:
the packaging body has pins, and the direct insertion type is adopted, so that a mainboard can be effectively punched or a paper circuit can be penetrated, and the packaging body has good compatibility with the mainboard. The packaging body can be directly welded on a chip socket or welded on the same welding hole due to the existence of the pin. The packaging body has the pins, so that the welding process does not need high-temperature welding, and the application range is wider. The packaging body has the pins, so that the packaging body can be effectively positioned, and is simple and convenient in the welding process.
The utility model discloses a semiconductor package structure good reliability mainly shows following aspect:
the lead frame has most metals to expose, and the heat-sinking capability of its product of great improvement can be applicable to more abominable environment. Products soldered onto paper circuits can be distorted slightly without affecting the performance of the product. The product has strong positioning performance and welding performance due to the existence of the pins, and can be applied to wider application ends. In addition, the packaging body has the pins, so that the packaging body is convenient to maintain and easy to replace in the maintenance process.
Drawings
Fig. 1 schematically illustrates a cross-sectional view of a novel semiconductor package structure in accordance with an embodiment of the present invention;
fig. 2 schematically illustrates a perspective view of a novel semiconductor package structure according to an embodiment of the present invention;
fig. 3 is a perspective view schematically showing a novel semiconductor package structure according to a second embodiment of the present invention.
The reference numerals in the drawings represent the following meanings:
1. a lead frame; 2. an adhesive layer; 3. a chip; 4. a conductive material; 5. a package body; 51. an upper side package structure; 52. a lower side package structure; 6. a pin; 61. and (4) a sharp corner structure.
Detailed Description
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
The present invention will be described in detail with reference to the accompanying drawings and specific embodiments, which are not repeated herein, but the present invention is not limited to the following embodiments.
With reference to fig. 1, 2 and 3, the utility model provides a novel semiconductor package structure, including lead frame 1 the coating on the lead frame 1 have adhesive layer 2 be fixed with chip 3 on the adhesive layer 2, chip 2 with lead frame 1 is connected through conductive material 4 electricity, it will to be connected with packaging body 5 on the lead frame 1 the chip 3 conductive material 4 with adhesive layer 2 seals in the packaging body 5. The utility model discloses a pin 6 is connected to 1 lower extreme of lead frame, 6 front end closed angle structures 61 of pin.
According to the utility model discloses the design, at least the both sides of lead frame 1 are connected with pin 6. As shown in fig. 2, the lead frame 1 is provided with the leads 6 at both sides thereof, and as shown in fig. 3, the lead frame 6 is provided with the leads 6 at three sides thereof, but the leads 6 may be provided at four sides of the lead frame 1.
According to an embodiment of the present invention, the package body 5 includes an upper side packaging structure 51 and a lower side packaging structure 52, the side of the upper side packaging structure 51 is connected with the side of the lower side packaging structure 52. The lead frame 1 has a positioning groove, and the lower side package structure 52 is connected to the positioning groove in a matching manner.
The utility model discloses a semiconductor packaging structure has following advantage: the volume becomes smaller and the raw material used for a single product will be reduced. The raw materials can be selected from a wide range, and different materials can be used for completing the same function. The integration level is high, and the product of the same size can accomplish the product of several times DIP, realizes the same function, and the material that uses becomes fewly. The whole process is stable, and better product yield can be obtained.
Furthermore, the utility model discloses a semiconductor package structure welding performance is good, mainly shows following aspect:
the packaging body has pins, and the direct insertion type is adopted, so that a mainboard can be effectively punched or a paper circuit can be penetrated, and the packaging body has good compatibility with the mainboard. The packaging body can be directly welded on a chip socket or welded on the same welding hole due to the existence of the pin. The packaging body has the pins, so that the welding process does not need high-temperature welding, and the application range is wider. The packaging body has the pins, so that the packaging body can be effectively positioned, and is simple and convenient in the welding process.
The utility model discloses a semiconductor package structure good reliability mainly shows following aspect:
the lead frame has most metal to fall outside, and the heat-sinking capability of its product of great improvement can be applicable to more abominable environment. Products soldered onto paper circuits can be distorted slightly without affecting the performance of the product. The product has strong positioning performance and welding performance due to the existence of the pins, and can be applied to wider application ends. In addition, the packaging body has the pins, so that the packaging body is convenient to maintain and easy to replace in the maintenance process.
The above description is only one embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (2)
1. The novel semiconductor packaging structure is characterized by comprising a lead frame (1), wherein an adhesive layer (2) is coated on the lead frame (1), a chip (3) is fixed on the adhesive layer (2), the chip (3) is electrically connected with the lead frame (1) through a conductive material (4), and a packaging body (5) is connected onto the lead frame (1) to seal the chip (3), the conductive material (4) and the adhesive layer (2) in the packaging body (5);
the lower end of the lead frame (1) is connected with a pin (6);
the front end sharp corner structure (61) of the pin (6);
the packaging body (5) comprises an upper side packaging structure (51) and a lower side packaging structure (52), and the side edge of the upper side packaging structure (51) is connected with the side edge of the lower side packaging structure (52);
the lead frame (1) is provided with a positioning groove, and the lower side packaging structure (52) is matched and connected with the positioning groove.
2. The novel semiconductor package structure according to claim 1, wherein pins (6) are connected to two, three or four sides of the lead frame (1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122733544.7U CN215069966U (en) | 2021-11-10 | 2021-11-10 | Novel semiconductor packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122733544.7U CN215069966U (en) | 2021-11-10 | 2021-11-10 | Novel semiconductor packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN215069966U true CN215069966U (en) | 2021-12-07 |
Family
ID=79218480
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202122733544.7U Active CN215069966U (en) | 2021-11-10 | 2021-11-10 | Novel semiconductor packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN215069966U (en) |
-
2021
- 2021-11-10 CN CN202122733544.7U patent/CN215069966U/en active Active
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| PP01 | Preservation of patent right | ||
| PP01 | Preservation of patent right |
Effective date of registration: 20231211 Granted publication date: 20211207 |