CN108281424B - 半导体元件以及其制作方法 - Google Patents

半导体元件以及其制作方法 Download PDF

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CN108281424B
CN108281424B CN201710011195.3A CN201710011195A CN108281424B CN 108281424 B CN108281424 B CN 108281424B CN 201710011195 A CN201710011195 A CN 201710011195A CN 108281424 B CN108281424 B CN 108281424B
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storage node
dielectric
substrate
adjacent
bit lines
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CN108281424A (zh
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刘姿岑
冯立伟
何建廷
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Abstract

本发明公开一种半导体元件以及其制作方法，包括提供基板、多条字符线与多条位线，然后于各源极/漏极区上形成存储节点接触，使各存储节点接触的上表面于一方向上的宽度小于各存储节点接触的下表面于此方向上的宽度。

Description

半导体元件以及其制作方法
技术领域
本发明涉及一种半导体元件及其制作方法，特别是涉及一种避免相邻存储节点短路的动态随机存取存储器及其制作方法。
背景技术
一般而言，随机动态存取存储器(dynamic random access memory，DRAM)的单元结构由一个晶体管以及一个电容所构成，并通过其中的电容来存储电荷，进而记录所欲数据。随着应用的增加，DRAM的尺寸需要不断微缩，以提升DRAM的积极度、加快元件的操作速度、提高DRAM的容量以及符合消费者对于小型化电子装置的需求。
常见的DRAM是将晶体管制作于基底中，并通过字符线将排列在同一方向上的晶体管的栅极串联，然后于晶体管上设置与字符线交错的位线。接着，为了避免与位线与字符线电连接，存储节点接触可通过任两相邻的字符线与任两相邻的位线所围绕出的区域与晶体管的源极/漏极区连接。最后，再依序于每一个存储节点接触上形成存储节点、电容介电层及电容器上电极。为了尽量减少每一个电容所占芯片面积，且另一方面又要维持一定的电容值，目前均将电容制作得又高又细。为此，在制作存储节点时需于存储节点接触上形成高深宽比的开孔，且每一个开孔需仅对应一个存储节点接触，以使所形成的每一个电容仅与对应一个存储节点接触电连接。
然而，随着临界尺寸继续缩小，光刻制作工艺的对位误差容易导致所形成单一的高深宽比开孔会同时对应两个存储节点接触，如此造成后续所形成的存储节点电连接至两个相邻的存储节点接触，以致于发生存储节点接触短路的问题。
发明内容
本发明的目的在于提供一种半导体元件及其制作方法，以避免存储节点与两相邻存储节点接触相接触短路的问题发生。
本发明的一实施例提供一种半导体元件，其包括基板、多条字符线、多条位线以及多个存储节点接触。基板包括多个主动区，且各主动区包括两个源极/漏极区，分别位于各主动区的两端。字符线设置于基板中，且各字符线沿着第一方向延伸设置。位线设置于基板上，且各位线沿着第二方向延伸设置并横跨字符线，其中各源极/漏极区分别设置于由任两相邻的字符线与任两相邻的位线围绕出的一区域中。存储节点接触分别设置于源极/漏极区上，其中各存储节点接触的上表面于第二方向上的宽度小于各存储节点接触的下表面于第二方向上的宽度。
本发明的另一实施例提供一种半导体元件的制作方法。首先，提供基板、多条字符线以及多条位线，其中基板包括多个主动区，各主动区包括两个源极/漏极区，字符线嵌入基板中，各字符线沿着第一方向延伸设置，位线设置于基板上，各位线沿着一第二方向延伸设置并横跨字符线，且各源极/漏极区分别设置于由任两相邻的字符线与任两相邻的位线围绕出的一区域中。然后，在基板上形成多条介电条，各介电条分别设置于任两相邻的位线之间。接着，图案化各介电条，以于各源极/漏极区上分别形成一介电区块，其中任两相邻的介电区块之间具有一第一穿孔。随后，在各第一穿孔中分别形成一绝缘区块。接下来，移除介电区块，以于任两相邻的绝缘区块之间形成一第二穿孔。之后，在各第二穿孔中分别形成一存储节点接触，其中各存储节点接触的上表面于第二方向上的宽度小于各存储节点接触的下表面于第二方向上的宽度。
本发明通过形成各存储节点接触的上表面于第二方向上的宽度可小于其下表面于第二方向上的宽度，以提升存储节点在形成时在第二方向上的位移误差范围，进而降低因制作工艺误差所造成存储节点与两相邻存储节点接触相接触短路的问题。
附图说明
图1为本发明一实施例的半导体元件的上视示意图；
图2为图1沿着剖线A-A’的剖面示意图；
图3至图13为本发明一实施例的半导体元件的制作方法示意图。
主要元件符号说明
100 半导体元件 102 基板
104 元件隔离层 106 绝缘区块
108 介电条 108R 介电区块
AR 主动区 WL 字符线
BL 位线 SC 存储节点接触
SC1 多晶硅层 SC2 钴硅化物层
SC3 钨层 D1 第一方向
D2 第二方向 D3 第三方向
SD1 第一源极/漏极区 SD2 第二源极/漏极区
IN 绝缘层 CL 盖层
TH1 第一穿孔 TH2 第二穿孔
ES 蚀刻停止层 ESR 蚀刻停止区块
SN 存储节点 MP 掩模图案
OP 条状开孔
具体实施方式
请参考图1与图2，图1为本发明一实施例的半导体元件的上视示意图，图2为沿着图1的剖线A-A’的剖面示意图，其中图1与图2仅绘示半导体元件设置有电容的存储器区，但本发明并不以此为限。如图1与图2所示，本实施例的半导体元件100包括基板102、多条字符线WL、多条位线BL以及多个存储节点接触SC。基板102可包括多个主动区AR，彼此平行设置，且可分别为沿着第三方向D3延伸的条状结构。具体而言，半导体元件100可包括元件隔离层104，设置于基板102中，环绕主动区AR，以定义出主动区AR并电性绝缘主动区AR。元件隔离层104的上表面可与基板102的上表面位于同一平面上。此外，各主动区AR可包括两个第一源极/漏极区SD1以及一第二源极/漏极区SD2，第一源极/漏极区SD1分别位于各主动区AR的两端，且第二源极/漏极区SD2位于第一源极/漏极区SD1之间。
字符线WL彼此平行设置于基板102中，且分别沿着不同第三方向D3的第一方向D1延伸设置，因此与对应的主动区AR交错，用以作为栅极。举例而言，两相邻的字符线WL可横跨同一主动区AR，且分别设置于各第一源极/漏极区SD1以及第二源极/漏极区SD2之间，以将各第一源极/漏极区SD1与第二源极/漏极区SD2区隔开。并且，字符线WL可埋入基板102中，使其上表面低于基板102的上表面。各字符线WL与主动区AR之间还可设置有一绝缘层IN，用以将各字符线WL与主动区AR绝缘，并可作为栅极绝缘层，且各字符线WL上方可设置有一盖层CL，用以保护各字符线WL免于后续制作工艺的破坏。盖层CL的上表面可例如与基板102的上表面位于同一平面上。此外，各字符线WL可由例如包括多晶硅、掺杂多晶硅、金属或金属硅化物的导电材料所形成。
位线BL彼此平行设置于基板102上，且分别沿着不同于第三方向D3与第一方向D1的第二方向D2延伸设置，因此可横跨字符线WL与主动区AR。各位线BL可与排列在第二方向D2上的主动区AR的第二源极/漏极区SD2电连接。举例而言，第一方向D1可与第二方向D2垂直，且第三方向D3与第二方向D2可呈锐角夹角，因此各第一源极/漏极区SD1可分别设置于由任两相邻的字符线WL与任两相邻的位线BL围绕出的一区域中。并且，位线BL与字符线WL可通过盖层CL电性绝缘，而位线BL与第一源极/漏极区SD1之间可设置有另一绝缘层(图未示)，用以将彼此电性绝缘。各位线BL的侧壁上设置有间隙壁(图未示)，且其上方可设置有另一盖层(图未示)，用以保护各位线BL免于后续制作工艺的破坏。
存储节点接触SC分别设置于对应的第一源极/漏极区SD1上，用以将各第一源极/漏极区SD1电连接至一电容器(图未示)。各存储节点接触SC的上表面于第二方向D2上的宽度小于各存储节点接触SC的下表面于第二方向D2上的宽度。具体而言，半导体元件100还可包括多个绝缘区块106，设置于任两相邻的位线BL之间的盖层CL上，且任两相邻的绝缘区块106之间具有第二穿孔TH2，对应每一个第一源极/漏极区SD1设置，而各存储节点接触SC分别设置于各第二穿孔TH2中，以与对应的第一源极/漏极区SD1电连接。各第二穿孔TH2可由任两相邻的绝缘区块106与间隙壁所构成。由于各绝缘区块106于第二方向D2上具有一倒梯形形状，因此各第二穿孔TH2于第二方向D2上具有梯形形状，也就是设置于第二穿孔TH2中的存储节点接触SC在第二方向D2上具有梯形形状。存储节点接触SC的上表面可约略与绝缘区块106的上表面位于同一水平面上。并且，存储节点接触SC可通过设置于位线BL侧壁的间隙壁与位线BL电性绝缘。在本实施例中，各存储节点接触SC可包括多层结构。举例而言，多层结构可包括例如多晶硅层SC1、钴硅化物层SC2与钨层SC3依序堆叠的堆叠结构，但本发明不限于此。此外，本实施例的绝缘区块106与对应的盖层CL之间可另设置有蚀刻停止区块ESR。
半导体元件100还可包括多个存储节点SN，设置于存储节点接触SC与绝缘区块106上，并分别与对应的存储节点接触SC相接触。存储节点SN可作为电容器的下电极，且其上可另设置电容介电层与上电极(图未示)。在另一实施例中，存储节点SN也可以为设置于电容器下电极与存储节点接触SC之间的转接垫，用以电连接两者。值得说明的是，由于用以绝缘相邻存储节点接触SC的绝缘区块106具有倒梯形形状，因此相较于绝缘区块106在第二方向D2上为矩形的设计而言，相邻存储节点接触SC的上表面之间于第二方向D2上的间距可增加，如此一来可提升存储节点SN在形成时在第二方向D2上的位移误差范围，进而降低因制作工艺误差所造成存储节点SN与两相邻存储节点接触SC相接触短路的问题。
以下将进一步说明本实施例半导体元件100的制作方法。请参考图3至图13，且一并参考图1与图2。图3至图13为本发明一实施例的半导体元件的制作方法示意图，其中图4为图3沿着剖线B-B’的剖视示意图，图6为图5沿着剖线C-C’的剖视示意图，图8为图7沿着剖线D-D’的剖视示意图，图10为图9沿着剖线E-E’的剖视示意图，图12为图11沿着剖线F-F’的剖视示意图。首先，如图3与图4所示，提供基板102、字符线WL以及位线BL。此时，各位线BL的侧壁上已设置有间隙壁，且其上方已设置有盖层。本实施例的基板102、字符线WL与位线BL的具体配置方式可如上所述，因此在此不多赘述。在本实施例中，提供基板102、字符线WL与位线BL还可选择性地包括于基板102上提供蚀刻停止层ES，其覆盖基板102与字符线BL，但本发明不以此为限。然后，通过沉积制作工艺，在蚀刻停止层ES与字符线BL上的盖层上覆盖介电层，接着可通过平坦化制作工艺，移除位于盖层上的介电层直到暴露出盖层，以于基板102上形成多条自对准的介电条108，其中各介电条108分别设置于任两相邻的位线BL之间。
然后，图案化各介电条108，以于各第一源极/漏极区SD1上分别形成一介电区块108R，其中任两相邻的介电区块108R之间具有第一穿孔TH1。具体而言，如图5与图6所示，在介电条108与位线BL上形成一掩模图案MP，其中掩模图案MP包括多个条状开孔OP，横跨介电条108以及位线BL。也就是说，各条状开孔OP沿着字符线WL的延伸方向(即第一方向D1)延伸设置，并分别位于对应的字符线WL正上方。举例而言，掩模图案MP可通过三层结构所形成。三层结构可例如包括有机层、含硅层以及光致抗蚀剂层的堆叠结构。然后，进行光刻制作工艺，以图案化光致抗蚀剂层，进而形成光致抗蚀剂图案。含硅层可例如为含硅硬掩模底抗反射(silicon-containing hard mask bottom anti-reflective coating，SHB)层，可用以减少光致抗蚀剂层与基板102之间的反射光。接着，以光致抗蚀剂图案为掩模进行对含硅层的蚀刻制作工艺，将光致抗蚀剂图案转移至含硅层，以形成含硅图案。随后，以含硅图案为掩模进行对有机层的蚀刻制作工艺，将含硅图案转移至有机层，并移除光致抗蚀剂图案，以形成掩模图案MP。然后，如图7与图8，以掩模图案MP与位线BL上方的盖层为掩模进行蚀刻制作工艺，以蚀刻介电条108，进而形成介电区块108R与第一穿孔TH1。各第一穿孔TH1可由两相邻的介电区块108R与两相邻的位线BL定义出。通过控制蚀刻制作工艺，所形成的各介电区块108R的上表面于第二方向D2上的宽度可小于其下表面于第二方向D2的宽度。
接着，如图9与图10所示，在第一穿孔TH1中分别形成多个绝缘区块106。具体而言，在介电区块108R与位线BL上沉积一绝缘层，其中绝缘层填满第一穿孔TH1。当半导体元件于存储器区外的周边区中还包括其他周边元件时，可于绝缘层上形成掩模，遮蔽周边区的绝缘层，且掩模具有开口暴露出存储器区中的绝缘层。然后，进行蚀刻制作工艺，以蚀刻存储器区中的绝缘层，直到暴露出介电区块108R，进而形成绝缘区块106，其中所形成的各绝缘区块106的上表面于第二方向D2上的宽度可大于其下表面于第二方向D2的宽度，例如各绝缘区块106于第二方向D2上可具有一倒梯形形状。接着可将掩模移除。
然后，如图11与图12所示，移除介电区块108R，以暴露出蚀刻停止层ES。随后，进一步将被暴露出的蚀刻停止层ES蚀穿，以于相邻绝缘区块106之间形成具有梯形形状的第二穿孔TH2，暴露出第一源极/漏极区SD1，并形成蚀刻停止区块ESR。接着，如图13所示，在第二穿孔TH2中分别形成存储节点接触SC，其中各存储节点接触SC的上表面于第二方向D2上的宽度小于各存储节点接触SC的下表面于第二方向D2上的宽度。举例来说，可重复进行沉积制作工艺与回蚀刻制作工艺，依序于第二穿孔TH2中堆叠出多晶硅层SC1、钴硅化物层SC2与钨层SC3的堆叠结构。随后，如图2所示，通过光刻与蚀刻制作工艺，在各存储节点接触SC上分别形成一存储节点SN，其中存储节点SN彼此分隔。在形成存储节点SN之后可进一步于存储节点SN上依序形成电容介电层与上电极，以形成具有DRAM的半导体元件100。值得说明的是，在形成存储节点SN之前，各绝缘区块106于第二方向D2上具有一倒梯形形状，使得第二穿孔TH2于绝缘区块106上表面的开口可相较于绝缘区块106在第二方向D2上为矩形的设计小，因此形成于第二穿孔TH2中的相邻存储节点接触SC的上表面之间于第二方向D2上的间距可较大，由此可提升存储节点SN在形成时的在第二方向D2上的位移误差范围，进而降低因制作工艺误差所造成存储节点SN与两相邻存储节点接触SC相接触短路的问题。
由上述可知，本发明的制作方法通过形成各绝缘区块的上表面于第二方向上的宽度可大于其下表面于第二方向的宽度，使得填入第二穿孔中的各存储节点接触的上表面于第二方向上的宽度可小于其下表面于第二方向上的宽度，由此可降低因制作工艺误差所造成存储节点与两相邻存储节点接触相接触短路的问题。
以上所述仅为本发明的较佳实施例，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (11)

1.一种半导体元件，其特征在于，包括：
基板，包括多个主动区，且各该主动区包括两个源极/漏极区，分别位于各该主动区的两端；
多条字符线，设置于该基板中，且各该字符线沿着一第一方向延伸设置；
多条位线，设置于该基板上，且各该位线沿着一第二方向延伸设置并横跨该多条 字符线，其中各该源极/漏极区分别设置于由任两相邻的该多条 字符线与任两相邻的该多条位线围绕出的一区域中，各位线的侧壁上设置有间隙壁；
多个存储节点接触，分别设置于多个源极/漏极区上，其中各该存储节点接触的上表面于该第二方向上的宽度小于各该存储节点接触的下表面于该第二方向上的宽度；以及
多个绝缘区块，设置于任两相邻的该多条 位线之间的该多条 字符线上，其中任两相邻的该多个绝缘区块之间具有一穿孔，且各该存储节点接触分别设置于各该穿孔中。
2.如权利要求1所述的半导体元件，其特征在于，各该存储节点接触于该第二方向上具有梯形形状。
3.如权利要求1所述的半导体元件，其特征在于，各该绝缘区块于该第二方向上具有一倒梯形形状。
4.如权利要求1所述的半导体元件，其特征在于，还包括多个存储节点，分别设置于该多个存储节点接触上。
5.如权利要求1所述的半导体元件，其特征在于，各该存储节点接触包括多层结构。
6.一种半导体元件的制作方法，其特征在于，包括：
提供一基板、多条字符线以及多条位线，其中该基板包括多个主动区，各该主动区包括两个源极/漏极区，该多条 字符线嵌入该基板中，各该字符线沿着一第一方向延伸设置，该多条 位线设置于该基板上，各该位线沿着一第二方向延伸设置并横跨该多条 字符线，且各该源极/漏极区分别设置于由任两相邻的该多条 字符线与任两相邻的该多条 位线围绕出的一区域中；
在该基板上形成多条介电条，各该介电条分别设置于任两相邻的该多条 位线之间；
图案化各该介电条，以于各该源极/漏极区上分别形成一介电区块，其中任两相邻的多个介电区块之间具有一第一穿孔；
在各该第一穿孔中分别形成一绝缘区块；
移除该多个介电区块，以于任两相邻的多个绝缘区块之间形成一第二穿孔；以及
在各该第二穿孔中分别形成一存储节点接触，其中各该存储节点接触的上表面于该第二方向上的宽度小于各该存储节点接触的下表面于该第二方向上的宽度。
7.如权利要求6所述的半导体元件的制作方法，其特征在于，图案化各该介电条包括：
在多个介电条与该多条 位线上形成一掩模图案，其中该掩模图案包括多个条状开孔，横跨该多个介电条以及该多条 位线；以及
以该掩模图案为一掩模进行一蚀刻制作工艺，以蚀刻该多个介电条，进而形成该多个介电区块，其中各该介电区块的上表面于该第二方向上的宽度小于各该介电区块的下表面于该第二方向的宽度。
8.如权利要求6所述的半导体元件的制作方法，其特征在于，形成该多个绝缘区块包括：
在该多个介电区块与该多条 位线上沉积一绝缘层，其中该绝缘层填满多个第一穿孔；以及
进行一蚀刻制作工艺，以蚀刻该绝缘层，直到暴露出该多个介电区块，进而形成该多个绝缘区块，其中各该绝缘区块于该第二方向上具有一倒梯形形状。
9.如权利要求6所述的半导体元件的制作方法，其特征在于，提供该基板、该多条 字符线与该多条 位线还包括提供一蚀刻停止层，覆盖该基板与该多条 字符线。
10.如权利要求9所述的半导体元件的制作方法，其特征在于，形成该第二穿孔还包括蚀刻该蚀刻停止层，以暴露出多个源极/漏极区。
11.如权利要求6所述的半导体元件的制作方法，其特征在于，还包括于各该存储节点接触上分别形成一存储节点。
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