CN108269806B - 制作半导体元件的方法 - Google Patents
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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Abstract
本发明公开一种制作半导体元件的方法。首先提供一基底,该基底上具有一存储区,然后形成一沟槽于基底内,形成一阻障层于沟槽内,形成一导电层于阻障层上,进行一第一蚀刻制作工艺去除部分导电层,之后再进行一第二蚀刻制作工艺去除部分阻障层,其中第二蚀刻制作工艺包含一无等离子体蚀刻制作工艺。
Description
技术领域
本发明涉及一种制作半导体元件的方法,尤其是涉及一种制作动态随机存取存储器元件的方法。
背景技术
随着各种电子产品朝小型化发展的趋势,动态随机存取存储器(Dynamic RandomAccess Memory,DRAM)单元的设计也必须符合高集成度及高密度的要求。对于一具备凹入式栅极结构的DRAM单元而言,由于其可以在相同的半导体基底内获得更长的载流子通道长度,以减少电容结构的漏电情形产生,因此在目前主流发展趋势下,其已逐渐取代仅具备平面栅极结构的DRAM单元。
一般来说,具备凹入式栅极结构的DRAM单元会包含一晶体管元件与一电荷贮存装置,以接收来自于位线及字符线的电压信号。然而,受限于制作工艺技术之故,现有具备凹入式栅极结构的DRAM单元仍存在有许多缺陷,还待进一步改良并有效提升相关存储器元件的效能及可靠度。
发明内容
本发明较佳实施例公开一种制作半导体元件的方法。首先提供一基底,该基底上具有一存储区,然后形成一沟槽于基底内,形成一阻障层于沟槽内,形成一导电层于阻障层上,进行一第一蚀刻制作工艺去除部分导电层,之后再进行一第二蚀刻制作工艺去除部分阻障层,其中第二蚀刻制作工艺包含一无等离子体蚀刻制作工艺。
附图说明
图1至图6为本发明较佳实施例制作一随机动态处理存储器元件的方法示意图。
主要元件符号说明
10 动态随机存取存储器元件 12 位线
14 字符线 16 基底
18 主动区 20 存储区(存储器区)
22 栅极 24 浅沟绝缘
26 介电层 28 沟槽
30 栅极介电层 32 阻障层
34 导电层 36 第一气体
38 反应室 40 离子过滤器
42 栅极电极 44 硬掩模
46 基座 48 第一蚀刻制作工艺
50 第二蚀刻制作工艺 52 第二气体
具体实施方式
请参照图1至图6,图1至图6为本发明较佳实施例制作一随机动态处理存储器元件的方法示意图,其中图1为俯视图,图2至图6则显示图1中沿着切线A-A’的剖视图。本实施例是提供一存储器元件,例如是具备凹入式栅极的随机动态处理存储器(dynamic randomaccess memory,DRAM)元件10,其包含有至少一晶体管元件(图未示)以及至少一电容结构(图未示),以作为DRAM阵列中的最小组成单元并接收来自于位线12及字符线14的电压信号。
如图1所示,动态随机存取存储器元件10包含一基底16,例如一由硅所构成的半导体基底或半导体晶片,然后于基底16内形成有至少一浅沟绝缘24,以于基底16上定义出多个主动区(active area,AA)18。此外,基底16上还定义有一存储区20以及一周边区(图未示)。其中,动态随机存取存储器元件10的多个字符线(word line,WL)14与多个位线(bitline,BL)12较佳形成于存储区20的基底16上而其他的主动元件等(未绘示)则可形成在周边区。需注意的是,为简化说明,本发明的图1仅绘示出位于存储区20的元件上视图并省略了位于周边区的元件。
在本实施例中,各主动区18例如是相互平行地朝向一第一方向延伸,而字符线14或多条栅极22是形成在基底16内并穿越各主动区18及浅沟绝缘24。具体来说,各栅极22是沿着不同于第一方向的一第二方向延伸,且第二方向与第一方向相交并小于90度。
另一方面,位线12是相互平行地形成在基底16上沿着一第三方向延伸,并同样横跨各主动区18及浅沟绝缘24。其中,第三方向同样是不同于第一方向,并且较佳是与第二方向垂直。也就是说,第一方向、第二方向及第三方向彼此皆不同,且第一方向与第二方向及第三方向皆不垂直。此外,字符线14两侧的主动区18内较佳设有接触插塞,例如包括位线接触插塞(bit line contact,BLC)(图未示)来电连接至各晶体管元件的源极/漏极区域(图未示)以及存储节点(storage node)接触插塞(图未示)来电连接一电容。
以下针对字符线14(或又称埋藏式字符线)的制作进行说明。如图2所示,首先形成一介电层26于基底16表面,然后进行一光刻暨蚀刻制作工艺,例如可先形成一图案化掩模于介电层26表面,再利用蚀刻去除部分未被图案化掩模所遮蔽的部分介电层26与部分基底16,以形成至少一沟槽28于存储区20的基底16内。
接着进行一现场蒸气成长(in-situ steam generation,ISSG)制作工艺以形成一由氧化硅所构成的栅极介电层30于沟槽28内。然后形成一阻障层32于介电层26上表面、介电层26侧壁以及栅极介电层30表面,并再形成一导电层34于阻障层32上,其中导电层34较佳填满沟槽28并凸出于介电层26表面。在本实施例中,介电层26较佳包含氧化硅,阻障层32较佳包含氮化钛,而导电层34则较佳包含钨,但不局限于此。
随后如图3所示,进行一第一蚀刻制作工艺48去除部分导电层34,使剩余的导电层34略低于基底16表面。在本实施例中第一蚀刻制作工艺48较佳包含一干蚀刻制作工艺,且第一蚀刻制作工艺48所使用的蚀刻气体成分可包含但不局限于例如三氟化氮(NF3)、六氟化硫(SF6)或其组合。
接着如图4所示,进行一第二蚀刻制作工艺50去除部分阻障层32,使剩余的阻障层32上表面略低于基底16表面甚至略低于导电层34上表面。需注意的是,本实施例中剩余的阻障层32上表面虽略低于导电层34上表面,但不局限于此,又可于第二蚀刻制作工艺50时调整制作工艺的参数,例如蚀刻的时间或气体成分与比例等,使剩余的阻障层32上表面切齐导电层34上表面,此实施例也属本发明所涵盖的范围。
依据本发明的较佳实施例,第二蚀刻制作工艺50较佳包含一无等离子体蚀刻制作工艺,其中无等离子体蚀刻制作工艺可由几种手段来达成。举例来说,如图5所示,依据本发明一实施例,可先于一反应室38中将基底16放置于一基座46上,然后通入一第一气体36,例如一离子化的气体至一反应室38,其中离子化的气体可包含经由解离过且同时带有正电荷与负电荷的离子气体与自由基,例如氯气。然后利用一离子过滤器(ion filter)40去除气体中的负电荷与正电荷以形成一第二气体52,例如一不带有电荷的气体。换句话说,原本带有电荷的离子气体例如氯气经由离子过滤器40过滤之后即重回不带电荷的原子身分,例如氯原子。接着再利用不带电荷的氯原子气体进行前述第二蚀刻制作工艺50来去除部分阻障层32。值得注意的是,由于第二蚀刻制作工艺50较佳选用不带电荷的原子气体作为蚀刻媒介而非现行直接利用经由解离后带有电荷的蚀刻气体来进行蚀刻,本实施例的第二蚀刻制作工艺50或无等离子体蚀刻制作工艺可做到所谓无轰击的(bombardment free)效果,进而确保在蚀刻部分阻障层32过程中周边的物件,例如栅极介电层30等不受到任何损害。
除此之外,依据本发明另一实施例,第二蚀刻制作工艺50或无等离子体蚀刻制作工艺可包含一软蚀刻(soft etching)制作工艺,其中该软蚀刻制作工艺较佳选用氯气、氦气或其组合所构成的蚀刻气体来去除部分阻障层32。在本实施例中,阻障层32相对于导电层34的蚀刻选择比较佳控制在大于50%,但不局限于此。
另外,依据本发明又一实施例,第二蚀刻制作工艺50或无等离子体蚀刻制作工艺可利用一蒸气蚀刻制作工艺来去除部分阻障层32。在本实施例中,蒸气蚀刻制作工艺的气体较佳选自由氨气、二氧化氢、盐酸、水以及硫酸所构成的群组,蒸气蚀刻制作工艺的温度介于摄氏25度至摄氏60度,以及蒸气蚀刻制作工艺的压力较佳小于100毫托且大于0毫托。
依据前述三种实施例,经由第一蚀刻与第二蚀刻制作工艺后剩余的阻障层32与导电层34即成为一栅极电极42。随后如图6所示,可形成一硬掩模44于栅极电极42上,并使硬掩模44上表面切齐介电层26上表面,其中硬掩模44较佳包含氮化硅,但不局限于此。至此即完成本发明较佳实施例的一埋藏式字符线的制作。
之后可依据制作工艺需求进行一离子注入制作工艺,以于栅极电极42两侧的基底16内形成一掺杂区(图未示),例如一轻掺杂漏极或源极/漏极区域。最后进行接触插塞制作工艺,例如可分别于栅极电极32两侧形成位线接触插塞电连接源极/漏极区域与后续所制作的位线,以及形成存储节点接触插塞同时电连接源极/漏极区域与后续所制作的电容。
以上所述仅为本发明的较佳实施例,凡依本发明权利要求所做的均等变化与修饰,皆应属本发明的涵盖范围。
Claims (9)
1.一种制作半导体元件的方法,包含:
提供一基底,该基底上具有一存储区;
形成一沟槽于该基底内;
形成一阻障层于该沟槽内;
形成一导电层于该阻障层上;
进行一第一蚀刻制作工艺去除部分该导电层;以及
进行一第二蚀刻制作工艺去除部分该阻障层,其中该第二蚀刻制作工艺包含:
通入一离子化的第一气体至一反应室;
利用一离子过滤器去除该气体中的电荷以形成一第二气体,该第二气体为一不带有电荷的气体;以及
利用该第二气体去除部分该阻障层。
2.如权利要求1所述的方法,其中该第一气体包含氯气。
3.如权利要求1所述的方法,其中该第二气体包含氯原子。
4.如权利要求1所述的方法,另包含:
形成一介电层于该基底上;
形成该沟槽于该介电层及该基底内;
形成一栅极介电层于该沟槽内;
形成该阻障层于该栅极介电层上、该介电层上表面以及该介电层侧壁;
进行该第一蚀刻制作工艺来去除部分该导电层并使该导电层上表面低于该介电层下表面;以及
进行该第二蚀刻制作工艺来去除该介电层上表面的该阻障层以及该介电层侧壁的该阻障层。
5.如权利要求4所述的方法,其中该介电层包含氧化硅。
6.如权利要求1所述的方法,其中该阻障层包含氮化钛。
7.如权利要求1所述的方法,其中该导电层包含钨。
8.一种制作半导体元件的方法,包含:
提供一基底,该基底上具有一存储区;
形成一沟槽于该基底内;
形成一阻障层于该沟槽内;
形成一导电层于该阻障层上;
进行一第一蚀刻制作工艺去除部分该导电层;以及
进行一第二蚀刻制作工艺去除部分该阻障层,其中该第二蚀刻制作工艺包含一无等离子体蚀刻制作工艺,该无等离子体蚀刻制作工艺包含一软蚀刻制作工艺。
9.如权利要求8所述的方法,其中该软蚀刻制作工艺的气体是选自由氯气以及氦气所构成的群组。
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