CN108257929B - 一种散热基板及其制备方法和应用以及电子元器件 - Google Patents
一种散热基板及其制备方法和应用以及电子元器件 Download PDFInfo
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Abstract
本发明涉及用于电子元器件封装的散热基板领域,公开了一种散热基板及其制备方法和应用以及电子元器件。该散热基板包括:金属‑陶瓷复合板,所述金属‑陶瓷复合板为金属层包覆陶瓷体;在所述金属层的外表面上形成有与所述金属层成为一体的金属氧化层;以及在所述金属氧化层的至少部分外表面上形成的导电层,所述导电层形成有导电线路,用于连结和承载芯片。可以提供具有好的抗腐蚀、焊接、结合力性能的散热基板,并降低制得的电子元器件的厚度。同时制备工艺简单,易于工业化,减少镍的使用和废液排放,有利于环保。
Description
技术领域
本发明涉及用于电子元器件封装的散热基板领域,具体地,涉及一种散热基板及其制备方法和应用以及电子元器件。
背景技术
在电子元器件的制备工艺中,通常需要使用封装材料解决电子电路,如芯片的热失效问题。封装材料既需要起到能够承受焊接铜基板并承载芯片的作用,还要同时负责散热。由于进行热交换的过程中封装材料与冷却液相接触,还要求封装材料具有防腐性能。
因此在实际使用中,封装材料通常以基板的形式应用,要求基板的一面焊接铜基板并承载芯片,能够具有焊接功能;相对的另一面与冷却液相接触实现散热,能够具有防腐功能。而为了满足此要求,目前通常的解决方法是将整个基板进行镀镍。但这严格要求基板的表面的质量,如有凹坑、砂眼等,镀镍不能掩盖这些缺陷,会造成焊接优良率低。虽然可以通过镀层结构的设计,增加镀层厚度,但明细增加生产的成本。
CN102534627A公开了一种SiC/Al复合材料表面的发黑处理方法,采用依次进行前处理、阳极氧化、表面金属化、发黑处理的生产流程,得到最终的成品。该方法中经过阳极氧化后,得到SiC/Al复合材料表面氧化膜,然后经过表面金属化得到表面的导电层,再经采用镀镍或黑铬电镀方法的发黑处理得到成品。该方法的目的是解决SiC/Al复合材料在特定的应用场合(用于卫星照相机系统的结构件)需要控制材料对光的反射程度的问题。该方法没有涉及电子元器件的制备工艺中封装材料的制备方法。
CN104183683A公开了一种基于铝基复合材料基板的多芯片LED封装方法,包括:将铝基复合材料进行表面抛光,再在表面蒸发一层铝膜;将沉积好铝膜的衬底进行掩膜光刻,然后进行选择性阳极氧化,使用作绝缘层的铝膜完全氧化成多孔型氧化铝层;在阳极氧化好的衬底表面溅射金属籽晶层,通过光刻、显影得到表面电极图形,然后通过电镀加厚所述表面电极图形,得到表面电极金属层,去除光刻胶和腐蚀籽晶层,获得大功率LED封装的表面道题布线和电极焊区;在所述衬底表面电极焊区进行LED的多芯片微组装与微互连,最后进行透明外壳的封装。该方法在基板的表面沉积铝膜之后,再将铝膜氧化以提供氧化层,以解决LED特殊封装要求的散热问题。
现有技术在电子元器件的制备工艺中采取镀镍方法解决封装材料的散热和防腐问题,但是存在产品优良率低,成本高的缺陷。
发明内容
本发明的目的是为了解决封装电子元器件所使用的散热基板存在的上述问题,提供一种散热基板及其制备方法和应用以及电子元器件。
为了实现上述目的,本发明提供一种散热基板,其中,该散热基板包括:金属-陶瓷复合板,所述金属-陶瓷复合板为金属层包覆陶瓷体;在所述金属层的外表面上形成有与所述金属层成为一体的金属氧化层;以及在所述金属氧化层的至少部分外表面上形成的导电层,所述导电层形成有导电线路,用于连结和承载芯片。
本发明还提供了一种制备本发明的散热基板的方法,包括:将金属-陶瓷复合板直接进行金属氧化,其中,所述金属-陶瓷复合板为金属层包覆陶瓷体的复合板材;在金属层的外表面上形成与金属成为一体的金属氧化层;在所述金属氧化层的至少部分外表面上形成导电层。
本发明还提供了一种本发明的散热基板在电子元器件中的应用。
本发明还提供了一种电子元器件,其中,该电子元器件包括:散热基板,所述散热基板具有导电层;以及在所述导电层的至少部分外表面上依次层叠地形成的焊层和芯片,所述芯片与所述导电层通过导线连接;所述散热基板为本发明的散热基板。
通过上述技术方案,采取在金属-陶瓷复合板的金属层外表面上原位直接氧化形成金属氧化层,可以提供具有散热、防腐和焊接功能的散热基板,该散热基板的结合强度更大,可以更好地承载芯片,克服已有技术中采取镀镍方法的缺陷。通过上述技术方案,可以提供得到的散热基板进行中性盐雾测试有更好的防腐蚀性能;可以提供得到的散热基板进行结合性能测试,金属氧化层与金属-陶瓷复合板的金属层有更好的结合强度;可以提供得到的散热基板进行静滴法测试具有好的润湿性能,好的焊接性能。
该散热基板在金属氧化层的外表面可以直接形成导电层,有导电线路,在形成电子元器件时可以直接用于连接芯片,实现节省焊接金属层、衬板和多余的焊层与铜基板,从而降低电子元器件的厚度。
本发明的其它特征和优点将在随后的具体实施方式部分予以详细说明。
附图说明
附图是用来提供对本发明的进一步理解,并且构成说明书的一部分,与下面的具体实施方式一起用于解释本发明,但并不构成对本发明的限制。在附图中:
图1为散热基板的结构示意图;
图2为电子元器件的结构示意图;
图3为静滴法测试接触角θ示意图。
附图标记说明
1、金属-陶瓷复合板 2、金属氧化层 3、导电层
4、焊层 5、导线 6、芯片
具体实施方式
以下对本发明的具体实施方式进行详细说明。应当理解的是,此处所描述的具体实施方式仅用于说明和解释本发明,并不用于限制本发明。
在本文中所披露的范围的端点和任何值都不限于该精确的范围或值,这些范围或值应当理解为包含接近这些范围或值的值。对于数值范围来说,各个范围的端点值之间、各个范围的端点值和单独的点值之间,以及单独的点值之间可以彼此组合而得到一个或多个新的数值范围,这些数值范围应被视为在本文中具体公开。
本发明的第一目的,提供一种散热基板,如图1所示,其中,该散热基板包括:金属-陶瓷复合板1,所述金属-陶瓷复合板为金属层包覆陶瓷体;在所述金属层的外表面上形成有与所述金属层成为一体的金属氧化层2;以及在所述金属氧化层的至少部分外表面上形成的导电层3,所述导电层形成有导电线路,用于连结和承载芯片。
根据本发明,所述金属氧化层通过将所述金属层直接进行氧化而形成,包覆所述金属层。所述金属氧化层由所述金属层直接原位氧化形成,可以结合强度更大。可以通过金相显微镜进行照相观察,观察本发明提供的散热基板的截面,所述金属-陶瓷复合板的金属层和所述金属氧化层之间没有分界。而如果通过涂覆或沉积金属层再氧化得到金属氧化层,则通过金相显微镜观察在所述金属-陶瓷复合板的金属层与形成的金属氧化层之间存在明显的分界。进一步地,所述金属氧化层可以设置焊接面(或A面)和散热面(或B面)。焊接面(或A面)与散热面(或B面)可以是所述散热基板上两个相对的面,且一般是所述散热基板上面积最大的两个面。所述导电层仅设置在所述焊接面上可以进一步用于焊接芯片。所述散热面可以与冷却液相接触用于散热。优选情况下,所述导电层设置在所述散热基板一侧的所述金属氧化层上;另一侧的所述金属氧化层用于与冷却液接触,进行散热。
本发明中,优选地,所述导电层用于形成导电线路,可以进一步与后续焊接的芯片连接。
本发明中,提供的散热基板可以通过原位氧化形成金属氧化层具有更好的结合强度、焊接性能和抗腐蚀性能,进而可以直接形成导电层,在进一步封装芯片形成电子元器件时实现电子元器件结构上减少常规的焊接金属层、衬板等部件,降低电子元器件的厚度。
根据本发明,所述散热基板可以选用电子元器件封装材料中常规使用的基板材料作为基材,例如可以是含有金属的基材,可以优选金属-陶瓷复合板作为基材。进而在此基材上形成所述金属氧化层、导电层。优选情况下,所述陶瓷体选自SiC陶瓷体或Si陶瓷体;所述金属层为Al金属层、Mg金属层或Ti金属层。所述金属-陶瓷复合板可以商购获得。陶瓷体的厚度可以没有特别的限定,可以是3mm左右。
根据本发明,所述金属氧化层为所述金属层原位形成,所述金属氧化层为与所述金属层所使用的金属相应的氧化物。所述金属氧化层为氧化铝层、氧化镁层或氧化钛层。
根据本发明,所述导电层可以选用常规的导电材料形成。优选地,所述导电层为铜金属层或银金属层。
根据本发明,所述散热基板中包括的各层的厚度能够实现散热、防腐以及承载芯片的功能即可,优选情况下,所述金属层的厚度为20~500μm;所述金属氧化层的厚度为5~300μm;所述导电层的厚度为3~400μm。
根据本发明,所述散热基板中的所述金属层和所述金属氧化层可以具有更好的结合强度。优选情况下,所述金属氧化层与所述金属层的结合强度达到20MPa以上,优选结合强度达到20~30MPa。所述结合强度可以通过GB/T 8642-2002测试。
本发明中,一种优选实施方式,所述导电层设置在所述散热基板的一侧。优选地,在所述散热基板上,设置有所述导电层的一侧的金属氧化层厚度大于或等于另一侧的金属氧化层厚度。即在所述焊接面(如前所述,所述散热基板上形成有所述导电层的一侧)上的金属氧化层厚度要大于或等于所述散热面(如前所述,与所述散热基板上形成有所述导电层的一侧相对的另一侧)上的金属氧化层厚度。例如所述焊接面上的金属氧化层厚度可以为80~300μm,散热面上的金属氧化层的厚度为40~100μm。
本发明的第二目的,提供了一种制备本发明的散热基板的方法,包括:将金属-陶瓷复合板直接进行金属氧化,在金属的外表面上形成与金属成为一体的金属氧化层;在所述金属氧化层的至少部分外表面上形成导电层;其中,所述金属-陶瓷复合板为金属包覆陶瓷体的复合板材。
根据本发明,可以选用已有的适用于电子元器件封装的材料,可以是含金属的材料,例如可以是金属-陶瓷复合板作为形成所述散热基板的基材。其中,所述陶瓷体可以选自SiC陶瓷体或Si陶瓷体;所述金属层可以选自Al金属层、Mg金属层或Ti金属层。陶瓷体的厚度可以没有特别的限定,可以是3mm左右。所述金属层的厚度可以为20~500μm。进一步地,可以通过所述金属氧化在金属-陶瓷复合板中的金属层外表面上直接原位形成金属氧化层。如金属层为Al金属层,则得到氧化铝层;金属层为Mg金属层,则得到氧化镁层;金属层为Ti金属层,则得到氧化钛层。
本发明中,可以将所述散热基板上面积大的两个面作为前述的焊接面和散热面。一种优选实施方式,所述焊接面上的金属氧化层厚度大于或等于所述散热面上的金属氧化层厚度。所述焊接面可以用于进一步设置依次层叠的导电层、焊层和芯片。所述散热面与冷却液相接触用于起到散热作用。优选地,形成所述焊接面和散热面上的金属氧化层厚度不同的方法可以是:单面阴极氧化、遮蔽氧化或二次氧化。
本发明中,单面阴极氧化的方法可以为:将焊接面的金属氧化层面向阴极,散热面则不设置阴极。遮蔽氧化的方法可以为:设置挡板造成焊接面和散热面两面氧化厚度不同。二次氧化的方法可以例如为:在散热面用夹具遮掩防止接触药水,氧化到一定厚度(约40μm)时去除夹具,进行两面均匀氧化,可以实现焊接面和散热面上金属氧化层的厚度具有约40μm的差异。
本发明中,所述金属氧化可以有多种具体的实施方法,只要在金属-陶瓷复合板中的金属层外表面上形成满足需要厚度的金属氧化层即可。优选情况下,所述金属氧化的方法可以包括阳极氧化或微弧氧化。具体地,阳极氧化的方法和条件包括:将金属-陶瓷复合板除去表面油污和表面氧化层,然后放入化学氧化溶液中通电10~30min进行封闭处理。所述封闭处理可以采用热水封闭。所述氧化溶液为含有180~220g/L的硫酸溶液,温度为-5℃~25℃,电压为10~22V,电流密度为0.5~2.5A/dm2。
微弧氧化的方法和条件包括:将金属-陶瓷复合板除去表面油污后放入微弧氧化槽中的微弧氧化液中通电进行微弧氧化,微弧氧化完成后进行热水封闭。所述微弧氧化液一般为弱碱性溶液,可以含有硅酸盐、磷酸盐、硼酸盐等。微弧氧化的温度控制在20~60℃,电压一般可控制在400~750V。所述微弧氧化也可以采用低压微弧氧化技术实施。
本发明的一种优选实施方式,形成的所述金属氧化层的厚度可以为5~300μm。进一步地,所述焊接面上的金属氧化层厚度可以为80~300μm,散热面上的金属氧化层的厚度为40~100μm。
根据本发明,所述导电层用于形成导电线路,可用于进一步连接芯片。优选情况下,形成所述导电层的方法包括:在所述金属氧化层上进行表面遮蔽后,喷涂导电金属得到导电线路形成所述导电层;或者,在所述金属氧化层上进行喷涂或溅射镀导电金属后,掩模蚀刻得到导电线路形成所述导电层。所述导电金属可以选自铜或银,为粉末状,平均颗粒直径为1~50μm。可以是已知物质,如商购天久金属材料有限公司TITD-Q Cu牌号的37μm铜粉获得。实施所述喷涂实现获得足够厚度和需要的导电线路形成所述导电层即可,优选地,经过形成所述导电层的方法可以形成的所述导电层的厚度为3~400μm。
本发明中,形成所述导电层采用的喷涂可以是冷喷涂,包括:将形成的金属氧化层的表面去除油污,再经硼砂处理,然后进入冷喷涂工序:气体为氮气和/或He;冷喷涂压力为1.5~3.5MPa;喷涂距离为10~50mm;送粉速度为3~15kg/h。其中,送粉速度是指进行所述冷喷涂时喷涂所述导电金属的速度。
本发明中,进行所述喷涂时,可以将所述金属氧化层上不需要喷涂的部分采用遮蔽的方法进行保护。
本发明中,上述制备方法还可以包括:将所述金属-陶瓷复合板先进行预处理,将所述金属-陶瓷复合板进行除油除蜡,并进一步去除因自然氧化在所述金属-陶瓷复合板的金属层外表面上形成的氧化层,然后再进行本发明提供的上述制备方法中的所述金属氧化。例如,除油除蜡可以将所述金属-陶瓷复合板在酒精溶液中浸泡5min,或者采用除油粉U-151(安美特)在50℃下浸泡5min。除去因自然氧化形成的氧化层的方法和条件可以为将所述金属-陶瓷复合板在浓度为50g/L的氢氧化钠水溶液中浸泡3min,或者在室温下浸泡在由热浸电解除垢粉U-152配置成的槽液中1min。
本发明中,上述制备方法还可以包括:在完成所述金属氧化步骤之后,将得到的板材进行封闭并烘干,然后再进行所述金属喷涂。其中封闭的作用可以是将氧化过程形成的孔封闭。可以采用沸水封孔的方法实现封闭。烘干可以采用在80~100℃下烘干20~30min即可。
本发明的第三目的,提供了一种本发明的散热基板在电子元器件中的应用。可以用作封装材料。
本发明的第四目的,提供了一种电子元器件,如图2所示,其中,该电子元器件包括:散热基板1,所述散热基板具有导电层3;以及在所述导电层的至少部分外表面上依次层叠地形成的焊层4和芯片6,所述芯片与所述导电层通过导线5连接;所述散热基板为本发明的散热基板。所述散热基板包括:金属层包覆陶瓷体的金属-陶瓷复合板;在所述金属层的外表面上形成的且与所述金属层成为一体的金属氧化层;以及在所述金属氧化层的至少部分外表面上形成所述导电层。
本发明的所述电子元器件中,所述散热基板提供承载芯片和芯片散热的功能。所述散热基板形成有所述导电层的一侧进一步设置焊层和芯片,承载芯片;而相对的另一侧没有所述导电层,可以与冷却液接触,作为冷却面提供芯片散热。由于冷却液具有腐蚀性,所述散热基板的冷却面具有直接氧化所述金属层而原位形成的所述金属氧化层,可以提供防腐功能。
本发明的电子元器件中,所述焊层用于提供连结所述导电层和芯片。所述焊层可以是通过锡焊方法采用锡膏形成。
本发明的电子元器件中,所述导线连接所述芯片和所述导电层,也可以采用本领域常规的方法,不再赘述。
以下将通过实施例对本发明进行详细描述。
以下实施例和对比例中,金属-陶瓷复合板为Al-SiC复合板,HWT科技有限公司;
焊接性能通过静滴法(Sessile Drop)测试:将融溶焊料液体滴落在洁净光滑的散热基板的导电层表面上,待达到平衡稳定状态后拍照如图3所示。放大照片直接测量接触角θ,并通过θ角计算相应的液-固界面张力。该法中接触角θ可用于表征润湿合格与否:θ<90°,称为润湿;θ>90°,称为不润湿:θ=0°,称为完全润湿;θ=180°,称为完全不润湿。润湿代表焊接性好,“OK”表示;不润湿代表焊接性不好。
散热基板的抗腐蚀性能通过中性盐雾测试:将散热基板倾斜15°~30°,使待测试表面能同时接受盐水的喷雾;条件为(5±0.1)%NaCl溶液;pH值在6.5~7.2之间;盐雾沉降量:1~2ml/80cm2·h;温度:35±2℃。观察测试样品表面,记录出现起泡、锈蚀的时间。
实施例中散热基板的金属氧化层与金属-陶瓷复合板之间的结合强度,以及对比例中散热基板的镍层与金属-陶瓷复合板之间的结合强度按照GB/T8642-2002测试。
实施例1
本实施例说明本发明的散热基板及其制备方法。
将Al-SiC复合板(SiC的厚度为3mm,Al的厚度为100μm)采用除油粉U-151(安美特)在50℃下浸泡5min进行除油除蜡,然后在室温下浸泡在由热浸电解除垢粉U-152配置成的槽液中1min进行去氧化层,得到待氧化的基板;
将待氧化的基板的一侧作为散热面用夹具遮掩,然后放入含有180g/L硫酸(98重量%)的氧化溶液中,在-5℃、10V和1A/cm3下进行第一次阳极氧化50min,在未遮掩的一侧得到厚度为40μm的氧化铝层作为焊接面;去除夹具再放入上述氧化溶液中同条件下进行第二次阳极氧化,然后以纯净水在95℃下进行封闭5min,再在80℃下烘干30min;得到待喷涂的基板;散热面的氧化铝层厚度为40μm,焊接面的氧化铝层厚度为80μm;
用绘制有导电线路图案的治具遮蔽待喷涂基板的焊接面的局部,然后进行冷喷涂铜:氮气、压力为2.5MPa、喷涂距离为30mm、送铜粉(TITD-Q Cu)速度为10kg/h,得到厚度为10μm的导电层;得到散热基板。
将散热基板进行焊接性能、抗腐蚀性能、结合性能测试,结果见表2。
实施例2
本实施例说明本发明的散热基板及其制备方法。
将Al-SiC复合板(SiC的厚度为3mm,Al的厚度为300μm)在酒精中浸泡5min进行除油除蜡,然后在50g/L的氢氧化钠水溶液中浸泡3min,得到待氧化的基板;
将待氧化的基板的一侧作为散热面用夹具遮掩,然后放入含有180g/L硫酸(98重量%)的氧化溶液中,在-5℃、22V和1A/cm3下进行第一次阳极氧化80min,在未遮掩的一侧得到厚度为100μm的氧化铝层作为焊接面;去除夹具再放入上述氧化溶液中同条件下进行第二次阳极氧化,然后以纯净水在95℃下进行封闭5min,再在80℃下烘干30min;得到待喷涂的基板;散热面的氧化铝层厚度为100μm,焊接面的氧化铝层厚度为200μm;
用绘制有导电线路图案的治具遮蔽待喷涂基板的焊接面的局部,然后进行冷喷涂铜:氮气、压力为3MPa、喷涂距离为40mm、送铜粉速度10kg/h,得到厚度为400μm的导电层。得到散热基板。
将散热基板进行焊接性能、抗腐蚀性能、结合性能测试,结果见表2。
实施例3
本实施例说明本发明的散热基板及其制备方法。
将Al-SiC复合板(SiC的厚度为3mm,Al的厚度为500μm)采用除油粉U-151(安美特)在50℃下浸泡5min进行除油除蜡,然后在室温下浸泡在由热浸电解除垢粉U-152配置成的槽液中1min进行去氧化层,得到待氧化的基板;
将待氧化的基板的一侧作为散热面用夹具遮掩,然后放入含有180g/L硫酸(98重量%)的氧化溶液中,在-5℃、22V和1A/cm3下进行第一次阳极氧化90min,在未遮掩的一侧得到厚度为70μm的氧化铝层作为焊接面;去除夹具再放入上述氧化溶液中同条件下进行第二次阳极氧化,然后以纯净水在95℃下进行封闭5min,再在80℃下烘干30min;得到待喷涂的基板;散热面的氧化铝层厚度为70μm,焊接面的氧化铝层厚度为140μm;
用绘制有导电线路图案的治具遮蔽待喷涂基板的焊接面的局部,然后进行冷喷涂铜:氦气、压力为2MPa、喷涂距离为30mm、送铜粉速度为10kg/h,得到厚度为300μm的导电层。得到散热基板。
将散热基板进行焊接性能、抗腐蚀性能、结合性能测试,结果见表2。
实施例4
将实施例1的散热基板采用锡膏通过锡焊方法,在导电层上形成焊层;再在焊层上连结芯片并引线连接芯片与导电层,得到电子元器件,结构如图2所示,电子元器件的总厚度为4.3mm。
对比例1
将Al-SiC复合板(SiC的厚度为3mm,Al的厚度为100μm)采用ERPREP Flex(安美特)在50℃下浸泡5min进行除油除蜡,然后在由Actane 4322s配置成的槽液中浸泡3min进行去氧化层;得到处理基板;
将处理基板按照表1所示的流程进行镀镍,得到厚度为10μm的镍层;得到散热基板。其中化学品商购乐思化学的产品。
表1
将散热基板进行焊接性能、抗腐蚀性能、结合性能测试,结果见表2。
对比例2
按照实施例4的方法,将对比例1制得的散热基板用于封装芯片,在镍层上依次层叠第一焊层、第一铜基板、衬板、第二铜基板、第二焊层和芯片,制备为电子元器件。电子元器件的总厚度为5.13mm。
表2
编号 | 焊接性能 | 抗腐蚀性能 | 结合性能 |
实施例1 | OK | 1000h | 20MPa |
实施例2 | OK | 1000h | 30MPa |
实施例3 | OK | 1000h | 25MPa |
对比例1 | OK | 24h | 10MPa |
由实施例、对比例和表2的数据结果可以看出,本发明提供的散热基板可以同时具有好的抗腐蚀性能、结合性能、焊接性能。同时本发明提供散热基板的工艺更简单,工业化方便,且减少了镍的使用,降低了成本以及镍废液的排放,本发明以更环保的方式提供了性能更好的散热基板。而对比例得到的散热基板可以满足焊接性能,但是抗腐蚀性能和结合性能都很差。
而且,对比实施例4和对比例2可以看出,本发明提供的散热基板可以制备降低电子元器件的厚度。
Claims (9)
1.一种散热基板,其特征在于,该散热基板包括:
金属-陶瓷复合板,所述金属-陶瓷复合板为金属层包覆陶瓷体;
在所述金属层的外表面上形成有与所述金属层成为一体的金属氧化层;以及
在所述金属氧化层的至少部分外表面上形成的导电层,所述导电层形成有导电线路,用于连结和承载芯片;
其中,所述金属氧化层通过将所述金属层直接进行氧化而形成;
所述导电层设置在所述散热基板的一侧;以及
在所述散热基板上,设置有所述导电层的一侧的金属氧化层厚度大于或等于另一侧的金属氧化层厚度,并且设置有所述导电层的一侧的金属氧化层厚度为80~300μm,另一侧的金属氧化层厚度为40~100μm;
所述陶瓷体选自SiC陶瓷体或Si陶瓷体;
所述金属氧化层与所述金属层的结合强度达到20MPa以上。
2.根据权利要求1所述的散热基板,其中,所述金属层为Al金属层、Mg金属层或Ti金属层;所述金属氧化层为氧化铝层、氧化镁层或氧化钛层;所述导电层为铜金属层或银金属层。
3.根据权利要求2所述的散热基板,其中,所述金属层的厚度为20~500μm;所述导电层的厚度为3~400μm。
4.一种制备权利要求1-3中任意一项所述的散热基板的方法,包括:将金属-陶瓷复合板直接进行金属氧化,其中,所述金属-陶瓷复合板为金属层包覆陶瓷体的复合板材;在金属层的外表面上形成与金属成为一体的金属氧化层;在所述金属氧化层的至少部分外表面上形成导电层。
5.根据权利要求4所述的方法,其中,所述金属氧化的方法包括阳极氧化或微弧氧化。
6.根据权利要求4或5所述的方法,其中,形成所述导电层的方法包括:在所述金属氧化层上进行表面遮蔽后,喷涂导电金属得到导电线路形成所述导电层;或者,在所述金属氧化层上进行喷涂或溅射镀导电金属后,掩模蚀刻得到导电线路形成所述导电层。
7.根据权利要求4或5所述的方法,其中,形成的所述金属氧化层的厚度为5~300μm;形成的所述导电层的厚度为3~400μm。
8.一种权利要求1-3中任意一项所述的散热基板在电子元器件中的应用。
9.一种电子元器件,其特征在于,该电子元器件包括:
散热基板,所述散热基板具有导电层;以及
在所述导电层的至少部分外表面上依次层叠地形成的焊层和芯片,所述芯片与所述导电层通过导线连接;
所述散热基板为权利要求1-3中任意一项所述的散热基板。
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101039548A (zh) * | 2006-03-17 | 2007-09-19 | 三星电机株式会社 | 阳极氧化金属基板模块 |
CN202454546U (zh) * | 2011-09-12 | 2012-09-26 | 英飞凌科技股份有限公司 | 半导体器件 |
CN103687419A (zh) * | 2012-09-04 | 2014-03-26 | 富瑞精密组件(昆山)有限公司 | 散热器及其制造方法 |
CN104465535A (zh) * | 2013-09-24 | 2015-03-25 | 英飞凌科技股份有限公司 | 衬底、芯片布置及其制造方法 |
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CN103413791A (zh) * | 2013-08-22 | 2013-11-27 | 广州天极电子科技有限公司 | 一种散热良好的陶瓷覆铜膜热沉模块及其制造方法 |
CN104064478B (zh) * | 2014-06-24 | 2016-08-31 | 南京航空航天大学 | 一种铜/氮化铝陶瓷复合导热基板的制作方法 |
CN104362099A (zh) * | 2014-09-17 | 2015-02-18 | 上海申和热磁电子有限公司 | 高热导覆铜陶瓷基板的制备方法 |
US10497636B2 (en) * | 2015-11-20 | 2019-12-03 | AZ Power Inc. | Passivation for silicon carbide (SiC) device and method for fabricating same |
US10199266B2 (en) * | 2016-12-26 | 2019-02-05 | Intel Corporation | Integrated circuit interconnect structure having metal oxide adhesive layer |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101039548A (zh) * | 2006-03-17 | 2007-09-19 | 三星电机株式会社 | 阳极氧化金属基板模块 |
CN202454546U (zh) * | 2011-09-12 | 2012-09-26 | 英飞凌科技股份有限公司 | 半导体器件 |
CN103687419A (zh) * | 2012-09-04 | 2014-03-26 | 富瑞精密组件(昆山)有限公司 | 散热器及其制造方法 |
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