CN108235786B - 垂直纳米线mosfet制造中的垂直后栅极工艺的方法 - Google Patents

垂直纳米线mosfet制造中的垂直后栅极工艺的方法 Download PDF

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CN108235786B
CN108235786B CN201680035096.2A CN201680035096A CN108235786B CN 108235786 B CN108235786 B CN 108235786B CN 201680035096 A CN201680035096 A CN 201680035096A CN 108235786 B CN108235786 B CN 108235786B
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CN108235786A (zh
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拉尔斯-埃里克·维尔纳松
马丁·贝里
卡尔-芒努斯·佩尔松
约翰内斯·斯文松
埃里克·林德
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Ai LikeLinde
Ka Er MangnusiPeiersong
Ma DingBeili
La Ersi AilikeWeiernasong
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Ka Er MangnusiPeiersong
Ma DingBeili
La Ersi AilikeWeiernasong
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Abstract

本发明涉及一种使用后栅极工艺的垂直纳米线MOSFET制造方法。首先制造顶部欧姆电极，并且其可以用作掩模以利用蚀刻技术形成栅极凹陷。随后形成栅极，其在很大程度上降低了接入电阻。

Description

垂直纳米线MOSFET制造中的垂直后栅极工艺的方法
技术领域
本发明大体上涉及垂直金属-氧化物-半导体场效应晶体管(MOSFET)的制造，特别是涉及在自对准后栅极工艺中的垂直纳米线MOSFET的制造、以及其在电子电路中的应用。
背景技术
垂直纳米线MOSFET可以实现细通道的较小占用面积(foot-prints)，其通过围栅几何形状而具有良好的静电控制。纳米线直径的减少可以改善静电性并减小占用面积，但其显示出外部串联电阻的增加。沿纳米线轴向的高精度掺杂控制已被证明是不充分的，而且非常具有挑战性。纳米线直径越小，会增加金属-半导体的接触电阻，这是因为面积变小。此外，欧姆接触通常需要高温退火工艺以达到足够低的比接触电阻率，然而栅介质的电特性和结构特性对高温工艺敏感。后栅极工艺通常用于平面技术，其中在栅极确定之前便制作源区和漏区及其电接触。
发明内容
为了解决上述问题，本发明应用了自对准后栅极工艺，其使用数字化刻蚀从而可以使栅区中纳米线直径局部减少，并同时实现内部沟道和掺杂接触区。此外，该工艺还可以在同一样品上并联制造具有不同栅长的MOSFET。
考虑到上述描述，然后，本发明的一些实施方案的一个方面提供一种技术，其试图以单独的方式或以任何组合的方式缓和、减轻或消除本领域中的一个或多个上述提及的缺陷和缺点。
本发明的一个方面涉及在栅极形成之前制作顶部欧姆接触的技术。
本发明的另一个方面涉及垂直MOSFET的制造，其中，首先沉积顶部金属电极，然后将其用作蚀刻掩模，以在栅极确定之前减小纳米线晶体管通道的直径。
本发明的又一个方面涉及通过使用替换掩模(其被用作蚀刻掩模)以在栅极确定之前形成顶部接触区，从而减小纳米线晶体管通道的直径。随后，将该替换掩模移除并以金属接触代替。
在又一个实施方案中，将在后栅极工艺中制造的垂直纳米线MOSFET用于数字化应用中，其中将一根或几根纳米线连接成组以形成电路。
在又一个实施方案中，将在后栅极工艺中制造的垂直纳米线MOSFET用于RF应用或毫米波应用中，其中将一根或几根纳米线连接成组以形成电路。
在又一个实施方案中，将在后栅极工艺中制造的垂直纳米线MOSFET用于混合模式应用或存储器应用中，其中将一根或几根纳米线连接成组以形成电路。
本发明的另一个方面涉及采用后栅极工艺制造的垂直MOSFET的形成，其中同一样品上的MOSFET之间的栅长是不同的。
本发明的另一个方面涉及采用后栅极工艺制造的垂直隧穿场效应晶体管(FET)的形成，其中纳米线由轴向pn结组成，栅极对准该结以实现隧穿FET。
上述实施方案的特征可以以任意组合方式进行组合。
附图简要说明
本发明的其他目的、特征和优点将通过本发明的以下详细描述而理解，其中将参考附图以更详细地描述本发明的实施方案，其中：
图1是在后栅极工艺中制造的垂直MOSFET的示意图。
图2是垂直纳米线MOSFET的SEM显微照片。
图3是垂直纳米线MOSFET的所测量得到的输出特性。
图4是垂直纳米线MOSFET的所测量得到的传输特性。
具体实施方式
下面将参照附图更全面地描述本发明的实施方案，其中在附图中示出了本发明的实施方案。然而，本发明可以以许多不同的形式来实施，并且不应该被解释为限制于本文中所列举的实施方案。相反，提供这些实施方案是为了使本公开内容透彻且完整，并将本发明的范围充分地传达给本领域技术人员。在全文中，相同的参考符号始终指代相同的元件。
在半导体衬底(如Si或III-V族复合材料)上制作纳米线MOSFET。纳米线可以直接生长在衬底上，或者生长在沉积于半导体晶片上的外延层上。可以通过使用气-液-固法的金属有机化合物气相外延，从而在电子束限定的Au颗粒上生长III-V族或IV族纳米线(例如InAs、InGaAs、GaSb、Si及其组合)。或者，也可以使用其他方法来生长纳米线，例如在具有电介质(SiO2或SiNx)掩模的衬底上生长。也可以通过在自上而下的工艺中蚀刻半导体晶片来限定纳米线。此外，纳米线可以暴露于再生长步骤，其中沿着纳米线使用一个或多个掩模，从而可以在沿着纳米线的一个、两个或多个区域中沉积半导体材料。纳米线可以以某种构型排列，例如排列成具有200nm间距的双排阵列或六边形图案。另外，纳米线可具有均匀的材料组成和掺杂程度，或者，纳米线也可以由不同的掺杂或材料组成的轴向区段形成，例如200nm长的未掺杂底部部分，随后是400nm长的高度掺杂部分。对于隧穿FET，纳米线可以由GaAs/InAs pn结组成，其中栅极位于紧邻异质结的位置。纳米线可进一步包含在核/壳异质结构中形成的径向异质结构或掺杂变化，例如由高度掺杂的InAs(或InGaAs)壳过度生长得到的内部核InAs(或InGaAs)。这里，纳米线可以是指由一种单一材料组成的半导体棒，或者是指由核/壳纳米线组成的半导体棒，其中在该核/壳纳米线中，第二材料外延生长于第一纳米线的侧面上以用来提供增强的功能，例如通道接入电阻，输送增强的应变减少、或表面钝化。或者，也可以考虑轴向异质结构纳米线，其中在纳米线中组合了两种或多种不同的材料及掺杂程度区段。这些纳米线可以在垂直MOSFET中用作晶体管通道，在该垂直MOSFET中，在纳米线的顶部形成顶部电极，并且用作与纳米线的欧姆接触。电极可以由金属接触以及半导体接触区组成。栅极位于顶部电极的下方，而第三电极位于栅极的下方、或者位于与纳米线相连的衬底上。第三电极用作与晶体管的第二欧姆接触。
在本发明的第一实施方案中，在栅极形成之前形成顶部欧姆晶体管电极。
在第一步骤中，通过一层或若干层有机层或无机层(例如，氢倍半硅氧烷(HSQ)、SiNx、SiO2、BCB、光刻胶)保护纳米线的底部。为了实现对栅长的控制，通过(例如)下述方式控制每根纳米线周围的层厚度，例如通过控制暴露剂量，或者通过蚀刻从而将层的局部减薄，或者通过沉积从而局部添加材料。通过金属沉积形成顶部金属接触，例如溅射20nm的W和原子层沉积(ALD)5nm的TiN、或沉积Ni。这种金属通过(例如)以下方法进行各向异性蚀刻：进行干法蚀刻，移除平面层，并且仅保留位于纳米线侧壁上的金属。随后，将保护层移除。
在第二步骤中，沉积诸如SiO2之类的有机或无机间隔层，其中该层的厚度比第一保护层薄。
在第三步骤中，通过(例如)原子层沉积而沉积得到高κ氧化物，其由(例如)Al2O3、HfO2、ZrO2或其组合组成。
在第四步骤中，通过(例如)溅射的W来沉积金属栅极。由此最终限定了金属栅长，而栅极-漏极和栅极-源极间距分别由保护层的厚度和间隔层的厚度来限定。
然后，在第五步骤中，通过分别接触栅极和晶体管顶部欧姆接触，以及形成底部电极，从而完成了晶体管工艺。
在第二实施方案中，在栅极形成之前，形成顶部欧姆晶体管电极。
在第一步骤中，将欧姆接触沉积在晶体管的栅极区的下方。
在第二步骤中，底部欧姆接触上方的区域由有机层或无机层保护，例如氢倍半硅氧烷(HSQ)、SiNx、SiO2、BCB、光刻胶。为了实现对栅长的控制，通过(例如)下述方式控制每根纳米线周围的层厚度，例如通过控制暴露剂量，或者通过蚀刻从而将层的局部减薄，或者通过沉积从而局部添加材料。通过金属沉积形成顶部金属接触，例如溅射20nm的W和原子层沉积(ALD)5nm的TiN、或沉积Ni。这种金属通过(例如)以下方法进行各向异性蚀刻：进行干法蚀刻，移除平面层，并且仅保留位于纳米线侧壁上的金属。随后，将保护层移除。
在第三步骤中，沉积有机或无机间隔层，例如SiO2，其中该层的厚度比第一保护层薄。
在第四步骤中，通过(例如)原子层沉积而沉积得到高κ氧化物，其由(例如)Al2O3、HfO2、ZrO2或其组合组成。
在第五步骤中，通过(例如)溅射的W来沉积金属栅极。由此最终限定了金属栅长，而栅极-漏极和栅极-源极间距分别由保护层的厚度和间隔层的厚度来限定。
然后，在第六步骤中，通过分别接触栅极和晶体管顶部欧姆接触，以及形成底部电极，从而最终完成了晶体管工艺。
在第三实施方案中，在栅极形成之前形成顶部欧姆晶体管电极。
在第一步骤中，通过有机层或无机层(例如，氢倍半硅氧烷(HSQ)、SiNx、SiO2、BCB、光刻胶)保护纳米线的底部。为了实现对栅长的控制，通过(例如)下述方式控制每根纳米线周围的层厚度，例如通过控制暴露剂量，或者通过蚀刻从而将层的局部减薄，或者通过沉积从而局部添加材料。通过金属沉积形成顶部金属接触，例如溅射20nm的W和原子层沉积(ALD)5nm的TiN、或沉积Ni。这种金属通过(例如)以下方法进行各向异性蚀刻：进行干法蚀刻，移除平面层，并且仅保留位于纳米线侧壁上的金属。随后，将保护层移除。
在第二步骤中，沉积有机或无机间隔层，例如SiO2，其中该层的厚度比第一保护层薄。
在第三步骤中，使用顶部电极和间隔层作为掩模以蚀刻纳米线，从而形成凹陷区。可以采用交替使用O3氧化和HCl:H2O(1:10)的纳米线的数字化刻蚀。可以通过这种方式在纳米线的一部分上对高度掺杂的壳进行局部蚀刻，并且将直径修整为所需的尺寸(3-50nm)。
在第四步骤中，通过(例如)原子层沉积而沉积得到高κ氧化物，其由(例如)Al2O3、HfO2、ZrO2或其组合组成。
在第五步骤中，通过(例如)溅射的W来沉积金属栅极。由此最终限定了金属栅长，而栅极-漏极和栅极-源极间距分别由保护层的厚度和间隔层的厚度来限定。
然后，在第六步骤中，通过分别接触栅极和晶体管顶部欧姆接触，以及形成底部电极，从而完成了晶体管工艺。
在第四实施方案中，在栅极形成之前限定顶部欧姆晶体管电极的延伸。
在第一步骤中，通过有机层或无机层(例如，氢倍半硅氧烷(HSQ)、SiNx、SiO2、BCB、光刻胶)保护纳米线的底部。为了实现对栅长的控制，通过(例如)下述方式控制每根纳米线周围的层厚度，例如通过控制暴露剂量，或者通过蚀刻从而将层的局部减薄，或者通过沉积从而局部添加材料。通过掩模(例如SiNx或SiO2)的各向同性沉积来限定顶部接触。这种掩膜通过(例如)以下方法进行各向异性蚀刻：进行干法蚀刻，移除平面层，并且仅保留位于纳米线侧壁上的掩膜。随后，将保护层移除。
在第二步骤中，沉积有机或无机间隔层，例如SiO2，其中该层的厚度比第一保护层薄。
在第三步骤中，使用顶部电极和间隔层作为掩模以蚀刻纳米线，从而形成凹陷区。可以采用交替使用O3氧化和HCl:H2O(1:10)的纳米线的数字化刻蚀。可以通过这种方式在纳米线的一部分上对高度掺杂的壳进行局部蚀刻，并且将直径修整为所需的尺寸(3-50nm)。
在第四步骤中，通过(例如)原子层沉积而沉积得到高κ氧化物，其由(例如)Al2O3、HfO2、ZrO2或其组合组成。
在第五步骤中，通过(例如)溅射的W来沉积金属栅极。由此最终限定了金属栅长，而栅极-漏极和栅极-源极间距分别由保护层的厚度和间隔层的厚度来限定。
然后，在第六步骤中，通过金属化从而分别接触栅极并限定晶体管顶部欧姆接触，以及形成底部电极，从而完成了晶体管工艺。
本文所给出的实施方案的特殊优点在于栅长的控制，可以由第一保护层的厚度来限定栅长。然而，可以理解的是，如果间隔层的厚度改变而保护层的厚度保持恒定，则将获得相同的效果。类似地，在晶体管当中，这两个层的厚度均可以变化。
还应理解的是，所提供的实施方案中描述的保护层和间隔层实际上可以由多层结构组成，该多层结构组合在一起将充当所描述的层。
本发明的一个特殊优点在于，可以在栅极限定之前对欧姆接触进行退火。当使用Ni作为接触金属时，可以利用这种特殊优点从而在接触区中形成Ni合金，这可进一步用于降低接入电阻。
除非另外定义，否则这里使用的所有术语(包括技术和科学术语)具有与本发明所属领域的普通技术人员通常理解的相同的含义。将进一步理解的是，除非在本文中有明确定义，否则本文中使用的术语应该被解释为具有与其在本说明书的上下文中和相关领域的含义相一致的含义，并且将不被理解为理想化或过度形式化的意义。
以上描述了本发明的原理、优选实施方案以及操作模式。然而，本发明应被认为是说明性的而不是限制性的，并且不局限于上面讨论的特定实施方案。除了那些明确描述的组合之外，本发明的各种实施方案的不同特征能够以其它组合方式进行组合。因此，应该理解的是，本领域技术人员可以在这些实施方案中进行变化，而不偏离由所附权利要求限定的本发明的范围。

Claims (14)

1.一种在半导体衬底上制造垂直纳米线MOSFET的方法，所述半导体衬底具有至少一根纳米线，所述方法包括：
围绕纳米线的底部沉积保护层，通过控制每根纳米线周围的保护层来限定栅极-漏极间距，以及通过控制所述保护层的厚度来控制栅长；
通过金属沉积形成顶部金属接触，所述顶部金属接触为漏极金属接触，各向异性地蚀刻顶部金属接触，使得平面层被去除并且仅保留纳米线的侧壁上的金属；
移除所述保护层；
沉积间隔层，其中所述间隔层的厚度小于所述保护层的厚度，通过所述间隔层的厚度来限定栅极-源极间距；
沉积高κ氧化物；
沉积金属栅极，从而限定最终栅极长度；
分别接触所述栅极和所述顶部金属接触；以及
形成底部电极，所述底部电极为源极。
2.根据权利要求1所述的方法，进一步包括：
通过使用顶部金属接触和所述间隔层作为掩模进行蚀刻在所述纳米线中形成凹陷区，其中在沉积所述高κ氧化物的操作之前形成所述凹陷区。
3.根据权利要求1所述的方法，其中形成所述顶部金属接触包括溅射20nm的W、原子层沉积(ALD)5nm的TiN、或沉积Ni。
4.根据权利要求3所述的方法，其中形成所述顶部金属接触的操作进一步包括：
各向异性蚀刻沉积的金属以移除所沉积的金属的平面部分。
5.根据权利要求1所述的方法，其中所述保护层包括：氢倍半硅氧烷(HSQ)、SiNx、SiO2、BCB或光刻胶。
6.根据权利要求1所述的方法，其中所述保护层为氢倍半硅氧烷(HSQ)，并且所述移除保护层的操作为使用HF蚀刻所述保护层。
7.根据权利要求1所述的方法，其中使用原子层沉积来沉积所述高κ氧化物。
8.根据权利要求1所述的方法，其中所述高κ氧化物由Al2O3、HfO2、ZrO2或它们的组合组成。
9.根据权利要求1所述的方法，其中所述半导体衬底由Si或III-V族复合材料制成。
10.根据权利要求1所述的方法，其中所述纳米线为III-V或IV族纳米线。
11.一种采用权利要求1至10中任一项所述的方法制造的垂直纳米线MOSFET。
12.根据权利要求11所述的垂直纳米线MOSFET在数字化应用中的用途，其中将一根或多根纳米线连接成组以形成电路。
13.根据权利要求11所述的垂直纳米线MOSFET在RF波应用或毫米波应用中的用途，其中将一根或多根纳米线连接成组以形成电路。
14.根据权利要求11所述的垂直纳米线MOSFET在混合模式应用或存储器应用中的用途，其中将一根或多根纳米线连接成组以形成电路。
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CN102576726A (zh) * 2009-09-30 2012-07-11 国立大学法人北海道大学 隧道场效应晶体管及其制造方法
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