CN114430862A - 制造非对称竖直纳米线mosfet的方法和非对称竖直纳米线mosfet - Google Patents

制造非对称竖直纳米线mosfet的方法和非对称竖直纳米线mosfet Download PDF

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CN114430862A
CN114430862A CN202080064240.1A CN202080064240A CN114430862A CN 114430862 A CN114430862 A CN 114430862A CN 202080064240 A CN202080064240 A CN 202080064240A CN 114430862 A CN114430862 A CN 114430862A
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vertical nanowire
bottom portion
outer shell
vertical
nanowire
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拉尔斯-埃里克·维纳森
奥利-佩卡·基尔皮
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C2amps AB
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  • Thin Film Transistor (AREA)

Abstract

提供了一种用于在包括至少一条竖直纳米线(125)的半导体衬底(110)上制造非对称竖直纳米线MOSFET(100)的方法，该至少一条竖直纳米线包括核心部分(120)和外壳部分(130)，该外壳部分包围核心部分(120)。该方法包括：在半导体衬底(110)上沉积保护层(140)；在竖直纳米线(125)的未被保护层(140)遮盖的剩余部分(120t)周围形成顶部接触件(150)；去除保护层(140)；在半导体衬底(110)上沉积间隔层(160)；去除竖直纳米线(125)的底部分(125b)的中间部分(125i)的外壳部分；修整竖直纳米线(125)的底部分(125b)的上部部分(125u)的外壳部分；在间隔层(160)上沉积金属栅极(170)，并且形成下源极漏极部分和上源极漏极部分。

Description

制造非对称竖直纳米线MOSFET的方法和非对称竖直纳米线 MOSFET
技术领域
本发明构思涉及一种用于在半导体衬底上制造非对称竖直纳米线金属氧化物半导体场效应晶体管(MOSFET)的方法和一种非对称竖直纳米线MOSFET。
背景技术
在过去的几年中，已经开发了允许全环绕栅极几何结构的竖直纳米线MOSFET器件。特别地，由集成在Si衬底上的III-V族材料形成的MOSFET可以提供降低电源电压并因此降低功耗的可能性。然而，与现有技术水平的侧向MOSFET相比，竖直纳米线MOSFET已经表现出相当低的性能。与侧向MOSFET相比，竖直纳米线MOSFET的较低性能可能与其较长的栅极长度、较高的接入电阻和较高的电容有关。
发明内容
本发明构思的目的是至少部分地克服现有技术的一个或多个上述局限性。
根据本发明构思的一方面，提供了一种用于在包括至少一条竖直纳米线的半导体衬底上制造非对称竖直纳米线MOSFET的方法，其中，该至少一条竖直纳米线包括核心部分和外壳部分，该外壳部分沿着该纳米线的高度包围该核心部分，该方法包括：在半导体衬底上和竖直纳米线的底部分周围沉积保护层；在竖直纳米线的未被保护层遮盖的剩余部分周围形成顶部接触件；通过刻蚀去除保护层；在半导体衬底上和竖直纳米线的底部分的下部部分周围沉积间隔层，其中，间隔层的厚度小于保护层的厚度，并且其中，竖直纳米线的底部分的未被间隔层遮盖的剩余部分包括中间部分和上部部分；去除竖直纳米线的底部分的中间部分的外壳部分，从而在竖直纳米线的底部分的中间部分处暴露竖直纳米线的核心部分；修整竖直纳米线的底部分的上部部分的外壳部分，从而减小竖直纳米线的底部分的上部部分的外壳部分的厚度，或者去除竖直纳米线的底部分的上部部分的外壳部分；在隔离层上和纳米线的底部分的中间部分周围沉积金属栅极；以及形成下源极漏极部分和上源极漏极部分。
包括核心部分和外壳部分的至少一条竖直纳米线允许例如两种不同材料的组合。在半导体衬底上和竖直纳米线的底部分周围沉积保护层的步骤允许在形成顶部接触件的步骤期间保护竖直纳米线的底部分。因此，在竖直纳米线的剩余部分(即，竖直纳米线的未被保护层遮盖的顶部分)上形成顶部接触件。此外，保护层的厚度可以例如限定顶部接触件与下源极漏极部分之间的间距。通过刻蚀去除保护层的步骤允许接近竖直纳米线的底部分，同时纳米线的顶部分被顶部接触件遮盖。在半导体衬底上和竖直纳米线的底部分的下部部分周围沉积间隔层的步骤允许限定栅极与下源极漏极部分之间的间距。例如，间隔层的厚度可以影响栅极与下源极漏极部分之间的间距。
去除竖直纳米线的底部分的中间部分的外壳部分的步骤和修整竖直纳米线的底部分的上部部分的外壳部分的步骤允许形成紧邻金属栅极布置的竖直纳米线的非对称部分，即竖直纳米线的底部分的下部部分和竖直纳米线的底部分的上部部分变得非对称。例如，竖直纳米线的底部分的上部部分的厚度变得小于竖直纳米线的底部分的下部部分的厚度。非对称竖直纳米线MOSFET又允许设计栅极源极电容(Cgs)和栅极漏极电容(Cgd)，使得可以实现非对称的Cgs和Cgd。同时，在金属栅极的直接邻近区域上，至少在金属栅极的一侧上存在外壳提供了降低接入电阻的手段，这对于数字和射频(RF)应用是至关重要的。非对称的Cgs和Cgd又可以提高所获得的非对称竖直纳米线MOSFET的功率增益。
竖直纳米线MOSFET在此意味着包括半导体结构并且进一步包括栅极结构的MOSFET，该半导体结构包括下源极漏极部分和上源极漏极部分以及沟道部分，该沟道部分定位在下源极漏极部分与上源极漏极部分之间并且在它们之间竖直延伸，该栅极结构沿着沟道部分竖直地延伸。栅极结构可以至少部分地包围沟道部分。特别地，栅极结构可以环绕沟道部分，换句话说，形成全环绕栅极(GAA)结构。下源极漏极部分和上源极漏极部分以及沟道部分可以与共同的竖直平面相交。沟道部分适于(在器件的使用中)在源极漏极之间传导电荷载流子的竖直流动。
如本文中所使用的，术语“竖直的”表示平行于衬底的法线方向(即，主延伸平面或其主/上表面)的方向或取向(例如，表面、尺寸或其它特征的方向或取向)。术语“水平的”同时表示平行于衬底(即其主延伸平面或主表面)的方向或取向，或者等同地横向于竖直方向。
例如,“竖直纳米线”在此意味着纳米线高度平行于半导体衬底的法线延伸。
“在……上”在此意味着在上方并且与之接触。例如,“在半导体衬底上沉积保护层”在此意味着保护层沉积在半导体衬底上方并且与其接触。
同时，比如“底部”、“顶部”、“下部”和“中间”、“上部”等术语是指沿竖直方向观察的相对位置，并且因此并不意味着衬底或器件的绝对取向。例如，术语“纳米线的底部分”和“纳米线的顶部分”是指沿着竖直方向观察的相对位置，即“底部分”比“顶部分”更靠近半导体衬底布置。此外，术语“竖直纳米线的底部分的下部”部分、“竖直纳米线的底部分的中间”部分和“竖直纳米线的底部分的上部”部分是指沿着竖直方向观察的相对位置，即“下部部分”比“中间部分”和“上部部分”更靠近半导体衬底布置，并且“中间部分”比“上部部分”更靠近半导体衬底布置。术语“下源极漏极部分”和“上源极漏极部分”是指沿着竖直方向观察的源极漏极部分的相对位置。
“非对称竖直纳米线MOSFET”在此意味着金属栅极附近的纳米线几何结构非对称，即竖直纳米线的底部分的下部部分和上部部分非对称。
修整该竖直纳米线的底部分的上部部分的外壳部分的步骤可以包括去除该竖直纳米线的底部分的上部部分的外壳部分，从而在该竖直纳米线的底部分的上部部分处暴露竖直纳米线的核心部分。因此，可以实现非对称竖直纳米线MOSFET，即，竖直纳米线的底部分的下部部分可以具有外壳部分，而竖直纳米线的底部分的上部部分可以没有外壳部分或只有很少的外壳部分。
可以通过刻蚀来执行去除竖直纳米线的底部分的中间部分的外壳部分的步骤和修整竖直纳米线的底部分的上部部分的外壳部分的步骤。刻蚀可以有助于去除竖直纳米线的底部分的中间部分的外壳部分、以及修整竖直纳米线的底部分的上部部分的外壳部分。例如，可以执行刻蚀，使得可以控制刻蚀速率。这又可以允许在去除竖直纳米线的底部分的中间部分的外壳部分的步骤和修整竖直纳米线的底部分的上部部分的外壳部分的步骤期间改进控制。
可以同时执行去除竖直纳米线的底部分的中间部分的外壳部分的步骤和修整竖直纳米线的底部分的上部部分的外壳部分的步骤。因此，可以有助于制造非对称竖直纳米线MOSFET。例如，可以减少制造非对称竖直纳米线MOSFET的处理步骤的数量。“同时”在此意味着去除竖直纳米线的底部分的中间部分的外壳部分的步骤和修整竖直纳米线的底部分的上部部分的外壳部分的步骤在相同的工艺中同时完成。
该方法可以进一步包括在去除竖直纳米线的底部分的中间部分的外壳部分的步骤之前，掩模竖直纳米线的底部分的上部部分。因此，在去除竖直纳米线的底部分的中间部分的外壳部分的步骤期间，可以保护竖直纳米线的底部分的上部部分。这又可以对非对称竖直纳米线MOSFET的制造提供改进的控制。
在修整竖直纳米线的底部分的上部部分的外壳部分的步骤之前，可以执行在间隔层上和竖直纳米线的底部分的中间部分周围沉积金属栅极的步骤。因此，在修整竖直纳米线的底部分的上部部分的外壳部分的步骤期间，金属栅极可以保护竖直纳米线的底部分的中间部分。换句话说，在修整竖直纳米线的底部分的上部部分的外壳部分的步骤期间，金属栅极可以掩模竖直纳米线的底部分的中间部分。
该方法可以进一步包括在修整竖直纳米线的底部分的上部部分的外壳部分的步骤之前，使竖直纳米线的底部分的上部部分外露。因此，在修整竖直纳米线的底部分的上部部分的外壳部分的步骤之前，外露可以允许接近竖直纳米线的底部分的上部部分。
竖直纳米线的核心部分可以由InAs、InGaAs或其组合形成。竖直纳米线的核心部分可以由二元材料、三元材料或其组合形成。二元材料和三元材料可以由任何III-V半导体材料形成。竖直纳米线的核心部分可以掺杂有n型掺杂剂或p型掺杂剂。
竖直纳米线的外壳部分可以由InGaAs形成，n型掺杂剂剂量至少为1.1016原子/cm3。竖直纳米线的外壳部分可以由二元材料、三元材料或其组合形成。二元材料和三元材料可以由任何III-V半导体材料形成。竖直纳米线的外壳部分可以掺杂有n型掺杂剂或p型掺杂剂。掺杂剂的剂量可以在1.1016原子/cm3至1.1020原子/cm3的范围内。
根据本发明构思的另一方面，提供了一种非对称竖直纳米线MOSFET，该非对称竖直纳米线MOSFET包括：至少一条竖直纳米线，该至少一条竖直纳米线布置在半导体衬底上，其中，该至少一条竖直纳米线包括核心部分和外壳部分，该外壳部分沿着竖直纳米线的高度包围核心部分；第一间隔层，该第一间隔层布置在半导体衬底上并且围绕竖直纳米线的底部分的下部部分；金属栅极，该金属栅极布置在第一间隔层上并且围绕竖直纳米线的底部分的中间部分，其中，竖直纳米线的底部分的中间部分包括外壳部分中的贯穿凹部，该凹部包围核心部分；第二间隔层，该第二间隔层布置在金属栅极上并且至少围绕竖直纳米线的底部分的上部部分，其中，竖直纳米线的底部分的上部部分的外壳部分与竖直纳米线的底部分的下部部分相比具有减小的厚度；顶部接触件，该顶部接触件布置在竖直纳米线的顶部分周围，其中，竖直纳米线的顶部分的外壳部分与竖直纳米线的底部分的下部部分相比具有对应的厚度；以及下源极漏极部分和上源极漏极部分。
此方面总体上可以呈现与前一方面相同或对应的优点。
竖直纳米线的底部分的中间部分的外壳部分中的“贯穿凹部”在此意味着至少在竖直纳米线的底部分的中间部分的一部分处不存在外壳部分或只有很少的外壳部分。换句话说，竖直纳米线的底部分的中间部分的至少一部分没有任何外壳部分。
“顶部接触件”在此意味着布置在竖直纳米线的顶部分的接触部分。顶部接触件可以是上源极漏极部分的一部分。顶部接触件可以连接到上源极漏极部分。
非对称竖直纳米线MOSFET可以包括第一竖直纳米线和第二竖直纳米线，该第一竖直纳米线具有第一直径，该第二竖直纳米线具有不同于该第一竖直纳米线的第二直径。因此，非对称竖直纳米线MOSFET可以在不同的阈值电压下工作。
第一竖直纳米线可以具有第一核心部分和第一外壳部分，并且第二竖直纳米线可以具有第二核心部分和第二外壳部分。第一竖直纳米线和第二竖直纳米线可以形成为使得第一核心部分可以具有与第二核心部分相同的直径并且第一外壳部分可以具有与第二外壳部分不同的直径。第一竖直纳米线和第二竖直纳米线可以形成为使得第一核心部分可以具有与第二核心部分不同的直径并且第一外壳部分可以具有与第二外壳部分相同的直径。第一竖直纳米线和第二竖直纳米线可以形成为使得第一核心部分可以具有与第二核心部分不同的直径并且第一外壳部分可以具有与第二外壳部分不同的直径。
非对称竖直纳米线MOSFET可以进一步包括栅极氧化物层，该栅极氧化物层布置在竖直纳米线的底部分的中间部分的核心部分与金属栅极之间。栅极氧化物可以有助于调制非对称竖直纳米线MOSFET沟道的电导。
附图说明
通过参照附图进行的以下说明性且非限制性的详细描述，将更好地理解本发明构思的以上及附加的目的、特征和优点。在附图中，除非另有说明，否则相同的附图标记将用于相同的元件。
图1至图10示意性地图示了用于在半导体衬底上制造非对称竖直纳米线MOSFET的方法的各个步骤。
具体实施方式
现在将结合图1至图10披露在半导体衬底上制造非对称竖直纳米线MOSFET的各种方法。
图1示出了包括至少一条竖直纳米线125的半导体衬底110的截面视图。在图1中，Y轴表示与相对于半导体衬底110的上表面的法线方向相对应的竖直方向。X轴表示沿着半导体衬底100的第一水平方向，并且Z轴表示沿着半导体衬底100的第二水平方向，该第二水平方向垂直于第一方向X。应当注意，在附图中，所示元件的相对尺寸(比如元件的高度、宽度或厚度)仅仅是示意性的，并且为了说明清楚的目的，这些尺寸可以不同于物理结构。
半导体衬底110可以是任何常规衬底110，比如适用于MOSFET处理的衬底。衬底110例如可以是半导体衬底，比如Si衬底、Ge衬底或硅锗(SiGe)衬底。其他示例包括绝缘体上硅(SOI)衬底、GeOI衬底或SiGeOI衬底。衬底可以包括层(比如在Si衬底上形成的InAs层)的堆叠体。可以在Si衬底上外延生长InAs层。可以以本身在本领域中公知的方式外延生长InAs层。可以使用任何合适的常规技术(比如化学气相沉积(CVD)、金属有机CVD(MOCVD)、分子束外延(MBE)或气相外延(VPE))来形成InAs层。InAs层的典型厚度可以在100nm至500nm的范围内。
在图1和随后的图中，示出了一条竖直纳米线125。然而，应当注意，半导体衬底110可以在所图示区域之外包括任意数量的另外的竖直纳米线125。
图1所示的竖直纳米线125平行于Y方向延伸。举例来说，竖直纳米线125的典型高度可以在300nm至600nm的范围内。也可以考虑50nm至300nm范围内的更短的高度。竖直纳米线125的直径(即沿着X轴或Z轴的直径)可以在15nm至100nm的范围内。也可以考虑5nm至15nm的直径。可以以本身在本领域中公知的方式(例如通过刻蚀在半导体衬底110上形成的外延半导体层或层堆叠体)形成竖直纳米线125。在InAs层形成在Si衬底上的情况下，可以通过刻蚀在Si衬底上形成的InAs层来形成竖直纳米线125。可以以本身在本领域中公知的方式在半导体衬底110上外延生长竖直纳米线125。例如，可以使用比如Au纳米粒子的催化剂纳米粒子来生长竖直纳米线125。可以使用任何合适的常规技术(比如CVD、MOCVD、MBE或VPE)形成竖直纳米线125。
图1示出了竖直纳米线125包括核心部分120和外壳部分130，该外壳部分沿着该竖直纳米线的高度包围核心部分120。竖直纳米线125的核心部分120可以由InAs、InGaAs或其组合形成。竖直纳米线125的核心部分120可以包括沿着竖直方向(即沿着竖直纳米线125的高度)的层的堆叠体。换句话说，竖直纳米线125的核心部分120可以包括轴向异质结构。竖直纳米线125的核心部分120可以包括垂直于竖直方向(即沿着该竖直纳米线125的宽度)的层的堆叠体。换句话说，竖直纳米线125的核心部分120可以包括径向异质结构。层的堆叠体的任何层可以由二元材料或三元材料形成，该二元材料或三元材料由III-V半导体材料形成。竖直纳米线125的核心部分120可以掺杂有n型掺杂剂或p型掺杂剂。竖直纳米线125的核心部分120的直径(即沿着X轴或Z轴的直径)可以在5nm至80nm的范围内。
竖直纳米线125的外壳部分130可以由InGaAs形成。竖直纳米线125的外壳部分130可以包括层的堆叠体。层的堆叠体的任何层可以由二元材料或三元材料形成，该二元材料或三元材料由III-V半导体材料形成。竖直纳米线125的外壳部分130可以掺杂有n型掺杂剂或p型掺杂剂。在n型掺杂剂的情况下，竖直纳米线125的外壳部分130的n型掺杂剂剂量可以在1.1016至1.1020原子/cm3的范围内。竖直纳米线125的外壳部分130的n型掺杂剂剂量可以至少是1.1016原子/cm3。竖直纳米线125的外壳部分130的直径(即沿着X轴或Z轴的直径)可以在3nm至20nm的范围内。
可以以本身在本领域中公知的方式形成竖直纳米线125的核心部分120和外壳部分130。例如，在竖直纳米线125外延生长的情况下，竖直纳米线125的核心部分120和外壳部分130的生长可以通过选择控制外延生长参数(例如流量和温度)的适当前体来进行。
此外，半导体衬底110可以包括具有第一直径的第一竖直纳米线125和具有不同于第一竖直纳米线的第二直径的第二竖直纳米线125。在竖直纳米线125外延生长的情况下，第一竖直纳米线和第二竖直纳米线可以例如通过使用具有不同直径的催化剂纳米粒子来形成。
现在参考图2，该方法继续进行到在半导体衬底上和竖直纳米线125的底部分125b周围沉积保护层140。保护层140可以由一个或几个有机层或无机层(比如氢硅倍半氧烷(HSQ)、SiNx、Si02、BCB和光致抗蚀剂)形成。可以以本身在本领域中公知的方式(比如旋涂)沉积保护层140。保护层140的典型厚度可以在10nm至100nm的范围内。因此，竖直纳米线125的底部分125b的典型高度可以在10nm至100nm的范围内。
现在参考图3，该方法继续进行到在竖直纳米线125的未被保护层140遮盖的剩余部分120t周围形成顶部接触件150。图3示出了在竖直纳米线125的未被保护层140遮盖的顶部分125t上形成顶部接触件150。顶部接触件150可以由比如W、TiN和Ni等任何金属形成。顶部接触件150可以包括一层或多个层的堆叠体。可以以本身在本领域中公知的方式(比如溅射和原子层沉积(ALD))形成顶部接触件150。顶部接触件150沿着X轴或Z轴的典型厚度可以在3nm至50nm的范围内。例如，可以通过溅射20nm的W、原子层沉积(ALD)5nm的TiN或5nm的Ni的来形成顶部接触件150。
现在参考图4，该方法继续进行到去除保护层140。去除保护层140的步骤可以通过保护层140的湿法刻蚀来完成。可以使用氢氟酸(HF)来执行保护层140的湿法刻蚀。可以继续将保护层140从竖直纳米线125的底部分125b去除的步骤，直到竖直纳米线125的底部分125b暴露为止。图4示出了在从竖直纳米线125的底部分125b去除保护层140的步骤之后的竖直纳米线125。图4示出了竖直纳米线125的底部分125b被暴露。
现在参考图5，该方法继续进行到在半导体衬底110上沉积间隔层160。图5示出了间隔层160沉积在竖直纳米线125的底部分125b的下部部分120l周围。图5进一步示出了间隔层160的厚度小于保护层140的厚度。图5进一步示出了竖直纳米线125的底部分125b的未被间隔层160遮盖的剩余部分包括中间部分125i和上部部分125u。间隔层160可以由比如SiO2等无机材料或比如BCB等有机材料形成。可以以本身在本领域中公知的方式(比如等离子体增强化学气相沉积(PECVD)、CVD、旋涂或ALD)沉积间隔层160。间隔层160的典型厚度可以在5nm至150nm的范围内。
现在参考图6，该方法继续进行到去除竖直纳米线125的底部分125b的中间部分125i的外壳部分。图6示出了在去除竖直纳米线125的底部分125b的中间部分125i的外壳部分的步骤之后，已经暴露了竖直纳米线125的底部分125b的中间部分125i的核心部分。可以通过刻蚀来执行去除竖直纳米线125的底部分125b的中间部分125i的外壳部分的步骤。可以以本身在本领域中公知的方式进行刻蚀，比如使用例如盐酸(HCl)和氧气处理的循环刻蚀。刻蚀可以原位进行，或者通过在不同设备之间转移样品来进行。化学物质可以进一步被选择为相对于核心和外壳材料是选择性的或非选择性的。
在去除竖直纳米线125的底部分125b的中间部分125i的外壳部分的步骤之前，可以掩模竖直纳米线125的底部分125b的上部部分125u。可以以本身在本领域中公知的方式进行竖直纳米线125的底部分125b的上部部分125u的掩模。
现在参考图7a，该方法继续进行到修整竖直纳米线125的底部分125b的上部部分125u的外壳部分。图7a示出了竖直纳米线125的底部分125b的上部部分125u处的外壳部分的厚度已经减小。图7a示出了竖直纳米线125的底部分125b的上部部分125u处的外壳厚度小于竖直纳米线125的底部分125b的下部部分120l处的外壳厚度，即，竖直纳米线125的底部分125b的上部部分125u和下部部分120l处的外壳厚度是非对称的。在竖直纳米线125的底部分125b的上部部分125u已经被掩模的情况下，在去除竖直纳米线125的底部分125b的中间部分125i的外壳部分的步骤之前，该方法可以进一步包括在修整竖直纳米线125的底部分125b的上部部分125u的外壳部分的步骤之前，使竖直纳米线125的底部分125b的上部部分125u外露。
可以通过刻蚀来执行修整竖直纳米线125的底部分125b的上部部分125u的外壳部分的步骤。可以以类似于去除竖直纳米线125的底部分125b的中间部分125i的外壳部分的步骤的方式执行修整步骤。修整步骤可以被控制成使得可以去除竖直纳米线125的底部分125b的上部部分125u的外壳部分的期望厚度。修整步骤可以例如通过控制刻蚀时间来控制。在修整步骤之后，竖直纳米线125的底部分125b的上部部分125u的外壳部分的厚度可以减小30％-80％。在修整竖直纳米线125的底部分125b的上部部分125u的外壳部分的步骤之前，可以掩模竖直纳米线125的底部分125b的中间部分125i。可以通过利用新掩模重复上述工艺步骤来执行竖直纳米线125的底部分125b的中间部分125i的掩模，该新掩模与用于掩模竖直纳米线125的底部分125b的上部部分125u的掩模相比具有不同厚度。
现在参考图7b，修整竖直纳米线125的底部分125b的上部部分125u的外壳部分的步骤可以包括去除竖直纳米线125的底部分125b的上部部分125u的外壳部分。图7b示出了在竖直纳米线125的底部分125b的上部部分125u处已经暴露了竖直纳米线125的核心部分。换句话说，竖直纳米线125的底部分125b的上部部分125u和下部部分125l已经变得非对称。
仍然参考图7b，可以通过刻蚀来执行去除竖直纳米线125的底部分125b的中间部分125i的外壳部分的步骤和去除竖直纳米线125的底部分125b的上部部分125u的外壳部分的步骤。可以同时执行去除竖直纳米线125的底部分125b的中间部分125i的外壳部分的步骤和修整竖直纳米线125的底部分125b的上部部分125u的外壳部分的步骤。例如，可以在使用相同刻蚀剂的相同刻蚀工艺中执行去除竖直纳米线125的底部分125b的中间部分125i的外壳部分的步骤和修整竖直纳米线125的底部分125b的上部部分125u的外壳部分的步骤。
该方法可以包括在竖直纳米线125的底部分125b的中间部分125i的核心部分周围形成栅极氧化物层。栅极氧化物层可以由至少一种高k介电材料(比如HfOx)形成。可以以本身在本领域中公知的方式(比如ALD)形成栅极氧化物层。栅极氧化物层的典型厚度可以在1nm至6nm的范围内。栅极氧化物层的示例可以是Al2O3/HfO2，其典型厚度为1nm Al2O3。
现在参考图8a和图8b，该方法继续进行到在间隔层160上和竖直纳米线125的底部分125b的中间部分125i周围沉积金属栅极170，即在间隔层160上和栅极氧化物层(如果存在的话)周围沉积金属栅极170。可以以本身在本领域中公知的方式(比如溅射和ALD)沉积金属栅极170。金属栅极170可以由比如TiN和W等至少一种金属形成。金属栅极170的典型厚度可以在5nm至100nm的范围内。
参考图8a，在修整竖直纳米线125的底部分125b的上部部分125u的外壳部分的步骤之前，可以执行在间隔层160上和竖直纳米线125的底部分125b的中间部分125i周围沉积金属栅极170的步骤。换句话说，在间隔层160上并且围绕竖直纳米线125的底部分125b的中间部分125i沉积栅极氧化物层和金属栅极170的步骤之后，可以执行修整竖直纳米线125的底部分125b的上部部分125u的外壳部分的步骤。以这种方式，在修整竖直纳米线125的底部分125b的上部部分125u的外壳部分的步骤期间，竖直纳米线125的底部分125b的中间部分125i可以被金属栅极170保护。
现在参考图9a和图9b，该方法可以继续进行到在金属栅极170上和竖直纳米线125的底部分125b的至少上部部分125u周围沉积另一间隔层180(例如第二间隔层180)。可以以与间隔层160(即第一间隔层160)相似的方式沉积第二间隔层180。第二间隔层180的厚度可以在20nm至200nm的范围内。第二间隔层180可以被沉积成使得第二间隔层180的厚度可以类似于竖直纳米线125的底部分125b的上部部分125u的高度。第二间隔层180可以被沉积成使得第二间隔层180的厚度可以大于竖直纳米线125的底部分125b的上部部分125u的高度。
现在参考图10a和图10b，该方法继续进行到形成下源极漏极部分110和上源极漏极部分190。下源极漏极部分和上源极漏极部分可以分别包含在下源极漏极接触件和上源极漏极接触件中。图10a和图10b示出了上源极漏极部分190的示例，即金属上源极漏极部分190已经沉积在第二间隔层180上和竖直纳米线125的顶部分125t周围。上源极漏极部分190可以具有与竖直纳米线125的底部分125b的顶部分125t的高度相似的厚度。上源极漏极部分190可以具有与竖直纳米线125的底部分125b的顶部分125t的高度不同的厚度。可以以本身在本领域中公知的方式(比如溅射)沉积上源极漏极部分190。
在半导体衬底110包括高掺杂部分(例如在Si衬底上形成的高掺杂InAs层)的情况下，该高掺杂部分可以形成为下源极漏极部分。如图10a和图10b所示，半导体衬底110充当下源极漏极部分110。可以以本身在本领域中公知的方式形成下源极漏极部分。例如，可以通过使用例如电子束光刻对高掺杂部分进行图案化来形成下源极漏极部分。
仍然参考图10a和图10b，这些图示意性地图示了非对称竖直纳米线MOSFET 100的两个示例。图10a和图10b示出了两个非对称竖直纳米线MOSFET 100，其包括布置在半导体衬底110上的至少一条竖直纳米线125。图10a和图10b进一步示出了至少一条竖直纳米线125包括核心部分120和外壳部分130。图10a和图10b示出了外壳部分130沿着竖直纳米线125的高度包围核心部分120。图10a和图10b进一步示出了第一间隔层160，该第一间隔层布置在半导体衬底110上并且围绕竖直纳米线125的底部分125b的下部部分125l。图10a和图10b进一步示出了金属栅极170，该金属栅极布置在第一间隔层160上并且围绕竖直纳米线125的底部分125b的中间部分125i。图10a和图10b示出了竖直纳米线125的底部分125b的中间部分125i包括外壳部分中的贯穿凹部，使得该凹部包围核心部分120。
图10a和图10b示出了第二间隔层180布置在金属栅极170上并且至少围绕竖直纳米线125的底部分125b的上部部分125u。图10a和图10b进一步示出了竖直纳米线125的底部分125b的上部部分125u的外壳部分与竖直纳米线125的底部分125b的下部部分125l相比具有减小的厚度。图10a和图10b进一步示出了顶部接触件150，该顶部接触件围绕竖直纳米线125的顶部分125t布置。图10a和图10b示出了与竖直纳米线125的底部分125b的下部部分125l相比，竖直纳米线125的顶部分125t的外壳部分具有对应的厚度。图10a和图10b进一步示出了下源极漏极部分110和上源极漏极部分190。图10a和图10b中呈现的非对称竖直纳米线MOSFET 100展示了在栅极金属170附近具有非对称外壳结构的晶体管。非对称外壳结构在金属栅极的一侧提供了由外壳部分130的存在所提供的低接入电阻。非对称外壳结构在金属栅极的另一侧提供了由外壳部分130和金属栅极170的分离所提供的低电容。这两种特性的结合为高频晶体管的设计以及包括其增益特性提供了优势。
在上文中，已经主要参考有限数量的示例描述了本发明构思。然而，如本领域技术人员容易理解的，在由所附权利要求限定的本发明构思的范围内，除以上披露的示例之外的其他示例同样是可能的。本领域技术人员认识到，本发明决不限于上述优选实施例。相反地，在所附权利要求的范围内，许多修改和变化是可能的。
例如，在去除竖直纳米线的底部分的中间部分的外壳部分之后，可以去除竖直纳米线的底部分的中间部分的核心部分的一部分。再如，在去除竖直纳米线的底部分的上部部分的外壳部分之后，可以去除竖直纳米线的底部分的上部部分的核心部分的一部分。另外，所披露实施例的变化是技术人员在实践所要求保护的发明时通过学习附图、披露内容、以及所附权利要求可以理解并实现的。

Claims (12)

1.一种用于在包括至少一条竖直纳米线(125)的半导体衬底(110)上制造非对称竖直纳米线MOSFET(100)的方法，其中，该至少一条竖直纳米线(125)包括核心部分(120)和外壳部分(130)，该外壳部分沿着该竖直纳米线(125)的高度包围该核心部分(120)，该方法包括：
在该半导体衬底(110)上和该竖直纳米线(125)的底部分(125b)周围沉积保护层(140)，
在该竖直纳米线(125)的未被该保护层(140)遮盖的剩余部分(125t)周围形成顶部接触件(150)，
通过刻蚀去除该保护层(140)，
在该半导体衬底(110)上和该竖直纳米线(125)的底部分(125b)的下部部分(125l)周围沉积间隔层(160)，其中，该间隔层(160)的厚度小于该保护层(140)的厚度，并且其中，该竖直纳米线(125)的底部分(125b)的未被该间隔层(160)遮盖的剩余部分包括中间部分(125i)和上部部分(125u)，
去除该竖直纳米线(125)的底部分(125b)的中间部分(125i)的外壳部分，从而在该竖直纳米线(125)的底部分(125b)的中间部分(125i)处暴露该竖直纳米线(125)的核心部分，
修整该竖直纳米线(125)的底部分(125b)的上部部分(125u)的外壳部分，从而减小该竖直纳米线(125)的底部分(125b)的上部部分(125u)的外壳部分的厚度，或者去除该竖直纳米线(125)的底部分(125b)的上部部分(125u)的外壳部分，
在该间隔层(160)上和该竖直纳米线(125)的底部分(125b)的中间部分(125i)周围沉积金属栅极(170)，以及
形成下源极漏极部分和上源极漏极部分(110，190)。
2.根据权利要求1所述的方法，其中，修整该竖直纳米线(125)的底部分(125b)的上部部分(125u)的外壳部分的步骤包括去除该竖直纳米线(125)的底部分(125b)的上部部分(125u)的外壳部分，从而在该竖直纳米线(125)的底部分(150b)的上部部分(125u)处暴露该竖直纳米线(125)的核心部分。
3.根据权利要求1或2所述的方法，其中，通过刻蚀来执行去除该竖直纳米线(125)的底部分(125b)的中间部分(125i)的外壳部分的步骤和修整该竖直纳米线(125)的底部分(125b)的上部部分(125u)的外壳部分的步骤。
4.根据权利要求1至3中任一项所述的方法，其中，同时执行去除该竖直纳米线(125)的底部分(125b)的中间部分(125i)的外壳部分的步骤和修整该竖直纳米线(125)的底部分(125b)的上部部分(125u)的外壳部分的步骤。
5.根据权利要求1所述的方法，进一步包括：
在去除该竖直纳米线(125)的底部分(120b)的中间部分(125i)的外壳部分的步骤之前，掩模该竖直纳米线(125)的底部分(120b)的上部部分(125u)。
6.根据权利要求5所述的方法，其中，在修整该竖直纳米线(125)的底部分(125b)的上部部分(125u)的外壳部分的步骤之前，执行在该间隔层(160)上和该竖直纳米线(125)的底部分(125b)的中间部分(125i)周围沉积该金属栅极(170)的步骤。
7.根据权利要求6所述的方法，进一步包括：
在修整该竖直纳米线(125)的底部分(125b)的上部部分(125u)的外壳部分的步骤之前，使该竖直纳米线(125)的底部分(125b)的上部部分(125u)外露。
8.根据权利要求1至7中任一项所述的方法，其中，该竖直纳米线(125)的核心部分(120)由InAs、InGaAs或其组合形成。
9.根据权利要求1至8中任一项所述的方法，其中，该竖直纳米线(125)的外壳部分(130)由InGaAs形成，n型掺杂剂剂量至少为1.1016原子/cm3。
10.一种非对称竖直纳米线MOSFET(100)，包括：
至少一条竖直纳米线(125)，该至少一条竖直纳米线布置在半导体衬底(110)上，其中，该至少一条竖直纳米线(125)包括核心部分(120)和外壳部分(130)，该外壳部分沿着该竖直纳米线(125)的高度包围该核心部分(120)，
第一间隔层(160)，该第一间隔层布置在该半导体衬底(110)上并且围绕该竖直纳米线(125)的底部分(125b)的下部部分(125l)，
金属栅极(170)，该金属栅极布置在该第一间隔层(160)上并且围绕该竖直纳米线(125)的底部分(125b)的中间部分(125i)，其中，该竖直纳米线(125)的底部分(125b)的中间部分(125i)包括该外壳部分中的贯穿凹部，该凹部包围该核心部分(120)，
第二间隔层(180)，该第二间隔层布置在该金属栅极(170)上并且至少围绕该竖直纳米线(125)的底部分(125b)的上部部分(125u)，其中，该竖直纳米线(125)的底部分(125b)的上部部分(125u)处的该外壳部分与该竖直纳米线(125)的底部分(125b)的下部部分(125l)相比具有减小的厚度，
顶部接触件(150)，该顶部接触件布置在该竖直纳米线(125)的顶部分(125t)周围，其中，该竖直纳米线(125)的顶部分(125t)的外壳部分与该竖直纳米线(125)的底部分(125b)的下部部分(125l)相比具有对应的厚度，以及
下源极漏极部分和上源极漏极部分(110，190)。
11.根据权利要求10所述的非对称竖直纳米线MOSFET(100)，其中，该非对称竖直纳米线MOSFET(100)包括第一竖直纳米线(125)和第二竖直纳米线(125)，该第一竖直纳米线具有第一直径，该第二竖直纳米线具有不同于该第一竖直纳米线(125)的第二直径。
12.根据权利要求10或11所述的非对称竖直纳米线MOSFET(100)，进一步包括栅极氧化物层，该栅极氧化物层布置在该竖直纳米线(125)的底部分(125b)的中间部分(125i)的核心部分与该金属栅极(170)之间。
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