CN108206216B - Semiconductor device, manufacturing method thereof and electronic device - Google Patents

Semiconductor device, manufacturing method thereof and electronic device Download PDF

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CN108206216B
CN108206216B CN201611178075.4A CN201611178075A CN108206216B CN 108206216 B CN108206216 B CN 108206216B CN 201611178075 A CN201611178075 A CN 201611178075A CN 108206216 B CN108206216 B CN 108206216B
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layer
hard mask
mask layer
forming
grid
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CN108206216A (en
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邱慈云
陈玉华
江宇雷
蔡建祥
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET

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  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention provides a semiconductor device, a manufacturing method thereof and an electronic device, and relates to the technical field of semiconductors. The method comprises the following steps: providing a semiconductor substrate, forming a grid on the semiconductor substrate, and forming a hard mask layer on the grid; forming a gap wall to cover the top surface of the hard mask layer and the side walls of the hard mask layer and the grid; and forming a metal silicide layer on the surface of the gap wall. The manufacturing method of the invention has the following advantages: 1) the formed metal silicide layer has better quality because a new clearance wall profile is provided, which is beneficial to the formation of the metal silicide layer; 2) since a silicide barrier layer (including silicide barrier layer deposition and etching processes) is not required, the production cost and the production cycle time are reduced; 3) because a thicker dielectric layer is arranged between the formed metal silicide layer and the grid electrode, the crosstalk between the metal silicide layer and the grid electrode can be reduced, and the performance of a device is improved.

Description

Semiconductor device, manufacturing method thereof and electronic device
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof and an electronic device.
Background
The Mature Technology Enhancement (MTE) process can achieve twice the gate density compared to the common logic device fabrication technology at the same process node, and it uses a special metal layer M0 as a connection structure to reduce the device size. The metal layer M0 is deposited after the spacer etching, and the self-aligned silicide forming process is used to react the polysilicon layer deposited on the top surface of the hard mask layer and the surface of the spacer into a metal silicide layer as the metal layer M0, when the self-aligned silicide forming process is performed, a patterned silicide blocking layer (SAB) is also required to be formed to cover the region where the metal silicide is not required to be formed, so the process is complicated and complicated, the cost is high, the period is long, and the quality of the metal silicide in the partial region on the side wall of the spacer is poor due to the influence of the spacer profile, and the performance of the device is further influenced.
Therefore, it is necessary to provide a new method for manufacturing a semiconductor device to solve the above technical problems.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In view of the deficiencies of the prior art, a first embodiment of the present invention provides a method for manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate, forming a grid on the semiconductor substrate, and forming a hard mask layer on the grid;
forming a gap wall to cover the top surface of the hard mask layer and the side walls of the hard mask layer and the grid;
and forming a metal silicide layer on the surface of the gap wall.
Further, the step of forming the spacer includes the processes of:
depositing a spacer material layer to cover the hard mask layer, the gate and the semiconductor substrate;
forming a patterned photoresist layer to cover the gap wall material layer above the hard mask layer and on the two sides of the hard mask layer;
and etching and removing part of the gap wall material layer by taking the patterned photoresist layer as a mask so as to form the gap wall.
Further, the step of forming the metal silicide layer includes the processes of:
forming a polysilicon layer on the surface of the gap wall;
depositing a metal layer to cover the polysilicon layer;
and carrying out thermal annealing to enable the metal layer to react with the part in contact with the polycrystalline silicon layer to form the metal silicide layer.
Further, the step of forming the gate electrode includes the processes of:
sequentially depositing a grid layer and a hard mask layer on the semiconductor substrate;
forming a patterned photoresist layer on the hard mask layer;
etching the hard mask layer by taking the patterned photoresist layer as a mask;
and etching the gate layer by taking the hard mask layer as a mask to form the gate.
Further, the hard mask layer includes an oxide layer and a nitride layer stacked from bottom to top.
Further, the material of the gate comprises polysilicon.
An embodiment of the present invention provides a semiconductor device prepared by the foregoing method, including:
the semiconductor device comprises a semiconductor substrate, a grid electrode and a hard mask layer, wherein the grid electrode is formed on the semiconductor substrate;
forming gap walls on the top surface of the hard mask layer and the side walls of the hard mask layer and the grid;
a metal silicide layer is formed on the surface of the spacer.
Further, the hard mask layer includes an oxide layer and a nitride layer stacked from bottom to top.
Further, the gap wall extends to the surface of the semiconductor substrate outside the grid electrode.
The third embodiment of the invention provides an electronic device, which comprises the semiconductor device.
The manufacturing method of the invention forms the spacer covering the hard mask layer and the top surface and the side wall of the grid to replace the existing spacer only formed on the side wall of the grid, and then forms the metal silicide layer M0 on the surface of the spacer, and the manufacturing method of the invention does not need to use a silicide barrier layer, therefore, the manufacturing method of the invention has the following advantages:
1) the formed metal silicide layer has better quality because a new clearance wall profile is provided, which is beneficial to the formation of the metal silicide layer;
2) since a silicide barrier layer (including silicide barrier layer deposition and etching processes) is not required, the production cost and the production cycle time are reduced;
3) because a thicker dielectric layer is arranged between the formed metal silicide layer and the grid electrode, the crosstalk between the metal silicide layer and the grid electrode can be reduced, and the performance of a device is improved.
The semiconductor device of the present invention has the same advantages as described above because of the above manufacturing method. The electronic device of the present invention also has the above advantages because of the use of the above semiconductor device.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
fig. 1A to 1E are schematic structural views of a device obtained in the related steps of manufacturing a semiconductor device by a conventional MTE process;
fig. 2A to 2E are schematic structural views of a device obtained at the relevant steps of the method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 3 shows a process flow diagram of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Fig. 4 shows a schematic diagram of an electronic device in an embodiment of the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
Next, steps related to the conventional MTE process for manufacturing a semiconductor device will be briefly described with reference to fig. 1A to 1E, wherein fig. 1A to 1E show schematic structural diagrams of devices obtained by the steps related to the conventional MTE process for manufacturing a semiconductor device.
First, as shown in fig. 1A, a semiconductor substrate is provided, a polysilicon gate 101 is formed on the semiconductor substrate, and a hard mask layer including a silicon oxide layer 102 and a silicon nitride layer 103 stacked from bottom to top is formed on the polysilicon gate 101.
Next, as shown in fig. 1B, a spacer material layer 104a is deposited to cover the semiconductor substrate and the silicon nitride 103, wherein the material of the spacer material layer 104a includes an oxide.
Next, as shown in fig. 1C, a portion of the spacer material layer on the surface of the silicon nitride layer 103 and on the surface of the semiconductor substrate is etched to form a spacer 104, where the spacer 104 is located on the gate and the sidewalls of the stacked silicon oxide layer 102 and silicon nitride layer 103.
Next, as shown in fig. 1D, a polysilicon layer 105 is deposited to cover the semiconductor substrate, and a portion of the polysilicon layer 105 is removed by photolithography and etching processes, and a portion of the polysilicon layer 105 on the surface of the silicon nitride 103, the surface of the spacer 104, and a portion of the surface of the semiconductor substrate remains.
Next, a silicide blocking layer (SAB) is deposited and patterned to expose the polysilicon layer 105, covering areas where a metal silicidation process is not required.
Subsequently, as shown in fig. 1E, a salicide formation process is performed, for example, a metal layer, which may include cobalt (cobalt), is first deposited overlying the polysilicon layer 105. An annealing process is then performed to cause the metal layer to silicidize with the underlying polysilicon layer, thereby forming a metal silicide layer 106. An etchant is then used that attacks the metal layer but does not attack the regions of the metal silicide layer to remove the unreacted metal layer.
Since the polysilicon layer 105 deposited on the top surface of the silicon nitride layer 103 and the surface of the spacer is reacted into the metal silicide layer 106 as the metal layer M0, and in the self-aligned silicide formation process, a patterned silicide blocking layer (SAB) is also required to be formed to cover the region where the metal silicide is not required to be formed, the process is complicated, the production cost is high, the period is long, and the quality of the metal silicide in the partial region on the sidewall of the spacer is poor due to the influence of the spacer profile, thereby affecting the performance of the device.
Example one
In order to solve the above technical problem, the present invention provides a method for manufacturing a semiconductor device, as shown in fig. 3, the method mainly includes the following steps:
step S1: providing a semiconductor substrate, forming a grid on the semiconductor substrate, and forming a hard mask layer on the grid;
step S2: forming a gap wall to cover the top surface of the hard mask layer and the side walls of the hard mask layer and the grid;
step S3: and forming a metal silicide layer on the surface of the gap wall.
The manufacturing method of the invention forms the spacer covering the hard mask layer and the top surface and the side wall of the grid to replace the existing spacer only formed on the side wall of the grid, and then forms the metal silicide layer M0 on the surface of the spacer, and the manufacturing method of the invention does not need to use a silicide barrier layer, therefore, the manufacturing method of the invention has the following advantages:
1) the formed metal silicide layer has better quality because a new clearance wall profile is provided, which is beneficial to the formation of the metal silicide layer;
2) since a silicide barrier layer (including silicide barrier layer deposition and etching processes) is not required, the production cost and the production cycle time are reduced;
3) because a thicker dielectric layer is arranged between the formed metal silicide layer and the grid electrode, the crosstalk between the metal silicide layer and the grid electrode can be reduced, and the performance of a device is improved.
Next, a method for manufacturing a semiconductor device of the present invention is described in detail with reference to fig. 2A to 2E, in which fig. 2A to 2E show schematic structural views of a device obtained by relevant steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
First, as shown in fig. 2A, a semiconductor substrate (not shown) is provided, on which a gate 201 is formed, and a hard mask layer is formed on the gate 201.
Specifically, the semiconductor substrate may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others. As an example, in the present embodiment, the constituent material of the semiconductor substrate is single crystal silicon.
Structures such as Shallow Trench Isolation (STI) and well regions may also be formed in the semiconductor substrate, which is not limited herein.
In one example, the method for forming the gate 201 and the hard mask layer includes steps a1 to a 4:
first, step a1 is performed to sequentially deposit a gate layer and a hard mask layer on the semiconductor substrate.
In one embodiment, the gate layer is made of polysilicon, and a metal, a metal nitride, a metal silicide or the like may be used as the material of the gate layer, preferred methods for forming the gate layer include Chemical Vapor Deposition (CVD) such as low temperature chemical vapor deposition (L TCVD), low pressure chemical vapor deposition (L PCVD), rapid thermal chemical vapor deposition (L TCVD), plasma chemical vapor deposition (PECVD), and the like.
Any suitable hard mask material known to those skilled in the art may be used as the hard mask layer, for example, the hard mask layer may comprise SiO2Preferably, the hard mask layer includes an oxide layer 202 and a nitride layer 203 stacked from bottom to top, wherein the oxide layer 202 may use a High Temperature Oxide (HTO), the oxide layer 202 may specifically include silicon oxide, and the material of the nitride layer 203 includes silicon nitride. The hard mask layer can be formed by using methods such as a chemical vapor deposition method, a physical vapor deposition method and the like, and the thickness of the hard mask layer can be set reasonably according to an actual process.
Next, step A2 is performed to form a patterned photoresist layer on the hard mask layer. A photoresist layer may be first spin-coated on the semiconductor substrate and then patterned by a photolithography process (e.g., exposure and development steps) to form the patterned photoresist layer, which defines a pattern of a gate electrode to be formed.
Then, step a3 is performed, and the hard mask layer is etched by using the patterned photoresist layer as a mask. The hard mask layer may be etched using a dry etch to pattern the hard mask layer. The photoresist layer can also be removed by ashing.
Finally, step a4 is performed, and the gate layer is etched by using the hard mask layer as a mask to form the gate 201.
The etching can be performed by dry etching or wet etching, wherein the dry etching process can be reactive ion etching, ion beam etching, plasma etching, laser ablation, or any combination of these methods. A single etching method may also be used, or more than one etching method may also be used.
Optionally, a pre-clean process may be performed to remove impurities after the gate 201 is formed. The pre-washing process may be a reactive (reactive) or non-reactive (non-reactive) pre-washing process. For example, the reactive process is a plasma process using a hydrogen-containing plasma (hydrogen-containing plasma), and the non-reactive process is a plasma process using an argon-containing plasma (argon-containing plasma).
Optionally, after a pre-clean process, the gate 201 may be re-oxidized to form a thin oxide layer (not shown), which may be any suitable oxidation process known to those skilled in the art and will not be described herein.
Subsequently, as shown in fig. 2B, a spacer material layer 204a is deposited to cover the hard mask layer, the gate 201 and the semiconductor substrate.
Specifically, the spacer material layer 204a may be made of one of silicon oxide, silicon nitride, and silicon oxynitride, or a combination thereof. As a preferred embodiment of this embodiment, the spacer material layer 204a is silicon oxide, such as Tetraethylorthosilicate (TEOS) oxide, which uses Tetraethylorthosilicate (TEOS) solution as a basic raw material to deposit silicon oxide (PETEOS) by using plasma enhanced chemical vapor deposition method, and optionally a precleaning step is performed before deposition to remove impurities on the semiconductor substrate.
Subsequently, as shown in fig. 2C, a patterned photoresist layer 205 is formed to cover portions of the spacer material layer 204a above and on both sides of the hard mask layer.
Specifically, a photoresist layer 205 may be spin-coated on the semiconductor substrate, and then the photoresist layer 205 is patterned by a photolithography process (e.g., exposure and development steps) to form the patterned photoresist layer 205, which covers a portion of the spacer material layer 204a above and on both sides of the hard mask layer, wherein the patterned photoresist layer 205 defines a predetermined spacer pattern.
Subsequently, as shown in fig. 2D, with the patterned photoresist layer as a mask, etching and removing a portion of the spacer material layer to form the spacer 204, where the formed spacer 204 covers a top surface of the hard mask layer, and covers sidewalls of the hard mask layer and the gate 201, and may further extend to an outer portion of the surface of the semiconductor substrate.
The etching in this step may use dry etching or wet etching, a conventional dry etching process such as reactive ion etching, ion beam etching, plasma etching, laser ablation, or any combination of these methods. A single etching method may be used, or more than one etching method may be used.
In this embodiment, the existing spacer self-aligned etching process is replaced by performing photolithography and etching processes on the spacer material layer, and the formed spacer not only covers the sidewalls of the hard mask layer and the gate 201, but also covers the top surface of the hard mask layer.
Finally, the patterned photoresist layer 205 may be removed using an ashing process.
Subsequently, as shown in fig. 2D, a polysilicon layer 206 is formed on the surface of the spacer 204.
Specifically, the polysilicon layer 206 may be deposited to cover the semiconductor substrate, a patterned photoresist layer may be formed by a photolithography process to cover a predetermined remaining polysilicon layer, the polysilicon layer outside the spacer 204 may be removed by etching using the patterned photoresist layer as a mask, only the polysilicon layer 206 on the surface of the spacer 204 may be remained, and finally, the patterned photoresist layer may be removed.
Illustratively, the polysilicon layer 206 may be formed by a low pressure chemical vapor deposition (L PCVD) process, the process conditions for forming the polysilicon include a reaction gas of Silane (SiH)4) The flow rate of the silane can be 100-200 cubic centimeters per minute (sccm), such as 150 sccm; the temperature in the reaction cavity can be 700-750 ℃; the pressure in the reaction chamber can be 250 to 350 millimeters of mercury (mTorr), such as 300 mTorr; the reaction gas can also comprise buffer gas, the buffer gas can be helium or nitrogen, and the helium and the nitrogen can be used for reactionThe flow rate of gas may range from 5 to 20 liters per minute (slm), such as 8slm, 10slm or 15 slm.
The step can adopt wet etching or dry etching to the etching of the polysilicon. In a specific embodiment of the present invention, the etch-back process may be performed by using a dry etching process, which includes but is not limited to: reactive Ion Etching (RIE), ion beam etching, plasma etching, or laser cutting. For example, using plasma etching, the etching gas can be oxygen (O) -based2-based) gas. Wherein, the etching gas of the dry etching can also be hydrogen bromide gas, carbon tetrafluoride gas or nitrogen trifluoride gas. It should be noted that the above etching method is only exemplary and not limited to this method, and those skilled in the art may select other common methods.
The polysilicon layer 206 may be replaced by other silicon-containing semiconductor material layers.
Finally, as shown in fig. 2E, a metal silicide layer 207 is formed on the surface of the spacer 204.
The method for forming the metal silicide layer 207(silicide) includes the steps of: a metal layer, which may comprise nickel (nickel), cobalt (cobalt), and platinum (platinum) materials or combinations thereof, is first deposited to cover the polysilicon layer. And then carrying out thermal annealing to cause the metal layer to have silicification with silicon below the metal layer, so that the part of the metal layer contacted with the polycrystalline silicon layer reacts to form the metal silicide layer. An etchant is then used that attacks the metal layer, but does not attack the metal silicide layer, to remove the unreacted metal layer.
The steps of depositing and etching the silicide barrier layer are not needed before the metal silicide layer 207 is formed, so that the cost and the time are saved.
In addition, since the profile of the spacer 204 formed in the present embodiment is more favorable for the formation of the metal silicide layer, the formed metal silicide layer has better quality.
The hard mask layer (including the oxide layer 202 and the nitride layer 203) between the gate 201 and the metal silicide layer 207 and the spacer 204 on the top surface of the hard mask layer are both used as dielectric layers, and compared with the prior art, the thickness of the dielectric layer is thicker, so that the crosstalk between the metal silicide layer and the gate can be reduced, and the device performance can be improved.
Through the above steps, the simple introduction of the manufacturing method of the semiconductor device of the present invention is completed, and other steps are required for the complete device preparation, which is not described herein again.
The manufacturing method of the invention forms the spacer covering the hard mask layer and the top surface and the side wall of the grid to replace the existing spacer only formed on the side wall of the grid, and then forms the metal silicide layer M0 on the surface of the spacer, and the manufacturing method of the invention does not need to use a silicide barrier layer, therefore, the manufacturing method of the invention has the following advantages:
1) the formed metal silicide layer has better quality because a new clearance wall profile is provided, which is beneficial to the formation of the metal silicide layer;
2) since a silicide barrier layer (including silicide barrier layer deposition and etching processes) is not required, the production cost and the production cycle time are reduced;
3) because a thicker dielectric layer is arranged between the formed metal silicide layer and the grid electrode, the crosstalk between the metal silicide layer and the grid electrode can be reduced, and the performance of a device is improved.
Example two
The invention also provides a semiconductor device prepared by the manufacturing method.
As an example, as shown in fig. 2E, the semiconductor device of the present invention includes a semiconductor substrate (not shown).
Specifically, the semiconductor substrate may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others. As an example, in the present embodiment, the constituent material of the semiconductor substrate is single crystal silicon.
Structures such as Shallow Trench Isolation (STI) and well regions may also be formed in the semiconductor substrate, which is not limited herein.
Further, a gate 201 is formed on the semiconductor substrate, and a hard mask layer is formed on the gate 201.
In one embodiment, the gate 201 is made of polysilicon, and metal, metal nitride, metal silicide or the like may be used as the gate material. The thickness of the gate can be set appropriately according to the size of the actual device and is not particularly limited herein.
Any suitable hard mask material known to those skilled in the art may be used as the hard mask layer, for example, the hard mask layer may comprise SiO2Preferably, the hard mask layer includes an oxide layer 202 and a nitride layer 203 stacked from bottom to top, wherein the oxide layer 202 may use a High Temperature Oxide (HTO), the oxide layer 202 may specifically include silicon oxide, and the material of the nitride layer 203 includes silicon nitride.
Further, a gap wall 204 is formed on the top surface of the hard mask layer and the sidewalls of the hard mask layer and the gate 201, and may further extend to the surface of the portion of the semiconductor substrate outside the gate 201.
The material of the spacer 204 may be one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. As a preferred embodiment of this embodiment, the spacer 204 is silicon oxide, such as Tetraethylorthosilicate (TEOS) oxide, which is deposited by plasma enhanced chemical vapor deposition (PETEOS) using Tetraethylorthosilicate (TEOS) solution as a base material.
Further, a metal silicide layer 207 is formed on the surface of the spacer 204.
Wherein the metal silicide layer 207 serves as a metal layer M0, serving as a connection structure to reduce the device size.
The material of the metal silicide layer 207 depends on its specific formation process, and may be NiSi, CoSi, PtSi, or the like, for example.
The hard mask layer (including the oxide layer 202 and the nitride layer 203) between the gate 201 and the metal silicide layer 207 and the spacer 204 on the top surface of the hard mask layer are both used as dielectric layers, and compared with the prior art, the thickness of the dielectric layer is thicker, so that the crosstalk between the metal silicide layer and the gate can be reduced, and the device performance can be improved.
The semiconductor device of the present invention also has the above-described advantages because it employs the manufacturing method of the first embodiment.
EXAMPLE III
The invention also provides an electronic device comprising the semiconductor device described in embodiment two or a semiconductor device obtained by using the manufacturing method described in embodiment one.
The electronic device of this embodiment may be any electronic product or device, such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a recording pen, an MP3, an MP4, a PSP, and the like, and may also be any intermediate product including a circuit. The electronic device of the embodiment of the invention has better performance due to the use of the semiconductor device.
Wherein figure 4 shows an example of a mobile telephone handset. The mobile phone handset 400 is provided with a display portion 402, operation buttons 403, an external connection port 404, a speaker 405, a microphone 406, and the like, which are included in a housing 401.
Wherein the mobile phone handset comprises the semiconductor device of embodiment two, the semiconductor device comprising:
the semiconductor device comprises a semiconductor substrate, a grid electrode and a hard mask layer, wherein the grid electrode is formed on the semiconductor substrate;
forming gap walls on the top surface of the hard mask layer and the side walls of the hard mask layer and the grid;
a metal silicide layer is formed on the surface of the spacer.
The electronic device of the embodiment of the invention has better performance due to the use of the semiconductor device.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims (10)

1. A method of manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate, forming a grid on the semiconductor substrate, and forming a hard mask layer on the grid;
forming a gap wall to cover the top surface of the hard mask layer and the side walls of the hard mask layer and the grid;
and forming a metal silicide layer on the top surface of the hard mask layer and the surfaces of the clearance walls covering the hard mask layer and the side walls of the grid.
2. The manufacturing method according to claim 1, wherein the step of forming the spacer includes the processes of:
depositing a spacer material layer to cover the hard mask layer, the gate and the semiconductor substrate;
forming a patterned photoresist layer to cover the gap wall material layer above the hard mask layer and on the two sides of the hard mask layer;
and etching and removing part of the gap wall material layer by taking the patterned photoresist layer as a mask so as to form the gap wall.
3. The manufacturing method according to claim 1, wherein the step of forming the metal silicide layer comprises the processes of:
forming a polysilicon layer on the surface of the gap wall;
depositing a metal layer to cover the polysilicon layer;
and carrying out thermal annealing to enable the metal layer to react with the part in contact with the polycrystalline silicon layer to form the metal silicide layer.
4. The method of manufacturing of claim 1, wherein the step of forming the gate comprises the process of:
sequentially depositing a grid layer and a hard mask layer on the semiconductor substrate;
forming a patterned photoresist layer on the hard mask layer;
etching the hard mask layer by taking the patterned photoresist layer as a mask;
and etching the gate layer by taking the hard mask layer as a mask to form the gate.
5. The manufacturing method according to claim 1 or 4, wherein the hard mask layer includes an oxide layer and a nitride layer stacked from bottom to top.
6. The method of claim 1, wherein the gate comprises a material comprising polysilicon.
7. A semiconductor device obtained by the method of any one of claims 1 to 6, comprising:
the semiconductor device comprises a semiconductor substrate, a grid electrode and a hard mask layer, wherein the grid electrode is formed on the semiconductor substrate;
forming gap walls on the top surface of the hard mask layer and the side walls of the hard mask layer and the grid;
a metal silicide layer is formed on the surface of the spacer.
8. The semiconductor device according to claim 7, wherein the hard mask layer includes an oxide layer and a nitride layer stacked from bottom to top.
9. The semiconductor device of claim 7, wherein the spacer further extends onto a portion of the surface of the semiconductor substrate outside the gate.
10. An electronic device, characterized in that the electronic device comprises the semiconductor device according to any one of claims 7 to 9.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6081016A (en) * 1998-03-31 2000-06-27 Seiko Epson Corporation CMOS device with improved wiring density
US6555455B1 (en) * 1998-09-03 2003-04-29 Micron Technology, Inc. Methods of passivating an oxide surface subjected to a conductive material anneal
JP2010219541A (en) * 2010-04-20 2010-09-30 Renesas Electronics Corp Semiconductor device and method of manufacturing the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6081016A (en) * 1998-03-31 2000-06-27 Seiko Epson Corporation CMOS device with improved wiring density
US6555455B1 (en) * 1998-09-03 2003-04-29 Micron Technology, Inc. Methods of passivating an oxide surface subjected to a conductive material anneal
JP2010219541A (en) * 2010-04-20 2010-09-30 Renesas Electronics Corp Semiconductor device and method of manufacturing the same

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