KR20120033640A - Method for manufacturing semiconductor device using tungsten gapfill - Google Patents

Method for manufacturing semiconductor device using tungsten gapfill Download PDF

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KR20120033640A
KR20120033640A KR1020100095266A KR20100095266A KR20120033640A KR 20120033640 A KR20120033640 A KR 20120033640A KR 1020100095266 A KR1020100095266 A KR 1020100095266A KR 20100095266 A KR20100095266 A KR 20100095266A KR 20120033640 A KR20120033640 A KR 20120033640A
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tungsten
film
semiconductor device
tungsten film
containing gas
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KR1020100095266A
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Korean (ko)
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김치호
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A semiconductor device manufacturing method which uses a tungsten gap filling process is provided to reduce a core due to a tungsten gap filling process only using surface treatment and washing processes, thereby improving device properties and process stability by reducing risk of a post process. CONSTITUTION: A second film(22) is formed on a first film(21). An open part(23) is formed by selectively etching the second film. A tungsten film which fills the open part is formed on the front surface of the second film. A barrier film pattern(24A) and a first tungsten film pattern(25A) are remaining within the open part by separating the tungsten film. A second tungsten film(27) which fills a gap of a core is formed by a surface treatment process(26).

Description

Method of manufacturing semiconductor device using tungsten gapfill {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING TUNGSTEN GAPFILL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method, and more particularly, to a semiconductor device manufacturing method involving a tungsten gapfill.

As semiconductor devices are becoming more integrated, reduced, and faster, securing a contact process margin is an urgent problem, and a device having a high signal transmission speed is required for rapid processing of information. In general, polysilicon or metal silicide having excellent thermal stability is mainly used as a material such as a gate electrode, a bit line, a metal wiring, or a metal contact.

However, with the higher integration of semiconductor devices, an alternative material having better electrical conductivity than polysilicon or metal silicide is required, and recently, tungsten (W) is mainly used as the replacement material.

Recently, a tungsten gapfill process is inevitably involved in the buried gate process and the metal contact process. The tungsten gapfill process is a process of filling tungsten in an open region having a constant aspect ratio. If the aspect ratio of the open part is large, the tungsten gapfill process should be performed using a method having excellent step coverage. Open portions include contact holes, trenches, recesses, and the like.

In the metal contact process, tungsten is gap-filled after barrier metal formation by using chemical vapor deposition (CVD) with good step coverage. In this case, tungsten may be deposited at low temperature (about 300 ° C) to improve the seam.

1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

As shown in FIG. 1A, a second film 12 is formed on the first film 11. The second layer 12 is etched to form an open portion 13 exposing a portion of the surface of the first layer 11. The open portion 13 includes contact holes, trenches, recesses, and the like, and has a constant aspect ratio.

The barrier layer 14 is formed on the entire surface including the open portion 13. The tungsten film 15 for gap-filling the open portion 13 is formed on the barrier film 14. This is called a tungsten gapfill process. The tungsten film 15 is formed by using chemical vapor deposition (CVD) with excellent step coverage.

As shown in FIG. 1B, the tungsten film 15 is separated. To this end, the planarization process is performed by using chemical mechanical polishing (CMP). By this planarization process, tungsten wiring 15A buried in the open portion 13 is formed. The barrier film pattern 14A also remains in the open portion 13. The tungsten wiring 15A is a metal contact, a buried gate, a bit line, or the like.

The tungsten gapfill process according to the prior art is virtually impossible to completely fill without a seam (see reference numeral 'S' in FIG. 1A), and proceeds to a level that controls the size of the seam S. FIG.

However, the shim S inevitably causes a loss of the tungsten film 15 during the planarization process such as CMP. For example, the tungsten film is excessively lost by a mechanical polishing process that is polished in the CMP process, or an excess water (H 2 O 2 ) used as a metal slurry. That is, the seam is further extended by the CMP process as shown by reference numeral 'S1'.

As the size of the seam S increases before the CMP progresses, the seam S1 by the CMP becomes more severe.

The shims (S, S1) as described above affect the subsequent gap fill process and etching process, and as the shims increase, the contact resistance increases, leading to deterioration of device characteristics.

In order to minimize the seam, a method of depositing a metal having a better gap fill capability after the CMP process of the tungsten film and then CMP is proposed, but this requires an additional deposition process and a CMP process, resulting in a low mass productivity and a high cost. Moreover, there is a problem that the seam recurs by an additional CMP process.

An object of the present invention is to provide a method for manufacturing a semiconductor device that can minimize the seam by the tungsten gapfill process.

A semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of forming a second film on the first film; Etching the second layer to form an open portion; Forming a tungsten film filling the open part on the entire surface of the second film; Separating the tungsten film so that the tungsten film remains inside the open portion; And flowing a tungsten-containing gas into the residual tungsten film. The tungsten-containing gas is characterized in that it comprises tungsten hexafluoride. In the step of flowing the tungsten-containing gas is characterized in that for further flowing a reducing gas.

In addition, the semiconductor device manufacturing method of the present invention comprises the steps of forming an insulating film on the substrate; Etching the insulating film to form a contact hole; Forming a barrier film on an entire surface of the insulating film including the contact hole; Forming a tungsten film to fill the contact hole on the barrier film; Separating the tungsten film and the barrier film so that the tungsten film remains in the contact hole; Flowing a tungsten-containing gas into the residual tungsten film; And cleaning to remove by-products remaining on the surface of the insulating film. The tungsten-containing gas is characterized in that it comprises tungsten hexafluoride. Further flowing a reducing gas in the step of flowing the tungsten-containing gas, the reducing gas is characterized in that it comprises any one of silane, hydrogen or diborane.

The present invention described above has the effect of reducing the process stability and the risk of the subsequent process and improving the device characteristics by reducing the seam by the tungsten gapfill process only by the surface treatment and cleaning process, which has less TAT (Turn Around Time) and process cost. There is.

1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
2A to 2D are cross-sectional views illustrating a tungsten gapfill method of a semiconductor device according to an embodiment of the present invention.
3A to 3G are cross-sectional views illustrating a method of manufacturing a buried gate using a tungsten gapfill process according to an exemplary embodiment of the present invention.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

2A to 2D are cross-sectional views illustrating a tungsten gapfill method of a semiconductor device according to an embodiment of the present invention.

As shown in FIG. 2A, a second film 22 is formed on the first film 21. The first film 21 may include a substrate such as a silicon substrate, or may include a gate electrode, a landing plug, a plate, or the like. In general, metal contacts, in particular metal contacts referred to as 'M1C', are formed on the plate and the gate electrode (peripheral circuit region) of the capacitor. The metal contact may include a bit line contact. The second film 22 includes an insulating film, and the second film 22 is called an interlayer insulating film. The second film 22 includes an oxide film such as BPSG.

The second layer 22 is selectively etched to form an open portion 23 exposing a part of the surface of the first layer 21. The opening part 23 includes a contact hole, a trench, a recess, etc. according to the purpose of use. In the following embodiment, it is assumed that the opening 23 is used as a contact hole. Accordingly, the second layer 22 is etched using the contact mask to form the open portion 23. The open part 23 includes M1C in which the metal contact is to be buried.

Next, the barrier film 24 is formed on the second film 22 including the open portion 23. Here, the barrier layer 24 includes a titanium layer Ti and a titanium nitride layer TiN. For example, the barrier film 24 may be formed by stacking a titanium film and a titanium nitride film. The barrier film 24 is formed using chemical vapor deposition (CVD). The barrier layer 24 may include an adhesive layer to adhere to the first layer 21 and a diffusion barrier layer to prevent the tungsten layer from reacting with the first layer 21. When the barrier film 24 is formed by stacking a titanium film and a titanium nitride film, the titanium film becomes an adhesive film and the titanium nitride film becomes a diffusion barrier film.

A first tungsten film 25 is formed on the barrier film 24 to gap-fill the open portion 23. This is called a tungsten gapfill process. The first tungsten film 25 is formed by chemical vapor deposition (CVD). When gap filling the first tungsten film 25, the seam S may be generated due to the aspect ratio of the open part 23. When depositing the first tungsten film 25, tungsten hexafluoride (WF 6 ) gas is used as a tungsten source, and silane (Silane, SiH 4 ), hydrogen (H 2 ) or diborane ( Diborane, B 2 H 6 ).

As shown in FIG. 2B, the first tungsten film 25 is separated. To this end, the process proceeds using CMP, and the barrier layer pattern 24A and the first tungsten layer pattern 25A remain in the open part 23. The seam may be further extended by the CMP process as shown by reference numeral 'S1'. The separation process may proceed to etchback.

As shown in FIG. 2C, tungsten oxide may be formed after the separation process such as CMP, and thus, a pre-cleaning process is performed to remove the tungsten oxide.

Next, tungsten-containing gas such as tungsten hexafluoride (WF 6 ) gas is flowed over the entire structure including the first tungsten film pattern 25A. This is referred to as a surface treatment step 26, and a second tungsten film 27 for gap filling the seam is formed by the surface treatment step 26 for flowing tungsten hexafluoride gas. In order to form the second tungsten film 27, a reducing gas is flowed together with the tungsten hexafluoride gas. Reducing gas is a substance that helps reduce the reaction of tungsten hexafluoride (WF 6 ) gas. The reducing gas includes any one of silane (Silane, SiH 4 ), hydrogen (H 2 ) or diborane (Diborane, B 2 H 6 ).

Silane (SiH 4 ) may be used as a pretreatment before flowing tungsten hexafluoride (WF 6 ) gas. If the tungsten hexafluoride gas is flowed after the pretreatment using silane (SiH 4 ), the deposition of the second tungsten film 27 is easier.

The reaction between silane and tungsten hexafluoride gas is as follows.

Figure pat00001

Hydrogen further improves the step coverage of the second tungsten film 27 as compared to silane (SiH 4 ). In other words, hydrogen has a greater reducing power than silane.

Diborane (B 2 H 6 ) has a greater reducing power than silane, thereby further improving the step coverage of the second tungsten film 27. When diborane is used as the reducing gas, the second tungsten film 27 can be formed while sufficiently gap filling the seam.

The surface treatment step 26 for forming the second tungsten film 27 proceeds at a low temperature of 300 ° C. As such, when the second tungsten film 27 is deposited at a low temperature of 300 ° C. or lower, the deposition rate of the second tungsten film 27 is lowered to improve the gap fill capability. When a low temperature process of 300 ° C. or less is applied, the reaction between the oxide film used as the second film 22 and the tungsten hexafluoride gas can be lowered. This suppresses the formation of unnecessary byproducts.

On the other hand, in order to increase the deposition rate by increasing the reactivity may be raised to 300 ℃ or more.

In order to improve the step coverage of the second tungsten film 27, the partial pressure of tungsten hexafluoride gas may be increased and controlled. For the same reason, the partial pressure of the reducing gas can be lowered.

Preferably, the surface treatment process 26 sets a process temperature in the range of normal temperature-500 degreeC. The process pressure is in the range of 0.001 to 1000 torr. Process time shall be in the range of 1 to 10000 seconds.

When the second tungsten film 27 is deposited by the surface treatment process 26 using tungsten hexafluoride gas, impurities 28 which are not deposited may remain on the surface of the second film 22 where the insulating film is used. . The impurity 28 includes tungsten hexafluoride gas that is not deposited into the second tungsten film 27 and remains unbound at the surface. In general, even in the case of insulator films such as oxide films, even if tungsten hexafluoride gas flows, nucleation necessary for forming tungsten into a continuous film is very difficult. Therefore, the second tungsten film 27 is selectively deposited only on the surface of the first tungsten film pattern 25A. That is, in the case of performing the surface treatment step 26 using tungsten hexafluoride gas, a metal bond is formed between the tungsten, and the tungsten film is easily deposited.

As shown in FIG. 2D, a cleaning process 29 is performed to remove impurities 28 remaining without being deposited on the surface of the second film 22. At this time, the cleaning process 29 proceeds to solvent cleaning of amine (Amine) series (ACT, RAM), thereby preventing the loss of the second tungsten film 27 and the first tungsten film pattern 25A. do.

On the other hand, the cleaning process may be performed using the fruit water (H 2 O 2 ) to remove the impurities 28, the second tungsten film 27 and the first tungsten film pattern in the case of the fruit water (H 2 O 2 ) Since there is a problem of oxidizing (25A), it is not used or its use is minimized.

The cleaning process (29) includes SPM (H 2 SO 4 / H 2 O 2 / DI), SC-1 cleaning, hydrofluoric acid, BOE (Buffered Oxide Etchant), phosphoric acid (H 3 PO) 4 ) It is also possible to apply cleaning processes such as series and mega sonic.

As a result, the present invention removes the seam by selectively depositing a tungsten film only in the open portion 23 only by the surface treatment process 26 and the cleaning process 29 that do not require the CMP process.

The tungsten gapfill process as described above may also be applied to a buried gate process.

3A to 3G are cross-sectional views illustrating a method of manufacturing a buried gate using a tungsten gapfill process according to an exemplary embodiment of the present invention.

As shown in FIG. 3A, the device isolation layer 32 is formed on the semiconductor substrate 31 through a shadow trench isolation (STI) process. In this case, the device isolation layer 32 may include an oxide film such as a high density plasma CVD oxide (HDP), a spin on dielectric (SOD), or the like. The active region 33 is defined by the device isolation layer 32.

Subsequently, the trench 36 in which the buried gate is to be formed is formed by an etching process using the pad layer 34 and the hard mask layer 35 as an etching barrier. In this case, the trench 36 may be formed by etching not only the active region 33 but also the device isolation layer 32. Typically, since the gate has a line type, the trench 36 is also in the form of a line, and the line 36 of the trench 36 crosses the active region 33 and the device isolation layer 32 at the same time. 36 is formed. However, since the etching selectivity between the active region 33 and the device isolation layer 32 is different, as the etching proceeds more toward the device isolation layer 32, the depth of the trench 36 may be deeper in the device isolation layer 32. . Such a structure having a depth difference is called a fin structure.

An etching process for forming the trench 36 uses the hard mask layer 35 as an etching barrier, and the hard mask layer 35 may be patterned by a photoresist pattern (not shown). The hard mask layer 35 is preferably a material having a high etching selectivity when etching the semiconductor substrate 31. For example, the hard mask film 35 may include a nitride film or a structure in which an oxide film and a nitride film are stacked. When the hard mask layer 35 is applied, the photoresist pattern may be stripped after the trench 36 is formed.

As shown in FIG. 3B, a gate insulating film 37 is formed on the surface of the trench 36. The gate insulating film 37 includes an oxide film such as silicon oxide film (SiO 2 ). In addition, the gate insulating layer 37 may include a high-k material such as HfO 2 and HfSiO. After the gate insulating layer 37 is formed, the surface may be nitrided through a nitriding process.

The barrier film 38 is formed on the entire surface including the gate insulating film 37. Here, the barrier film 38 includes a titanium film and a titanium nitride film. For example, the barrier film 38 applies a titanium nitride film.

A first tungsten film 39 for gap filling the trench 36 is formed on the barrier film 38. This is called a tungsten gapfill process. The first tungsten film 39 is formed by chemical vapor deposition (CVD). When gap filling the first tungsten film 39, the seam S may be generated due to the aspect ratio of the trench 36.

As shown in FIG. 3C, the first tungsten film 39 is separated. To this end, a separation process is performed using CMP, and the barrier layer pattern 38A and the first tungsten layer pattern 39A remain in the trench 36. The shim S1 may be further extended by the CMP process.

As shown in FIG. 3D, since tungsten oxide may be formed after the separation process such as CMP, a pre-cleaning process is performed to remove the tungsten oxide.

Next, tungsten-containing gas such as tungsten hexafluoride (WF 6 ) gas is flowed over the entire structure including the first tungsten film pattern 39A. This is referred to as a surface treatment step 42, and a second tungsten film 40 for gap filling the seam is formed by the surface treatment step 42 for flowing tungsten hexafluoride gas. In order to form the second tungsten film 40, a reducing gas is flowed together with the tungsten hexafluoride gas. Reducing gas is a substance that helps reduce the reaction of tungsten hexafluoride (WF 6 ) gas. The reducing gas includes any one of silane (Silane, SiH 4 ), hydrogen (H 2 ) or diborane (Diborane, B 2 H 6 ).

Silane (SiH 4 ) may be used as a pretreatment before flowing tungsten hexafluoride (WF 6 ) gas. If the tungsten hexafluoride gas is flowed after the pretreatment using silane (SiH 4 ), the deposition of the second tungsten film 40 is easier.

Hydrogen further improves the step coverage of the second tungsten film 40 compared to silane (SiH 4 ). In other words, hydrogen has a greater reducing power than silane.

Diborane (B 2 H 6 ) has a greater reducing power than silane, thereby further improving the step coverage of the second tungsten film 40. Accordingly, when diborane is used as the reducing gas, the second tungsten film 40 can be formed while sufficiently gap filling the seam.

The surface treatment step 42 for forming the second tungsten film 40 proceeds at a low temperature of 300 ° C. As such, when the second tungsten film 40 is deposited at a low temperature of 300 ° C. or lower, the deposition rate of the second tungsten film 40 is lowered to improve the gap fill capability. When a low temperature process of 300 ° C. or less is applied, the reaction between the material used as the hard mask layer 35 and the tungsten hexafluoride gas can be lowered. This suppresses the formation of unnecessary byproducts.

On the other hand, in order to increase the deposition rate by increasing the reactivity may be raised to 300 ℃ or more.

In order to improve the step coverage of the second tungsten film 40, the partial pressure of tungsten hexafluoride gas may be increased and controlled. For the same reason, the partial pressure of the reducing gas can be lowered.

Preferably, the surface treatment process 42 sets the process temperature to the range of normal temperature-500 degreeC. The process pressure is in the range of 0.001 to 1000 torr. Process time shall be in the range of 1 to 10000 seconds.

When the second tungsten film 40 is deposited by the surface treatment process 42 using tungsten hexafluoride gas, impurities 41 that are not deposited may remain on the surface of the hard mask film 35. The impurity 41 includes tungsten hexafluoride gas that is not deposited into the second tungsten film 40 and remains unbound at the surface. In general, even in the case of flowing tungsten hexafluoride gas in an insulating film such as an oxide film, nucleation required for forming tungsten into a continuous film is very difficult. Therefore, the second tungsten film 40 is selectively deposited only on the surface of the first tungsten film pattern 39A. That is, in the case of performing the surface treatment step 42 using tungsten hexafluoride gas, tungsten is easily deposited by metal bonding between tungsten.

As shown in FIG. 3E, the cleaning process 43 is performed to remove the impurities 41. At this time, the cleaning process 43 proceeds to solvent cleaning of amine (Amine) series (ACT, RAM), thereby preventing the loss of the second tungsten film 40 and the first tungsten film pattern 39A. do.

On the other hand, the cleaning process may be performed by using the fruit water (H 2 O 2 ) to remove the impurities 41, in the case of the fruit water to oxidize the second tungsten film 40 and the first tungsten film pattern 39A There is a problem, so do not use or minimize its use.

The cleaning process 43 may include SPM (H 2 SO 4 / H 2 O 2 / DI), SC-1 cleaning, hydrofluoric acid, BOE (Buffered Oxide Etchant), phosphoric acid (H 3 PO) 4 ) It is also possible to apply cleaning processes such as series and mega sonic.

As shown in FIG. 3F, the barrier film pattern 38A, the first tungsten film pattern 39A, and the second tungsten 40 are recessed through an etchback process. As a result, a buried gate (BG) in which a portion of the trench 36 is buried is formed. The buried gate BG includes a barrier film pattern 38A and a first tungsten film pattern 39A. When the target of the etch back process is below the shim, the second tungsten film 40 may be removed during the etch back process.

As described above, since the second tungsten film 40 is formed after filling the seam existing in the first tungsten film pattern 39A, the etch back process is not affected by the seam. Thus, uniformity and process margin of the etch back process are ensured.

As shown in FIG. 3G, a capping layer 44 gap-filling the buried gate BG is formed. The capping film 44 includes an insulating film having excellent gap fill characteristics. For example, the capping film 44 includes an oxide film or a nitride film. The oxide film is formed by a high temperature oxidation (HTO) process or a deposition method using Tetra-Ethyl-Ortho-Silicate (TEOS). Alternatively, the deposition may be performed by plasma enhanced CVD (PECVD). The nitride film may be deposited by plasma chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), or catalytic chemical vapor deposition (Catalytic CVD).

Subsequently, the surface of the hard mask film 35 is planarized using chemical mechanical polishing (CMP).

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

21 substrate 22 interlayer insulating film
23 contact hole 24 barrier film
25: first tungsten film 25A: first tungsten film pattern
26 surface treatment step 27 second tungsten film

Claims (16)

Forming a second film on the first film;
Etching the second layer to form an open portion;
Forming a tungsten film filling the open part on the entire surface of the second film;
Separating the tungsten film so that the tungsten film remains inside the open portion; And
Flowing a tungsten-containing gas into the residual tungsten film;
≪ / RTI >
The method of claim 1,
The tungsten-containing gas includes tungsten hexafluoride.
The method of claim 2,
In the step of flowing the tungsten-containing gas,
A method for manufacturing a semiconductor device that further flows reducing gas.

The method of claim 3,
The reducing gas is a semiconductor device manufacturing method comprising any one of silane, hydrogen or diborane.
The method of claim 1,
The step of flowing the tungsten-containing gas,
A process for manufacturing a semiconductor device in which the process temperature is in the range of room temperature to 500 ° C, the process pressure is in the range of 0.001 to 1000 torr, and the process time is in the range of 1 to 10000 seconds.
The method of claim 1,
And said first film comprises a silicon substrate and said second film comprises an insulating film.
The method of claim 1,
And the open part includes a contact hole in which a contact is buried or a trench in which a buried gate is buried.
The method of claim 1,
Separating the tungsten film,
A semiconductor device manufacturing method proceeding to CMP or etch back.
The method of claim 1,
Before forming the tungsten film,
And forming a barrier film over the entire surface of the second film including the open portion.
Forming an insulating film on the substrate;
Etching the insulating film to form a contact hole;
Forming a barrier film on an entire surface of the insulating film including the contact hole;
Forming a tungsten film to fill the contact hole on the barrier film;
Separating the tungsten film and the barrier film so that the tungsten film remains in the contact hole;
Flowing a tungsten-containing gas into the residual tungsten film; And
Performing cleaning to remove by-products remaining on the surface of the insulating film
≪ / RTI >
The method of claim 10,
The tungsten-containing gas includes tungsten hexafluoride.
The method of claim 10,
In the step of flowing the tungsten-containing gas,
A method for manufacturing a semiconductor device that further flows reducing gas.
The method of claim 12,
The reducing gas is a semiconductor device manufacturing method comprising any one of silane, hydrogen or diborane.
The method of claim 10,
Separating the tungsten film,
A semiconductor device manufacturing method proceeding to CMP or etch back.
The method of claim 10,
The step of flowing the tungsten-containing gas,
A process for manufacturing a semiconductor device in which the process temperature is in the range of room temperature to 500 ° C, the process pressure is in the range of 0.001 to 1000 torr, and the process time is in the range of 1 to 10000 seconds.
The method of claim 10,
The step of performing the cleaning,
A semiconductor device manufacturing method comprising any one of amine-based, SPM, SC-1, hydrofluoric acid-based, BOE-based, phosphoric acid-based or megasonic.
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Publication number Priority date Publication date Assignee Title
WO2018111547A1 (en) * 2016-12-15 2018-06-21 Applied Materials, Inc. Nucleation-free gap fill ald process
WO2021055399A1 (en) * 2019-09-16 2021-03-25 Tokyo Electron Limited Method of bottom-up metallization in a recessed feature
US11903199B2 (en) 2021-03-22 2024-02-13 Samsung Electronics Co., Ltd. Through via structure, semiconductor device including the through via structure, and massive data storage system including the semiconductor device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018111547A1 (en) * 2016-12-15 2018-06-21 Applied Materials, Inc. Nucleation-free gap fill ald process
KR20190086054A (en) * 2016-12-15 2019-07-19 어플라이드 머티어리얼스, 인코포레이티드 Gap-filling ALD process without nucleation
KR20210035353A (en) * 2016-12-15 2021-03-31 어플라이드 머티어리얼스, 인코포레이티드 Nucleation-free gap fill ald process
US11289374B2 (en) 2016-12-15 2022-03-29 Applied Materials, Inc. Nucleation-free gap fill ALD process
WO2021055399A1 (en) * 2019-09-16 2021-03-25 Tokyo Electron Limited Method of bottom-up metallization in a recessed feature
US11450562B2 (en) 2019-09-16 2022-09-20 Tokyo Electron Limited Method of bottom-up metallization in a recessed feature
US11903199B2 (en) 2021-03-22 2024-02-13 Samsung Electronics Co., Ltd. Through via structure, semiconductor device including the through via structure, and massive data storage system including the semiconductor device

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