CN107170723B - Semiconductor device, preparation method thereof and electronic device - Google Patents

Semiconductor device, preparation method thereof and electronic device Download PDF

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Publication number
CN107170723B
CN107170723B CN201610126984.7A CN201610126984A CN107170723B CN 107170723 B CN107170723 B CN 107170723B CN 201610126984 A CN201610126984 A CN 201610126984A CN 107170723 B CN107170723 B CN 107170723B
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insulating layer
layer
semiconductor substrate
semiconductor
semiconductor material
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CN107170723A (en
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周鸣
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

The invention relates to a semiconductor device, a manufacturing method thereof and an electronic device. The semiconductor device includes: a semiconductor substrate; an insulating layer over the semiconductor substrate to cover the semiconductor substrate, wherein the insulating layer includes a good conductor of heat; a fin on the good thermal conductor. The insulating layer not only can play an insulating role, but also can well conduct heat generated by the device, so that the bottom self-heating effect of the device is avoided, and the performance and the yield of the semiconductor device are improved.

Description

Semiconductor device, preparation method thereof and electronic device
Technical Field
The invention relates to the field of semiconductors, in particular to a semiconductor device, a preparation method thereof and an electronic device.
Background
With the continuous development of semiconductor technology, the size of integrated circuit devices is required to be continuously reduced in order to improve the performance of the devices, and with the continuous reduction of the size of CMOS devices, the development of three-dimensional designs such as fin field effect transistors (finfets) is promoted.
Compared with the existing planar transistor, the FinFET device has more excellent performance in the aspects of channel control, short channel effect reduction and the like; a planar gate structure is disposed over the channel, and in finfets the gate is disposed around the fin, thus allowing static control from three sides, with more outstanding performance in static control.
A typical FinFET device includes a substrate (e.g., silicon-on-insulator (SOI)), at least one fin on the substrate, wherein the fin includes a material, wherein an L-shaped insulating layer surrounding the fin is formed on the fin, wherein the insulating layer has a height lower than the height of the fin, at least a portion of a sidewall of the fin is exposed, and finally a gate structure surrounding the fin is formed on the fin.
Although the FinFET device has the above advantages, there are some drawbacks, such as leakage current and Self-Heating Effect (Self-Heating Effect), which seriously affect the performance and yield of the FinFET device, and further improvement is needed in the FinFET device and the manufacturing method thereof to eliminate the above problems.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
The present invention provides a semiconductor device, including:
a semiconductor substrate;
an insulating layer over the semiconductor substrate to cover the semiconductor substrate, wherein the insulating layer includes a good conductor of heat;
a fin on the good thermal conductor.
Optionally, the insulating layer comprises a Boron Nitride (BN) layer.
Optionally, the insulating layer comprises a horizontal portion and a vertical portion;
the horizontal part is positioned above the semiconductor substrate, the vertical parts are of cylindrical structures and are inserted into the semiconductor substrate at intervals, and one end of each vertical part is connected with the horizontal part.
The invention also provides a preparation method of the semiconductor device, which comprises the following steps:
providing a semiconductor substrate, and forming an insulating layer of a good thermal conductor on the semiconductor substrate so as to cover the semiconductor substrate;
forming a semiconductor material layer on the insulating layer of the good thermal conductor to cover the insulating layer;
and patterning the semiconductor material layer to form a fin.
Optionally, the insulating layer of the good thermal conductor comprises a Boron Nitride (BN) layer.
Optionally, the step of forming the insulating layer of a good thermal conductor on the semiconductor substrate includes:
providing a semiconductor substrate, and sequentially forming a first dielectric layer and a first insulating layer on the semiconductor substrate, wherein the first insulating layer is a good thermal conductor;
patterning the first insulating layer, the first dielectric layer and the semiconductor substrate to form a plurality of grooves spaced from each other;
depositing the semiconductor material layer to fill the groove and cover the insulating layer;
depositing a second dielectric layer to cover the semiconductor material layer;
patterning the second dielectric layer and the semiconductor material layer to remove the semiconductor material layer in the groove to expose the groove;
and depositing a second insulating layer to fill the groove and cover the second dielectric layer, wherein the second insulating layer is a good thermal conductor.
Optionally, after forming the second insulating layer, the method further includes:
etching back the second insulating layer to the first insulating layer;
removing the second dielectric layer;
continuing to deposit the semiconductor material layer and annealing to fill the groove above the second insulating layer;
patterning the semiconductor material layer to form the fin on the second insulating layer.
Optionally, a PVD process is selected for depositing the semiconductor material layer.
Optionally, the second insulating layer is etched back to the first insulating layer with a plasma including chlorine.
Optionally, removing the second dielectric layer with a plasma comprising fluorine.
Optionally, the size of the opening of the groove is 0.13-0.35 um.
The invention also discloses an electronic device which comprises the semiconductor device.
In order to solve the problems in the prior art, the invention provides a preparation method of a semiconductor device, wherein an insulating layer with good heat conducting property is formed on a semiconductor substrate, and then a fin is formed on the insulating layer, the insulating layer not only can play an insulating role, but also can well conduct heat generated by the device, so that the bottom self-heating effect of the device is avoided, and the performance and the yield of the semiconductor device are improved.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. There are shown in the drawings, embodiments and descriptions thereof, which are used to explain the principles and apparatus of the invention. In the drawings, there is shown in the drawings,
FIGS. 1a-1l are schematic views illustrating a process for fabricating a semiconductor device according to the present invention;
FIG. 2 is an external view of an example of a mobile telephone handset of the present invention;
fig. 3 is a flow chart of a manufacturing process of the semiconductor device according to the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
In order to solve the problems in the prior art, the present invention provides a method for manufacturing a semiconductor device, wherein fig. 3 is a flow chart of a manufacturing process of the semiconductor device according to the present invention, and specifically includes the following steps:
step S1: providing a semiconductor substrate, and forming an insulating layer of a good thermal conductor on the semiconductor substrate so as to cover the semiconductor substrate;
step S2: forming a semiconductor material layer on the insulating layer of the good thermal conductor to cover the insulating layer;
step S3: and patterning the semiconductor material layer to form a fin.
The insulating layer of the good thermal conductor in the present invention may be selected from those materials having high heat transfer efficiency and required to have good insulating properties, for example, a BN material layer may be selected, but is not limited to this example.
Wherein, the semiconductor substrate selects Si as a substrate for forming a BN material layer in the FINFET device.
Optionally, the semiconductor material layer is made of Si, and the semiconductor material layer may be subjected to high-temperature annealing under the action of the silicon substrate to form single crystal silicon.
Further, the semiconductor material layer may be formed by a PVD process.
In order to solve the problems in the prior art, the invention provides a preparation method of a semiconductor device, wherein an insulating layer with good heat conducting property is formed on a semiconductor substrate, and then a fin is formed on the insulating layer, the insulating layer not only can play an insulating role, but also can well conduct heat generated by the device, so that the bottom self-heating effect of the device is avoided, and the performance and the yield of the semiconductor device are improved.
Example one
The present invention provides a method for manufacturing a semiconductor device, which is described in detail below with reference to the accompanying drawings.
Wherein, FIGS. 1a-1l are schematic views of a process for manufacturing a semiconductor device according to the present invention; fig. 2 is an external view of an example of a mobile phone handset in the present invention.
Step 10 is executed to provide a semiconductor substrate 101, and a first dielectric layer 102 and a first insulating layer 103 are sequentially formed on the semiconductor substrate 101, wherein the first insulating layer is a good thermal conductor.
Specifically, as shown in fig. 1a, in this step, the semiconductor substrate 101 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others.
In this embodiment the semiconductor substrate 101 is selected from silicon.
Then, a first dielectric layer 102 is formed on the semiconductor substrate 101, wherein the first dielectric layer 102 includes an oxide, and a formation method of the oxide may be formed by a deposition method, such as a chemical vapor deposition method, an atomic layer deposition method, or by thermally oxidizing a surface of the semiconductor substrate, which is not described herein again.
As shown in fig. 1b, the first insulating layer 103 is formed on the first dielectric layer 102, wherein in the present invention, the first insulating layer 103 includes an insulating layer of a good thermal conductor, wherein the good thermal conductor refers to a substance that is good at heat transfer, and the good thermal conductor generally has the characteristics of fast heat absorption and fast heat dissipation, and in the present invention, the first insulating layer 103 (good thermal conductor) may be a material with high heat transfer efficiency, which can quickly absorb and conduct heat generated by the fin, and needs to have good insulating performance, for example, a layer of Boron Nitride (BN) may be used, but is not limited to this example.
Here, the first insulating layer 103 may be formed by a Chemical Vapor Deposition (CVD) method, a Physical Vapor Deposition (PVD) method, a Low Pressure Chemical Vapor Deposition (LPCVD) method, or the like.
And 11, patterning the first insulating layer, the first dielectric layer and the semiconductor substrate to form a plurality of grooves which are spaced from each other.
Specifically, as shown in fig. 1c, in this step, a plurality of grooves are formed in the first insulating layer, the first dielectric layer, and the semiconductor substrate at intervals, the size of the opening of the groove is 0.13 to 0.35um, and the groove with the size is formed, so that the filling performance in the subsequent groove filling process is improved, and the problems such as holes are avoided.
In this step, a mask layer having an opening, such as a photoresist layer, is formed on the first insulating layer, and then the first insulating layer, the first dielectric layer, and the semiconductor substrate are etched using the photoresist layer as a mask to form the groove.
Wherein the depth of the groove is not limited to a range of values.
Step 12 is performed to deposit a layer of semiconductor material 104 and anneal to fill the recess and cover the insulating layer.
In particular, as shown in fig. 1d, a layer of semiconductor material 104 is deposited in this step to fill the recess and cover the insulating layer.
The layer of semiconductor material 104 may include silicon, but is not limited to this example.
The semiconductor material layer 104 may be formed by a Chemical Vapor Deposition (CVD) method, a Physical Vapor Deposition (PVD) method, a Low Pressure Chemical Vapor Deposition (LPCVD) method, or the like.
Specifically, in this embodiment, the semiconductor material layer 104 is formed by a Physical Vapor Deposition (PVD) method.
Optionally, a high temperature anneal is performed to form the layer of semiconductor material 104 into single crystal silicon, as shown in fig. 1e, which may be at a temperature of 700-1000 ℃, but is not limited to this temperature range. Can be adjusted as required.
Step 13 is performed to deposit a second dielectric layer 105 to cover the semiconductor material layer.
Specifically, as shown in fig. 1f, the second dielectric layer 105 may be an oxide, for example, the same material as the first dielectric layer.
Further, before depositing the second dielectric layer 105, a step of planarizing the semiconductor material layer may be further included to obtain a smoother surface, so as to further improve the performance of the prepared device.
Non-limiting examples of the planarization process include a mechanical planarization method and a chemical mechanical polishing planarization method, among others.
And step 14, patterning the second dielectric layer and the semiconductor material layer to remove the semiconductor material layer in the groove and expose the groove.
Specifically, as shown in fig. 1g, in this step, the size of the opening of the groove is 0.13-0.35 um, and the groove with this size is formed, so as to improve the filling performance in the subsequent groove filling process, thereby avoiding the occurrence of problems such as voids.
The groove is formed in the previous step 11, and the forming method may include: in this step, a mask layer having an opening, such as a photoresist layer, is formed on the first insulating layer, and then the first insulating layer, the first dielectric layer, and the semiconductor substrate are etched using the photoresist layer as a mask to form the groove.
Wherein the depth of the groove is not limited to a range of values.
Step 15 is performed to deposit a second insulating layer 106 to fill the recess and cover the second dielectric layer, the second insulating layer being a good conductor of heat.
Specifically, as shown in fig. 1h, the second insulating layer 106 is formed on the first dielectric layer, wherein the second insulating layer 106 includes a thermal insulating layer with a good conductor, and in the present invention, a material with high heat transfer efficiency may be selected, and a good insulating property is required, for example, a BN material layer may be selected, but is not limited to this example.
Optionally, the second insulating layer 106 and the first insulating layer are made of the same material, such as a BN material layer.
The second insulating layer 106 may be formed by a Chemical Vapor Deposition (CVD) method, a Physical Vapor Deposition (PVD) method, a Low Pressure Chemical Vapor Deposition (LPCVD) method, or the like.
Step 16 is performed to etch back the second insulating layer 106 to the first insulating layer.
Specifically, as shown in fig. 1i, the second insulating layer is etched back to the first insulating layer with plasma including Cl in this step.
Wherein, the pressure of the Cl plasma treatment can be 50-200mTorr, the power is 200-.
Step 17 is performed to remove the second dielectric layer.
Specifically, as shown in fig. 1i, the second insulating layer is etched back to the first insulating layer with plasma including F in this step.
Wherein, the pressure of the F plasma treatment can be 50-200mTorr, the power is 200-.
Step 18 is performed to continue depositing the semiconductor material layer and annealing to fill the recess above the second insulating layer.
As shown in fig. 1j, the layer of semiconductor material may include silicon, but is not limited to this example.
Wherein the semiconductor material layer may be formed by a Chemical Vapor Deposition (CVD) method, a Physical Vapor Deposition (PVD) method, a Low Pressure Chemical Vapor Deposition (LPCVD) method, or the like.
Specifically, in this embodiment, the semiconductor material layer is formed by a Physical Vapor Deposition (PVD) method.
Optionally, a high temperature anneal is performed to form single crystal silicon from the layer of semiconductor material, as shown in fig. 1k, which may be at a temperature of 700 c to 1000 c, but is not limited to this temperature range. Can be adjusted as required.
Step 19 is performed to pattern the layer of semiconductor material to form the fins 107 on the second insulating layer.
Specifically, as shown in fig. 1l, in this step, a plurality of fins are formed in the semiconductor material layer in this step, the widths of the fins are all the same, or the fins are divided into a plurality of fin groups having different widths.
The specific forming method comprises the following steps: forming a hard mask layer (not shown) on the semiconductor material layer, wherein the hard mask layer can be formed by using various suitable processes familiar to those skilled in the art, such as a chemical vapor deposition process, and the hard mask layer can be a bottom-up stacked oxide layer and a silicon nitride layer; patterning the hard mask layer, forming a plurality of mutually isolated masks for etching the layer of semiconductor material to form fins thereon, in one embodiment, the patterning is performed using a self-aligned double pattern (SADP) process; the layer of semiconductor material is etched to form fin structures thereon.
Thus, the description of the manufacturing process of the semiconductor device of the embodiment of the present invention is completed. After the above steps, other related steps may also be included, such as forming a gate structure on the fin, which is not described herein again. Besides the above steps, the preparation method of this embodiment may further include other steps among the above steps or between different steps, and these steps may be implemented by various processes in the prior art, and are not described herein again.
In order to solve the problems in the prior art, the invention provides a preparation method of a semiconductor device, wherein an insulating layer with good heat conducting property is formed on a semiconductor substrate, and then a fin is formed on the insulating layer, the insulating layer not only can play an insulating role, but also can well conduct heat generated by the device, so that the bottom self-heating effect of the device is avoided, and the performance and the yield of the semiconductor device are improved.
Example two
The invention also provides a semiconductor device prepared according to the method of the first embodiment, the semiconductor device comprising:
a semiconductor substrate;
an insulating layer over the semiconductor substrate to cover the semiconductor substrate, wherein the insulating layer includes a good conductor of heat;
a fin on the good thermal conductor.
The insulating layer of the good thermal conductor in the present invention may be selected from those materials having high heat transfer efficiency and required to have good insulating properties, for example, a BN material layer may be selected, but is not limited to this example.
The first insulating layer (good thermal conductor) can be made of a material with high heat transfer efficiency, can quickly absorb and conduct heat generated by the fins, and needs to have good insulating performance.
Wherein, the semiconductor substrate selects Si as a substrate for forming a BN material layer in the FINFET device.
Optionally, the semiconductor material layer is made of Si, and the semiconductor material layer may be subjected to high-temperature annealing under the action of the silicon substrate to form single crystal silicon.
Further, the semiconductor material layer may be formed by a PVD process.
According to the semiconductor device, the insulating layer with good heat conducting property is formed on the semiconductor substrate, the fins are formed on the insulating layer, the insulating layer can play an insulating role, heat generated by the device can be conducted well, the bottom self-heating effect of the device is avoided, and the performance and yield of the semiconductor device are improved.
EXAMPLE III
The invention also provides an electronic device comprising the semiconductor device of the second embodiment, which is prepared by the method of the first embodiment.
The electronic device of this embodiment may be any electronic product or device, such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a recording pen, an MP3, an MP4, a PSP, and the like, and may also be any intermediate product including a circuit. The electronic device of the embodiment of the invention has better performance due to the use of the circuit.
Wherein figure 2 shows an example of a mobile telephone handset. The mobile phone handset 200 is provided with a display portion 202, operation buttons 203, an external connection port 204, a speaker 205, a microphone 206, and the like, which are included in a housing 201.
The mobile phone comprises the semiconductor device of the first embodiment, wherein an insulating layer with good heat conducting property is formed on the semiconductor substrate in the semiconductor device, fins are formed on the insulating layer, and the insulating layer not only can play an insulating role, but also can conduct heat generated by the device well, so that the bottom self-heating effect of the device is avoided, and the performance and the yield of the semiconductor device are improved.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims (11)

1. A semiconductor device, characterized in that the semiconductor device comprises:
a semiconductor substrate;
the semiconductor device comprises a semiconductor substrate, an insulating layer and a plurality of insulating layers, wherein the insulating layer is positioned above the semiconductor substrate so as to cover the semiconductor substrate, the insulating layer comprises a good thermal conductor and comprises a horizontal part and a vertical part, the horizontal part is positioned above the semiconductor substrate, the vertical parts are of cylindrical structures and are inserted into the semiconductor substrate at intervals, and one end of each vertical part is connected with the horizontal part;
and the fin is positioned on the insulating layer.
2. The semiconductor device according to claim 1, wherein the insulating layer comprises a boron nitride layer.
3. A method of fabricating a semiconductor device, the method comprising:
providing a semiconductor substrate, forming an insulating layer of a good thermal conductor on the semiconductor substrate to cover the semiconductor substrate, wherein the insulating layer comprises a horizontal part and a vertical part, the horizontal part is positioned above the semiconductor substrate, the vertical parts are of cylindrical structures and are inserted into the semiconductor substrate at intervals, and one end of each vertical part is connected with the horizontal part;
forming a semiconductor material layer on the insulating layer of the good thermal conductor to cover the insulating layer;
and patterning the semiconductor material layer to form a fin.
4. The method of claim 3, wherein the insulating layer of good thermal conductor comprises a layer of boron nitride.
5. The method of claim 3, wherein the step of forming the insulating layer of good thermal conductor on the semiconductor substrate comprises:
providing a semiconductor substrate, and sequentially forming a first dielectric layer and a first insulating layer on the semiconductor substrate, wherein the first insulating layer is a good thermal conductor;
patterning the first insulating layer, the first dielectric layer and the semiconductor substrate to form a plurality of grooves spaced from each other;
depositing the semiconductor material layer to fill the groove and cover the insulating layer;
depositing a second dielectric layer to cover the semiconductor material layer;
patterning the second dielectric layer and the semiconductor material layer to remove the semiconductor material layer in the groove to expose the groove;
and depositing a second insulating layer to fill the groove and cover the second dielectric layer, wherein the second insulating layer is a good thermal conductor.
6. The method of claim 5, further comprising, after forming the second insulating layer:
etching back the second insulating layer to the first insulating layer;
removing the second dielectric layer;
continuing to deposit the semiconductor material layer and annealing to fill the groove above the second insulating layer;
patterning the semiconductor material layer to form the fin on the second insulating layer.
7. The method of claim 6, wherein the layer of semiconductor material is deposited using a PVD process.
8. The method of claim 6, wherein etching back the second insulating layer to the first insulating layer is performed using a plasma comprising chlorine.
9. The method of claim 6, wherein the second dielectric layer is removed using a plasma comprising fluorine.
10. The method of claim 5, wherein the groove has an opening size of 0.13um to 0.35 um.
11. An electronic device characterized in that the electronic device comprises the semiconductor device according to any one of claims 1 to 2.
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