CN108206216A - A kind of semiconductor devices and its manufacturing method and electronic device - Google Patents
A kind of semiconductor devices and its manufacturing method and electronic device Download PDFInfo
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- CN108206216A CN108206216A CN201611178075.4A CN201611178075A CN108206216A CN 108206216 A CN108206216 A CN 108206216A CN 201611178075 A CN201611178075 A CN 201611178075A CN 108206216 A CN108206216 A CN 108206216A
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- grid
- hard mask
- mask layer
- clearance wall
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 80
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 44
- 229910052751 metal Inorganic materials 0.000 claims abstract description 77
- 239000002184 metal Substances 0.000 claims abstract description 77
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 72
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 72
- 238000000034 method Methods 0.000 claims abstract description 71
- 239000000758 substrate Substances 0.000 claims abstract description 44
- 238000005530 etching Methods 0.000 claims abstract description 30
- 230000008569 process Effects 0.000 claims abstract description 24
- 238000000151 deposition Methods 0.000 claims abstract description 11
- 239000000463 material Substances 0.000 claims description 36
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 31
- 229920005591 polysilicon Polymers 0.000 claims description 27
- 229920002120 photoresistant polymer Polymers 0.000 claims description 21
- 125000006850 spacer group Chemical group 0.000 claims description 14
- 239000011248 coating agent Substances 0.000 claims description 12
- 238000000576 coating method Methods 0.000 claims description 12
- 150000004767 nitrides Chemical class 0.000 claims description 12
- 238000006243 chemical reaction Methods 0.000 claims description 5
- 150000001875 compounds Chemical class 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 19
- 230000004888 barrier function Effects 0.000 abstract description 15
- 230000008901 benefit Effects 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 229910052710 silicon Inorganic materials 0.000 description 12
- 239000010703 silicon Substances 0.000 description 12
- 239000012212 insulator Substances 0.000 description 10
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- 239000000377 silicon dioxide Substances 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 7
- 238000001020 plasma etching Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 6
- 239000007789 gas Substances 0.000 description 6
- 238000001259 photo etching Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 239000000243 solution Substances 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 229910003978 SiClx Inorganic materials 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- 238000010884 ion-beam technique Methods 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 229910004541 SiN Inorganic materials 0.000 description 2
- 229910020177 SiOF Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000000608 laser ablation Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910003465 moissanite Inorganic materials 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- -1 one or more of SiCN Inorganic materials 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 239000012495 reaction gas Substances 0.000 description 2
- 238000009717 reactive processing Methods 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- VLJQDHDVZJXNQL-UHFFFAOYSA-N 4-methyl-n-(oxomethylidene)benzenesulfonamide Chemical compound CC1=CC=C(S(=O)(=O)N=C=O)C=C1 VLJQDHDVZJXNQL-UHFFFAOYSA-N 0.000 description 1
- 229910019001 CoSi Inorganic materials 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910005883 NiSi Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- SKYGTJFKXUWZMD-UHFFFAOYSA-N ac1l2n4h Chemical compound [Co].[Co] SKYGTJFKXUWZMD-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000001174 ascending effect Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000031709 bromination Effects 0.000 description 1
- 238000005893 bromination reaction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 150000002148 esters Chemical class 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
- 229910052753 mercury Inorganic materials 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- UPIXZLGONUBZLK-UHFFFAOYSA-N platinum Chemical compound [Pt].[Pt] UPIXZLGONUBZLK-UHFFFAOYSA-N 0.000 description 1
- 229910021340 platinum monosilicide Inorganic materials 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- RMAQACBXLXPBSY-UHFFFAOYSA-N silicic acid Chemical compound O[Si](O)(O)O RMAQACBXLXPBSY-UHFFFAOYSA-N 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention provides a kind of semiconductor devices and its manufacturing method and electronic device, is related to technical field of semiconductors.Including：Semiconductor substrate is provided, grid is formed on the semiconductor substrate, hard mask layer is formed on the grid；Clearance wall is formed, to cover the top surface of the hard mask layer and the side wall of the hard mask layer and the grid；Metal silicide layer is formed on the surface of the clearance wall.The manufacturing method of the present invention has the following advantages：1) due to the provision of new clearance wall profile, which is conducive to the formation of metal silicide layer, therefore the metal silicide layer formed has better quality；2) due to without using silicide barrier layer (process for depositing and etching including silicide barrier layer), therefore reducing production cost and time production cycle；3) due to having thicker dielectric layer between the metal silicide layer of formation and grid, the crosstalk between metal silicide layer and grid can be reduced, improves device performance.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and its manufacturing method and electronics
Device.
Background technology
Compared with the generic logic device manufacturing technology of same process node, mature technology enhancing (Matured
Technology Enhancement, abbreviation MTE) technique can realize twice of gate densities, and it uses a special gold
Belong to layer M0 as connection structure to reduce device size.Metal layer M0 depositions after clearance wall etching are formed, and be profit
With self-aligned silicide formation process, will be deposited on polysilicon layer reaction on the hard mask layer top surface and surface of clearance wall into
Metal silicide layer also needs to be formed patterned as metal layer M0, the process when carrying out self-aligned silicide formation process
Silicide barrier layer (SAB) covers the region for not needing to be formed metal silicide, therefore process complex steps are cumbersome, into
This high period is long, and in this way since the influence of clearance wall profile causes positioned at the side wall upper part subregion of clearance wall
Metal silicide formation it is of poor quality, and then influence device performance.
Therefore, it is necessary to a kind of manufacturing method of new semiconductor devices is proposed, to solve above-mentioned technical problem.
Invention content
A series of concept of reduced forms is introduced in Summary, this will in specific embodiment part into
One step is described in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection domain for attempting to determine technical solution claimed more.
In view of the deficiencies of the prior art, a kind of manufacturing method of semiconductor devices is provided in the embodiment of the present invention one, it is described
Method includes：
Semiconductor substrate is provided, grid is formed on the semiconductor substrate, hard mask is formed on the grid
Layer；
Clearance wall is formed, to cover the top surface of the hard mask layer and the side wall of the hard mask layer and the grid；
Metal silicide layer is formed on the surface of the clearance wall.
Further, the step of forming the clearance wall includes procedure below：
Spacer material layer is deposited, to cover the hard mask layer, the grid and the Semiconductor substrate；
Patterned photoresist layer is formed, to cover the part gap wall material of the hard mask layer top and both sides
The bed of material；
Using the patterned photoresist layer as mask, the etching removal part spacer material layer, with described in formation
Clearance wall.
Further, the step of forming the metal silicide layer includes procedure below：
Polysilicon layer is formed on the surface of the clearance wall；
Deposited metal layer, to cover the polysilicon layer；
Thermal annealing is carried out, the partial reaction that the metal layer is contacted with the polysilicon layer is made to form the metal silicide
Layer.
Further, the step of forming the grid includes procedure below：
It is sequentially depositing grid layer and hard mask layer on the semiconductor substrate；
Patterned photoresist layer is formed on the hard mask layer；
Using the patterned photoresist layer as hard mask layer described in mask etching；
Using the hard mask layer as grid layer described in mask etching, to form the grid.
Further, the hard mask layer includes the oxide skin(coating) and nitride layer that are laminated from bottom to top.
Further, the material of the grid includes polysilicon.
The embodiment of the present invention two provides a kind of semiconductor devices prepared using aforementioned method, including：
Semiconductor substrate is formed with grid on the semiconductor substrate, and hard mask layer is formed on the grid；
Clearance wall is formed on the top surface of the hard mask layer and the side wall of the hard mask layer and the grid；
Metal silicide layer is formed on the surface of the clearance wall.
Further, the hard mask layer includes the oxide skin(coating) and nitride layer that are laminated from bottom to top.
Further, the clearance wall also further extends into the surface of the part Semiconductor substrate on the outside of the grid
On.
The embodiment of the present invention three provides a kind of electronic device, and the electronic device includes aforementioned semiconductor devices.
The manufacturing method of the present invention forms the top surface for covering the hard mask layer and grid and the clearance wall of side wall substitutes now
Some is formed only in the clearance wall on gate lateral wall, and metal silicide layer M0, and this are then formed on the surface of clearance wall
The manufacturing method of invention is without using silicide barrier layer, and therefore, the manufacturing method of the present invention has the following advantages：
1) due to the provision of new clearance wall profile, which is conducive to the formation of metal silicide layer, therefore formed
Metal silicide layer has better quality；
2) due to without using silicide barrier layer (process for depositing and etching including silicide barrier layer), therefore reducing
Production cost and time production cycle；
3) due to having thicker dielectric layer between the metal silicide layer of formation and grid, metal silicide can be reduced
Crosstalk between layer and grid improves device performance.
The semiconductor devices of the present invention, as a result of above-mentioned manufacturing method, thus equally has the advantages that above-mentioned.The present invention
Electronic device, as a result of above-mentioned semiconductor device, thus equally have the advantages that above-mentioned.
Description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Figure 1A to Fig. 1 E shows the knot of device that the correlation step that existing MTE techniques prepare semiconductor devices is obtained
Structure schematic diagram；
Fig. 2A-Fig. 2 E show that the correlation step of the manufacturing method of the semiconductor devices of one embodiment of the present invention is obtained
The structure diagram of the device obtained；
Fig. 3 shows the process flow chart of the manufacturing method of the semiconductor devices of one embodiment of the present invention.
Fig. 4 shows the schematic diagram of the electronic device in one embodiment of the invention.
Specific embodiment
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.Disclosure will be made thoroughly and complete, and will fully convey the scope of the invention on the contrary, providing these embodiments
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated.From beginning to end
Same reference numerals represent identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer or
Person may have element or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or during layer, then there is no elements or layer between two parties.It should be understood that although it can make
Various elements, component, area, floor and/or part are described with term first, second, third, etc., these elements, component, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish an element, component, area, floor or part with it is another
One element, component, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and be used so as to describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that other than orientation shown in figure, spatial relationship term intention, which further includes, to be made
With the different orientation with the device in operation.For example, if the device overturning in attached drawing, then, is described as " under other elements
Face " or " under it " or " under it " elements or features will be oriented to other elements or features " on ".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
Number, step, operation, the presence of element and/or component, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, component and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
It describes to send out herein with reference to the cross-sectional view of the schematic diagram of the desirable embodiment (and intermediate structure) as the present invention
Bright embodiment.As a result, it is contemplated that due to caused by such as manufacturing technology and/or tolerance from the variation of shown shape.Therefore,
The embodiment of the present invention should not necessarily be limited to the specific shape in area shown here, but including due to for example manufacturing caused shape
Shape deviation.For example, it is shown as the injection region of rectangle usually has circle at its edge or bending features and/or implantation concentration ladder
Degree rather than the binary from injection region to non-injection regions change.Equally, the disposal area can be led to by injecting the disposal area formed
Some injections in area between the surface passed through during injection progress.Therefore, the area shown in figure is substantially schematic
, their shape is not intended the true form in the area of display device and is not intended to limit the scope of the present invention.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description, to illustrate this
Invent the technical solution proposed.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, this hair
It is bright to have other embodiment.
In the following, be briefly described with reference to figure 1A- Fig. 1 E correlation steps for preparing semiconductor devices to existing MTE techniques,
Wherein, Figure 1A to Fig. 1 E shows the structure of device that the correlation step that existing MTE techniques prepare semiconductor devices is obtained
Schematic diagram.
First, as shown in Figure 1A, Semiconductor substrate is provided, is formed with polysilicon gate 101 on the semiconductor substrate,
Hard mask layer is formed on the polysilicon gate 101, which includes 102 He of silicon oxide layer being laminated from bottom to top
Silicon nitride layer 103.
Then, as shown in Figure 1B, spacer material layer 104a is deposited, covers the Semiconductor substrate and the silicon nitride
The material of 103, the spacer material layer 104a include oxide.
Then, as shown in Figure 1 C, etching removal is located on 103 surface of silicon nitride and positioned at semiconductor substrate surface
On the part spacer material layer, to form clearance wall 104, which is located at the grid and the oxygen of stacking
On the side wall of SiClx layer 102 and silicon nitride layer 103.
Then, as shown in figure iD, deposit polycrystalline silicon layer 105, covers the Semiconductor substrate, and using photoetching process and
The etching technics etching removal part polysilicon layer 105, retains positioned at the surface of the silicon nitride 103, the clearance wall 104
Surface and part semiconductor substrate surface the part polysilicon layer 105.
Then, deposit silicide barrier layer (SAB), and be patterned, to expose the polysilicon layer 105, cover
Lid does not need to carry out the region of silication technique for metal.
Then, as referring to figure 1E, self-aligned silicide formation process is carried out, for example, first described in the covering of deposited metal layer
Polysilicon layer 105, metal layer may include cobalt (cobalt).Then it is made annealing treatment, causes metal layer and the polysilicon under it
Silicification, metal silicide layer 106 thus formation occur for layer.Then using erodable metal layer, but will not attack metal silicon
The etching agent of compound layer region, unreacted metal layer is removed.
Since the polysilicon layer 105 being deposited on on 103 top surface of the silicon nitride layer and surface of clearance wall is reacted into metal
Silicide layer 106 is used as metal layer M0, which also needs to form patterned silicon when carrying out self-aligned silicide formation process
(SAB) covers the region for not needing to be formed metal silicide on compound barrier layer, therefore process complex steps are cumbersome, production
Of high cost, the period is long, and in this way since the influence of clearance wall profile leads to the side wall upper part point positioned at clearance wall
The formation of the metal silicide in region is of poor quality, and then influences the performance of device.
Embodiment one
In order to solve the above technical problem, the present invention provides a kind of manufacturing method of semiconductor devices, as shown in figure 3, its
It mainly includes the following steps that：
Step S1：Semiconductor substrate is provided, grid is formed on the semiconductor substrate, is formed on the grid
Hard mask layer；
Step S2：Clearance wall is formed, to cover the top surface of the hard mask layer and the hard mask layer and the grid
Side wall；
Step S3：Metal silicide layer is formed on the surface of the clearance wall.
The manufacturing method of the present invention forms the top surface for covering the hard mask layer and grid and the clearance wall of side wall substitutes now
Some is formed only in the clearance wall on gate lateral wall, and metal silicide layer M0, and this are then formed on the surface of clearance wall
The manufacturing method of invention is without using silicide barrier layer, and therefore, the manufacturing method of the present invention has the following advantages：
1) due to the provision of new clearance wall profile, which is conducive to the formation of metal silicide layer, therefore formed
Metal silicide layer has better quality；
2) due to without using silicide barrier layer (process for depositing and etching including silicide barrier layer), therefore reducing
Production cost and time production cycle；
3) due to having thicker dielectric layer between the metal silicide layer of formation and grid, metal silicide can be reduced
Crosstalk between layer and grid improves device performance.
In the following, the manufacturing method of the semiconductor devices of the present invention is described in detail with reference to figure 2A- Fig. 2 E, wherein, Fig. 2A-
Fig. 2 E show the knot for the device that the correlation step of the manufacturing method of the semiconductor devices of one embodiment of the present invention is obtained
Structure schematic diagram.
First, as shown in Figure 2 A, Semiconductor substrate (not shown) is provided, is formed with grid on the semiconductor substrate
201, it is formed with hard mask layer on the grid 201.
Specifically, the Semiconductor substrate can be at least one of following material being previously mentioned：Silicon, silicon-on-insulator
(SOI), silicon (SSOI) is laminated on insulator, SiGe (S-SiGeOI), germanium on insulator SiClx are laminated on insulator
(SiGeOI) and germanium on insulator (GeOI) etc..As an example, in the present embodiment, the constituent material of Semiconductor substrate is selected
Monocrystalline silicon.
Wherein, the structures such as shallow trench isolation (STI), well region can also be formed in Semiconductor substrate, herein and without
It limits.
In one example, the method for forming the grid 201 and the hard mask layer includes the following steps A1 to step
A4：
First, step A1 is carried out, is sequentially depositing grid layer and hard mask layer on the semiconductor substrate.
In one embodiment, grid layer is made of polycrystalline silicon material, and metal, metal nitride, metal generally can also be used
The material of silicide or similar compound as grid layer.Grid layer preferably forms method and includes chemical vapour deposition technique
(CVD), such as low temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition
(LTCVD), plasma activated chemical vapour deposition (PECVD), it is possible to use general such as sputter and physical vapour deposition (PVD) (PVD)
Similar method.The thickness of grid layer can carry out reasonable set according to the size of practical devices and be not specifically limited herein.
Wherein it is possible to using any suitable hard mask material well known to those skilled in the art as hard mask layer, example
As hard mask layer can include SiO2, one or more of SiCN, SiN, SiC, SiOF, SiON, in the present embodiment, preferably
Ground, the hard mask layer include the oxide skin(coating) 202 being laminated from bottom to top and nitride layer 203, wherein, oxide skin(coating) 202 can
To use high-temperature oxide (HTO), oxide skin(coating) 202 can specifically include silica, and the material of nitride layer 203 includes nitridation
Silicon.It can use the methods of chemical vapor deposition method and physical gas-phase deposite method and form the hard mask layer, thickness can
With according to actual process reasonable set.
Then, step A2 is carried out, patterned photoresist layer is formed on the hard mask layer.It can spin coating photoresist first
Layer recycles photoetching process (such as exposed and developed and etc.) to carry out pattern to photoresist layer in the Semiconductor substrate
Change, to form the patterned photoresist layer, which defines the pattern of the grid of predetermined formation.
Then, step A3 is carried out, using the patterned photoresist layer as hard mask layer described in mask etching.It can use
Dry etching etches the hard mask layer, to be patterned to hard mask layer.It can also be by the method for ashing by the photoetching
Glue-line removes.
Finally, step A4 is carried out, using the hard mask layer as grid layer described in mask etching, to form the grid 201.
The methods of dry etching or wet etching can be used carries out above-mentioned etching, wherein, dry etch process can be
The arbitrary combination of reactive ion etching, ion beam etching, plasma etching, laser ablation or these methods.It can also use
Single lithographic method can also use more than one lithographic method.
Also optionally, after the grid 201 is formed, a prewashing (pre-clean) processing procedure is implemented, it is miscellaneous to remove
Matter.This prewashing processing procedure may be reactive (reactive) or non-reacted (non-reactive) prewashing processing procedure.For example,
Reactive processing procedure be, for example, using hydrogeneous plasma (hydrogen-containing plasma) a plasma processing rather than
Reactive processing procedure is, for example, using the plasma processing containing argon plasma (argon-containing).
Illustratively, after prewashing (pre-clean) processing procedure, also optionally grid 201 is reoxidized with shape
Into thin oxide skin(coating) (not shown), any suitable oxidation technology well known to those skilled in the art can be used, herein not
It repeats.
Then, as shown in Figure 2 B, deposit spacer material layer 204a, with cover the hard mask layer, the grid 201 with
And the Semiconductor substrate.
Specifically, spacer material layer 204a can be a kind of in silica, silicon nitride, silicon oxynitride or they are combined
It forms.As an optimal enforcement mode of the present embodiment, the spacer material layer 204a is silica, such as positive silicic acid second
Ester (TEOS) oxide with teos solution (TEOS) for base stock, uses plasma enhanced chemical vapor deposition
Method silicon oxide deposition (PETEOS) also optionally carries out prerinse step, to remove in Semiconductor substrate before deposition
Impurity.
Then, as shown in Figure 2 C, patterned photoresist layer 205 is formed, to cover the hard mask layer top and two
The part spacer material layer 204a of side.
Specifically, can spin coating photoresist layer 205 first in the Semiconductor substrate, photoetching process is recycled (such as to expose
Light and development) photoresist layer 205 is patterned, to form the patterned photoresist layer 205, cover institute
The part spacer material layer 204a of hard mask layer top and both sides is stated, which defines pre-
The pattern for the clearance wall being shaped as.
Then, as shown in Figure 2 D, using the patterned photoresist layer as mask, the etching removal part gap wall material
The bed of material, to form the clearance wall 204, wherein the clearance wall 204 formed covers the top surface of the hard mask layer and covering institute
The side wall of hard mask layer and grid 201 is stated, on the surface for the part semiconductor substrate that can also extend further into outside.
Etching in this step can use dry etching or wet etching, traditional deep dry etch process, for example, react from
The arbitrary combination of sub- etching, ion beam etching, plasma etching, laser ablation or these methods.Single quarter can be used
Etching method can also use more than one lithographic method.
In the present embodiment, existing clearance wall is substituted using to spacer material layer progress lithography and etching technical process
Self-aligned etching technique, the clearance wall of formation not only cover the side wall of the hard mask layer and grid 201, also cover and described cover firmly
The top surface of film layer.
Finally, the method that ashing can be used removes the patterned photoresist layer 205.
Then, continue as shown in Figure 2 D, to form polysilicon layer 206 on the surface of the clearance wall 204.
Specifically, Semiconductor substrate can be covered by deposit polycrystalline silicon layer 206 first, photoetching process is recycled to be formed patterned
Photoresist layer, covers the predetermined polysilicon layer retained, then using patterned photoresist layer for mask etch removal clearance wall 204 with
Outer polysilicon layer only retains the polysilicon layer 206 being located on 204 surface of clearance wall, finally, removes patterned photoetching
Glue-line.
Illustratively, low-pressure chemical vapor phase deposition (LPCVD) technique can be selected in the forming method of polysilicon layer 206.It is formed
The process conditions of the polysilicon include：Reaction gas is silane (SiH4), the range of flow of the silane can be 100~200
Cc/min (sccm), such as 150sccm；Temperature range can be 700~750 degrees Celsius in reaction chamber；React cavity pressure
Can be 250~350 millimetress of mercury (mTorr), such as 300mTorr；It may also include buffer gas in the reaction gas, it is described slow
Qi of chong channel ascending adversely body can be helium or nitrogen, and the range of flow of the helium and nitrogen can be 5~20 liters/min (slm), as 8slm,
10slm or 15slm.
Wet etching or dry etching may be used for the etching of polysilicon in this step.One in the present invention is specific real
It applies in example, dry etching execution may be used and be etched back to technique, dry method etch technology includes but not limited to：Reactive ion etching
(RIE), ion beam milling, plasma etching or laser cutting.For example, by using plasma etching, etching gas can be adopted
With based on oxygen (O2- based) gas.Wherein, the etching gas of dry etching can also be bromination hydrogen, carbon tetrafluoride
Gas or gas of nitrogen trifluoride.It should be noted that above-mentioned engraving method is only exemplary, it is not limited to this method,
Those skilled in the art can also select other common methods.
Wherein, polysilicon layer 206 can also be substituted by other siliceous semiconductor material layers.
Finally, as shown in Figure 2 E, metal silicide layer 207 is formed on the surface of the clearance wall 204.
The forming method of metal silicide layer 207 (silicide) includes the following steps：Deposited metal layer first is to cover
The polysilicon layer may include the material of nickel (nickel), cobalt (cobalt) and platinum (platinum) or combination.Then into
Row thermal annealing causes metal layer that silicification, the portion that the metal layer is made to be contacted with the polysilicon layer occurs with the silicon under it
Reaction is divided to form the metal silicide layer.Then using erodable metal layer, but will not attack metal silicide layer etching
Agent removes unreacted metal layer.
It need not carry out the deposition and etch step of silicide barrier layer, section again before metal silicide layer 207 is formed
Cost and time are saved.
In addition, being formed for metal silicide layer is more advantageous to by the profile of clearance wall 204 formed in this present embodiment, because
This metal silicide layer formed has better quality.
Wherein, the hard mask layer between grid 201 and metal silicide layer 207 is (including oxide skin(coating) 202 and nitride layer
203) clearance wall 204 and on hard mask layer top surface is as dielectric layer, and compared with prior art, the thickness of dielectric layer is thicker,
The crosstalk between metal silicide layer and grid can be reduced, improves device performance.
By above-mentioned steps, the simple introduction of the manufacturing method to semiconductor devices of the invention is completed, for complete
Device preparation the step of also needing other, this will not be repeated here.
The manufacturing method of the present invention forms the top surface for covering the hard mask layer and grid and the clearance wall of side wall substitutes now
Some is formed only in the clearance wall on gate lateral wall, and metal silicide layer M0, and this are then formed on the surface of clearance wall
The manufacturing method of invention is without using silicide barrier layer, and therefore, the manufacturing method of the present invention has the following advantages：
1) due to the provision of new clearance wall profile, which is conducive to the formation of metal silicide layer, therefore formed
Metal silicide layer has better quality；
2) due to without using silicide barrier layer (process for depositing and etching including silicide barrier layer), therefore reducing
Production cost and time production cycle；
3) due to having thicker dielectric layer between the metal silicide layer of formation and grid, metal silicide can be reduced
Crosstalk between layer and grid improves device performance.
Embodiment two
The present invention also provides a kind of semiconductor devices prepared using aforementioned manufacturing method.
As an example, as shown in Figure 2 E, semiconductor devices of the invention includes Semiconductor substrate (not shown).
Specifically, the Semiconductor substrate can be at least one of following material being previously mentioned：Silicon, silicon-on-insulator
(SOI), silicon (SSOI) is laminated on insulator, SiGe (S-SiGeOI), germanium on insulator SiClx are laminated on insulator
(SiGeOI) and germanium on insulator (GeOI) etc..As an example, in the present embodiment, the constituent material of Semiconductor substrate is selected
Monocrystalline silicon.
Wherein, the structures such as shallow trench isolation (STI), well region can also be formed in Semiconductor substrate, herein and without
It limits.
Further, it is formed with grid 201 on the semiconductor substrate, hard mask is formed on the grid 201
Layer.
In one embodiment, the material of grid 201 is made of polycrystalline silicon material, and metal, nitride metal generally can also be used
The material of object, metal silicide or similar compound as grid.The thickness of grid can be carried out according to the size of practical devices
Reasonable set is not specifically limited herein.
Wherein it is possible to using any suitable hard mask material well known to those skilled in the art as hard mask layer, example
As hard mask layer can include SiO2, one or more of SiCN, SiN, SiC, SiOF, SiON, in the present embodiment, preferably
Ground, the hard mask layer include the oxide skin(coating) 202 being laminated from bottom to top and nitride layer 203, wherein, oxide skin(coating) 202 can
To use high-temperature oxide (HTO), oxide skin(coating) 202 can specifically include silica, and the material of nitride layer 203 includes nitridation
Silicon.
Further, the shape on the top surface of the hard mask layer and the side wall of the hard mask layer and the grid 201
Into there is clearance wall 204, on the surface for the part semiconductor substrate that can also extend further into 201 outside of grid.
The material of clearance wall 204 can be a kind of in silica, silicon nitride, silicon oxynitride or they combine and form.Make
For an optimal enforcement mode of the present embodiment, the clearance wall 204 is silica, such as ethyl orthosilicate (TEOS) aoxidizes
Object with teos solution (TEOS) for base stock, is deposited with plasma enhanced chemical vapor deposition method and aoxidized
Silicon (PETEOS).
Further, it is formed with metal silicide layer 207 on the surface of the clearance wall 204.
Wherein, metal silicide layer 207 is used as metal layer M0, as connection structure to reduce device size.
The material of metal silicide layer 207 depend on its specific formation process, for example, its can be NiSi, CoSi or
PtSi etc..
Wherein, the hard mask layer between grid 201 and metal silicide layer 207 is (including oxide skin(coating) 202 and nitride layer
203) clearance wall 204 and on hard mask layer top surface is as dielectric layer, and compared with prior art, the thickness of dielectric layer is thicker,
The crosstalk between metal silicide layer and grid can be reduced, improves device performance.
The semiconductor devices of the present invention as a result of the manufacturing method of previous embodiment one, thus equally has above-mentioned
Advantage.
Embodiment three
The present invention also provides a kind of electronic devices, including the semiconductor devices described in embodiment two or include the use of
Implement the prepared semiconductor devices obtained of manufacturing method described in one.
The electronic device of the present embodiment can be mobile phone, tablet computer, laptop, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, Digital Frame, camera, video camera, recording pen, MP3, MP4, PSP is set
Standby or any intermediate products including circuit.The electronic device of the embodiment of the present invention, due to the use of above-mentioned semiconductor
Device, thus with better performance.
Wherein, Fig. 4 shows the example of mobile phone handsets.Mobile phone handsets 400, which are equipped with, to be included in shell 401
Display portion 402, operation button 403, external connection port 404, loud speaker 405, microphone 406 etc..
Wherein described mobile phone handsets include the semiconductor devices described in embodiment two, and the semiconductor devices includes：
Semiconductor substrate is formed with grid on the semiconductor substrate, and hard mask layer is formed on the grid；
Clearance wall is formed on the top surface of the hard mask layer and the side wall of the hard mask layer and the grid；
Metal silicide layer is formed on the surface of the clearance wall.
The electronic device of the embodiment of the present invention, due to the use of above-mentioned semiconductor devices, thus with better performance.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in the range of described embodiment.In addition people in the art
It is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of member
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (10)
1. a kind of manufacturing method of semiconductor devices, which is characterized in that the method includes：
Semiconductor substrate is provided, grid is formed on the semiconductor substrate, hard mask layer is formed on the grid；
Clearance wall is formed, to cover the top surface of the hard mask layer and the side wall of the hard mask layer and the grid；
Metal silicide layer is formed on the surface of the clearance wall.
2. manufacturing method as described in claim 1, which is characterized in that the step of forming the clearance wall includes procedure below：
Spacer material layer is deposited, to cover the hard mask layer, the grid and the Semiconductor substrate；
Patterned photoresist layer is formed, to cover the part spacer material of the hard mask layer top and both sides
Layer；
Using the patterned photoresist layer as mask, the etching removal part spacer material layer, to form the gap
Wall.
3. manufacturing method as described in claim 1, which is characterized in that the step of forming the metal silicide layer includes following
Process：
Polysilicon layer is formed on the surface of the clearance wall；
Deposited metal layer, to cover the polysilicon layer；
Thermal annealing is carried out, the partial reaction that the metal layer is contacted with the polysilicon layer is made to form the metal silicide layer.
4. manufacturing method as described in claim 1, which is characterized in that the step of forming the grid includes procedure below：
It is sequentially depositing grid layer and hard mask layer on the semiconductor substrate；
Patterned photoresist layer is formed on the hard mask layer；
Using the patterned photoresist layer as hard mask layer described in mask etching；
Using the hard mask layer as grid layer described in mask etching, to form the grid.
5. manufacturing method as described in claim 1 or 4, which is characterized in that the hard mask layer includes what is be laminated from bottom to top
Oxide skin(coating) and nitride layer.
6. manufacturing method as described in claim 1, which is characterized in that the material of the grid includes polysilicon.
7. a kind of semiconductor devices that method using described in one of claim 1 to 6 prepares, which is characterized in that including：
Semiconductor substrate is formed with grid on the semiconductor substrate, and hard mask layer is formed on the grid；
Clearance wall is formed on the top surface of the hard mask layer and the side wall of the hard mask layer and the grid；
Metal silicide layer is formed on the surface of the clearance wall.
8. semiconductor devices as claimed in claim 7, which is characterized in that the hard mask layer includes the oxygen being laminated from bottom to top
Compound layer and nitride layer.
9. semiconductor devices as claimed in claim 7, which is characterized in that the clearance wall also further extends into the grid
On the surface of the part Semiconductor substrate in outside.
10. a kind of electronic device, which is characterized in that the electronic device includes the semiconductor device described in one of claim 7 to 9
Part.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6081016A (en) * | 1998-03-31 | 2000-06-27 | Seiko Epson Corporation | CMOS device with improved wiring density |
| US6555455B1 (en) * | 1998-09-03 | 2003-04-29 | Micron Technology, Inc. | Methods of passivating an oxide surface subjected to a conductive material anneal |
| JP2010219541A (en) * | 2010-04-20 | 2010-09-30 | Renesas Electronics Corp | Semiconductor device and method of manufacturing the same |
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2016
- 2016-12-19 CN CN201611178075.4A patent/CN108206216B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6081016A (en) * | 1998-03-31 | 2000-06-27 | Seiko Epson Corporation | CMOS device with improved wiring density |
| US6555455B1 (en) * | 1998-09-03 | 2003-04-29 | Micron Technology, Inc. | Methods of passivating an oxide surface subjected to a conductive material anneal |
| JP2010219541A (en) * | 2010-04-20 | 2010-09-30 | Renesas Electronics Corp | Semiconductor device and method of manufacturing the same |
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