CN108075010A - 平面雪崩光电二极管 - Google Patents

平面雪崩光电二极管 Download PDF

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CN108075010A
CN108075010A CN201711451881.9A CN201711451881A CN108075010A CN 108075010 A CN108075010 A CN 108075010A CN 201711451881 A CN201711451881 A CN 201711451881A CN 108075010 A CN108075010 A CN 108075010A
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巴里·莱维尼
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Abstract

一种平面雪崩光电二极管,包括:第一半导体层、倍增层、电荷控制层、第二半导体层、梯度吸收层、阻挡层以及第二接触层。倍增层位于电荷控制层和第一半导体层之间。电荷控制层位于第二半导体层和倍增层之间。第二半导体层位于电荷控制层和梯度吸收层之间。梯度吸收层位于第二半导体层和阻挡层之间。

Description

平面雪崩光电二极管
本申请是申请日为2013年5月17日、申请号为201380025871.2、发明名称为“平面雪崩光电二极管”的中国发明专利申请的分案申请。
相关申请的交叉引用
本申请要求美国临时专利申请61/648,401的优先权,其全部内容通过引用并入本文。
背景技术
本发明涉及一种光电探测器。更具体地,本发明涉及一种雪崩光电二极管(“APD”)。
归因于已知的光子和电子之间的相互作用,近年来在光电探测器领域取得了进展,特别是在那些利用半导体材料的光电探测器方面。被称为雪崩光电二极管的一种基于半导体的光电探测器包括满足不同目的(例如吸收和倍增)的多种半导体材料。
雪崩光电二极管结构通过受激电荷载流子的作用来提供高增益,该受激电荷载流子在倍增层产生大量电子-空穴对。为了防止吸收层中的隧穿,在雪崩光电二极管自身内电场被调整,使得倍增层中的电场显著高于吸收层中的电场。
被称为台面(mesa)雪崩光电二极管的特定类型的雪崩光电二极管暴露高场p-n结和大量暴露的表面和界面态,其使得难于使用绝缘材料层来进行钝化。因此,常规的InP/InGaAs雪崩光电二极管采用掩埋p-n结的扩散结构(diffused structure)。然而,这些InP雪崩光电二极管需要对p型半导体区域的深度和扩散浓度两者的非常精确的扩散控制以及对发生该扩散的n掺杂区域的精确控制。该严格的掺杂控制是重要的,因为扩散控制p-n结的布局、倍增区域中电场的幅度、雪崩区域的长度以及电荷控制层中的总电荷,该总电荷决定高场InP雪崩区域和低场InGaAs吸收区域两者的电场值,高场InP雪崩区域的电场值必须足够大以产生倍增,低场InGaAs吸收区域的电场值必须足够小以避免隧穿。此外,在这种布置中使用精确放置的扩散的或注入的保护环,以避免在扩散的p-n结的边缘处的雪崩击穿。保护环和严格控制的扩散的这种组合增加电容、降低带宽并减少成品率,因而增加这些APD的成本。
对于超高速性能探测器,InAlAs可替代InP被用作雪崩层,因为更高的带隙减少隧穿,因而允许使用更薄的雪崩区域以产生更高的速度和更高性能的接收机。然而,在InAlAs中,获得扩散结构甚至更困难,因为和标准的基于InP的APD相比,(相对于空穴)更大的电子雪崩系数使得期望倍增电子而不是空穴。此外,因为n-掺杂剂的扩散不够快,所以简单地使标准的p-掺杂扩散结构反转是不足够的。
发明内容
为了克服现有技术的缺陷,申请人已经发现由于PIN探测器可以很容易地通过适当的表面预处理而被钝化和被BCB覆盖,因此在大面积未掺杂InGaAs吸收层的顶部刻蚀小面积p+InGaAs吸收区域,并像PIN一样用BCB钝化该小面积p+InGaAs吸收区域。
一种雪崩光电二极管包括第一半导体层、倍增层、电荷控制层、第二半导体层、梯度吸收(graded obsorption)层以及阻挡层。倍增层位于第一半导体层和电荷控制层之间。第二半导体层位于电荷控制层和梯度吸收层之间。阻挡层定位为与梯度吸收层相邻、与第二半导体层相对。
在另一个实施例中,可以刻蚀梯度吸收层以在第二半导体层的顶部获得小面积吸收区域。雪崩二极管也可以包括与第一半导体层相邻的第一接触部和与第二半导体层的顶部上的小面积吸收区域相邻的第二接触部。此外,可以采用如BCB的钝化结构来对雪崩光电二极管的一部分进行钝化。
在参考附属于本说明书并形成本说明书的一部分的附图和权利要求书仔细研究下述描述之后,本发明进一步的目标、特征和优点对本领域技术人员将变得清楚。
附图说明
图1是根据本发明的平面雪崩光电二极管的截面图;以及
图2是根据本发明的替代的平面雪崩光电二极管的截面图。
具体实施方式
美国专利号7,348,608(其全部内容通过引用并入本文)包含多项创新,包括:倍增层被掩埋在吸收层之下;由于在小的迷你台面下电场的集中,p+电荷控制层延伸穿过整个大的外部台面但不增加在工作偏置下的电容或降低工作偏置处的带宽;吸收层生长于电荷控制层之上以及倍增层之上;所有这些层具有外部台面的完整大面积;以及小的顶部p+迷你台面决定有源面积(active area)和电容及带宽。
在美国专利号7,348,608(其全部内容通过引用并入本文)中,InGaAs吸收层未掺杂从而在工作偏置下耗尽。电荷控制层和倍增层也在工作偏置下完全耗尽。由此,小的顶部p+迷你台面控制仅在该迷你台面正下方大的电场。由此,因为电容由小的迷你台面的面积决定,所以电容小。
穿过耗尽吸收层的电场收集电子和空穴,并决定它们的渡越时间,该渡越时间对穿过整个器件的总渡越时间做贡献,从而决定总响应速度。
美国专利号7,078,741(其全部内容通过引用并入本文)公开了在InGaAs吸收层中的梯度p+掺杂,以在不显著增加渡越时间或减小带宽的同时提高响应率。然而,因为这种p+掺杂层不会被耗尽并且大面积p+InGaAs层将与大n+底层一起引起大电容,所以该p+掺杂层不能简单地以与未掺杂InGaAs吸收层同样大的外部台面尺寸在现有的APD结构的顶部上生长。也就是说,为了具有低电容和高带宽,附加的p+层必须是和APD的有源区域相同的小尺寸。
参考图1,示出雪崩光电二极管10。作为其主要组件,雪崩光电二极管10包括第一半导体层12、倍增层14、电荷控制层16、数字梯度(digital grade)层18、第二半导体层20、梯度吸收层22以及阻挡层24。如图1所示,倍增层14位于电荷控制层16和第一半导体层12之间。数字梯度层18位于电荷控制层16和第二半导体层20之间。梯度吸收层22在第二半导体层20的顶部。阻挡层24在梯度吸收层22的顶部。
第一半导体层12可以是n型半导体并可以选自包括三元半导体的组或III-V族半导体。因此,第一半导体层12为来自III族的两种元素结合来自V族的一种元素,或反之,来自V族的两种元素结合来自III族的一种元素。下面示出周期表的代表性的族的表。
II族 III族 IV族 V族
锌(Zn) 铝(Al) 硅(Si) 磷(P)
镉(Cd) 镓(Ga) 锗(Ge) 砷(As)
汞(Hg) 铟(In) 锑(Sb)
在一些实施例中,第一半导体层12是InAlAs。然而,应当理解,第一半导体层12可以是为雪崩光电二极管10的优化操作提供带隙的任何二元或三元半导体。半导体倍增层14也可选自包括三元半导体的组或III-V族半导体。在优选实施例中,半导体倍增层14是InAlAs。
梯度吸收层22也选自包括三元半导体的组或III-V族半导体。在优选实施例中,梯度吸收层22是InGaAs。然而,应当理解,梯度吸收层22和半导体倍增层14两者都可以是为平面雪崩光电二极管10的优化操作提供带隙的任何二元或三元半导体。
第二半导体层20也可选自包括三元半导体的组或III-V族半导体。和前面一样,第二半导体层20为来自III族的两种元素结合来自V族的一种元素,或反之,来自V族的两种元素结合来自III族的一种元素。在优选实施例中,第二半导体层20为InAlAs。然而,应当理解,第二半导体层20可以是为雪崩光电二极管10的优化操作提供带隙的任何二元或三元半导体。
平面雪崩光电二极管10的特征是:所有关键的层厚度和掺杂浓度在初始晶体生长时被调整,从而处于控制下,使得它们可以可再生地生长且在整个晶片上是均匀的。因此,制造过程中与工艺控制相关的困难,尤其是关于扩散步骤的困难不明显。
参考图2示出雪崩光电二极管110的第二实施例。首先应当注意,相似的参考标号用于表示相似组件。例如,图2的第一半导体层112与图1的第一半导体层12类似。如图1中一样,雪崩光电二极管110包括第一半导体层112、倍增层114、电荷控制层116、数字梯度层118、第二半导体层120、梯度吸收层122以及阻挡层124。在该实施例中,雪崩光电二极管110已经被刻蚀。更具体地,已经刻蚀梯度吸收层122以在第二半导体层120的顶部上限定小面积吸收区域125。另外,雪崩光电二极管110包括与第一半导体层112相邻的第一接触部126和与阻挡层124相邻的第二接触部128。雪崩光电二极管110也可使至少一部分被钝化结构130钝化。该钝化结构可由BCB构成。
图1和图2示出电荷控制层16或116(可采用碳或Be作为p-掺杂剂来生长)延伸穿过整个隔离台面(isolation mesa)。无论在该隔离台面中p-n结的面积多大,高于穿通的电容不显著增加。发生这类情况是因为器件电容(在电荷穿通和耗尽之后)主要由小扩散区域(光电二极管10)或刻蚀的p+区域(光电二极管110)的面积而不是绝缘台面的面积来决定,由此形成低电容、高速APD。
上文描述的光电探测器可以被用作波导光电探测器或用作单个光子探测器。该光电探测器为了改进的光收集可以具有集成的透镜。
上述的和其他的实现在如下所述权利要求书的范围内。例如,所有n掺杂和p掺杂的半导体可以互换。即n掺杂和p掺杂可被反转以提供n型半导体的顶部迷你台面和p型半导体的下方接触。

Claims (9)

1.一种雪崩光电二极管,包括:
第一半导体层;
与所述第一半导体层相邻的倍增层;
与所述倍增层相邻、与所述第一半导体层相对的电荷控制层;
第二半导体层,所述第二半导体层是低掺杂的或非故意掺杂的,所述第二半导体层与所述电荷控制层相邻,其中所述第二半导体层在所述电荷控制层的与所述倍增层相对的一侧;
梯度吸收层,与所述第二半导体层相邻,其中所述梯度吸收层在所述第二半导体层的与所述第一半导体层相对的一侧,所述梯度吸收层是掺杂的并且与所述第二半导体层直接接触;以及
阻挡层,定位为与所述梯度吸收层相邻,其中所述阻挡层在所述梯度吸收层的与所述第二半导体层相对的一侧,所述阻挡层与所述梯度吸收层直接接触,并且
其中所述梯度吸收层被刻蚀以在与所述梯度吸收层直接接触的所述第二半导体层的顶部上限定小面积吸收区域,并且
所述梯度吸收层的截面宽度小于所述电荷控制层和倍增层的截面宽度,其中所述电荷控制层和倍增层的截面宽度基本相等。
2.如权利要求1所述的雪崩光电二极管,进一步包括位于所述电荷控制层和所述第二半导体层之间的数字梯度层。
3.如权利要求1所述的雪崩光电二极管,其中所述第一半导体层由磷化铟构成。
4.如权利要求1所述的雪崩光电二极管,其中所述倍增层由砷化铟铝构成。
5.如权利要求1所述的雪崩光电二极管,其中所述梯度吸收层由砷化铟镓构成。
6.如权利要求1所述的雪崩光电二极管,进一步包括与所述第一半导体层相邻的第一接触部。
7.如权利要求6所述的雪崩光电二极管,进一步包括与所述第二半导体层的顶部上的所述小面积吸收区域相邻的第二接触部。
8.如权利要求7所述的雪崩光电二极管,其中所述雪崩光电二极管的至少一部分被钝化结构钝化。
9.如权利要求8所述的雪崩光电二极管,其中所述钝化结构由苯并环丁烯构成。
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