CN108074916A - 具有重分布线结构的半导体封装件 - Google Patents

具有重分布线结构的半导体封装件 Download PDF

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Publication number
CN108074916A
CN108074916A CN201710218930.8A CN201710218930A CN108074916A CN 108074916 A CN108074916 A CN 108074916A CN 201710218930 A CN201710218930 A CN 201710218930A CN 108074916 A CN108074916 A CN 108074916A
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Prior art keywords
semiconductor chip
bond pad
redistribution
pad
wire bonding
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CN201710218930.8A
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CN108074916B (zh
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严柱日
李在薰
林相俊
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SK Hynix Inc
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Hynix Semiconductor Inc
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Abstract

具有重分布线结构的半导体封装件。一种半导体封装件可以包括具有位于第一有源表面上的第一接合焊盘的第一半导体芯片。该半导体封装件可以包括具有布置在第二有源表面上的第二接合焊盘的第二半导体芯片。所述第一半导体芯片和所述第二半导体芯片被堆叠成使得所述第一有源表面和所述第二有源表面彼此面对。

Description

具有重分布线结构的半导体封装件
技术领域
各种实施方式总体上可以涉及半导体封装件，并且更具体地，涉及包括重分布线结构的半导体封装件。
背景技术
如本领域中所公知的，当将存储器芯片安装至系统时，主要使用以下方法：以模块形式构造的存储器模块被安装至系统板的插座中。另外，因为系统需要高容量存储器，所以期望具有更高密度和更高速度特性的存储器模块。
在这方面，由于半导体集成技术的限制而致使难以制造具有所需容量的单个存储器芯片产品，所以当前使用了以下方法：多个存储器芯片被堆叠以创建高容量存储器。另外，为了制造高密度模块，制造了多个存储器芯片被嵌入在一个封装件中的MCP(多芯片封装)类型的封装件。
另外，重要的是减小安装在存储器模块中的封装件的电容负载，以确保系统的可靠的高速操作。
发明内容
在一个实施方式中，可以提供一种半导体封装件。该半导体封装件可以包括具有位于第一有源表面上的第一接合焊盘的第一半导体芯片。该半导体封装件可以包括具有被布置在第二有源表面上的第二接合焊盘的第二半导体芯片。所述第一半导体芯片和所述第二半导体芯片被堆叠成使得所述第一有源表面和所述第二有源表面彼此面对。
在一方面，提供了一种半导体封装件，该半导体封装件包括：第一半导体芯片，所述第一半导体芯片具有在第一有源表面的中间部分上布置成两排的第一接合焊盘；第二半导体芯片，所述第二半导体芯片具有与所述第一半导体芯片基本上相同的尺寸，并且具有在第二有源表面的中间部分上布置成两排的第二接合焊盘；重分布线，所述重分布线形成在所述第一有源表面上，并且具有与所述第一接合焊盘联接的重分布线焊盘和布线接合焊盘；以及凸块，所述凸块分别形成在所述第二半导体芯片的所述第二接合焊盘上，其中，所述第一接合焊盘和所述第二接合焊盘按照相同的焊盘布置结构来设置，其中，所述第一半导体芯片和所述第二半导体芯片被堆叠成使得所述第一有源表面和所述第二有源表面彼此面对，并且被设置成彼此偏移，并且其中，所述凸块被设置成分别与所述重分布线焊盘交叠。
在另一方面，提供了一种半导体封装件，该半导体封装件包括：第一半导体芯片，所述第一半导体芯片具有布置在所述第一半导体芯片的第一有源表面上的第一接合焊盘；第二半导体芯片，所述第二半导体芯片具有布置在所述第二半导体芯片的第二有源表面上的第二接合焊盘；重分布线，所述重分布线形成在所述第一有源表面上，并且具有与所述第一接合焊盘联接的重分布线焊盘和布线接合焊盘；以及凸块，所述凸块分别形成在所述第二半导体芯片的所述第二接合焊盘上，其中，所述第一接合焊盘和所述第二接合焊盘按照相同的焊盘布置结构来设置，其中，所述第一半导体芯片和所述第二半导体芯片被堆叠成使得所述第一有源表面和所述第二有源表面彼此面对，并且被设置成彼此偏移，并且其中，所述凸块被设置成分别与所述重分布线焊盘交叠。
附图说明
图1是例示DIMM(双列直插式存储器模块)和常规双管芯封装件的代表示例的视图。
图2是例示根据实施方式的半导体封装件的代表示例的截面图。
图3A是例示图2中例示的半导体封装件的第一半导体芯片的代表示例的平面图。
图3B是例示沿图3A中的线A-A’截取的截面图。
图4A是例示图2中例示的半导体封装件的第二半导体芯片的代表示例的平面图。
图4B是例示沿图4A中的线B-B’截取的截面图。
图5A、图5B、图6A、图6B、图7A和图7B是根据实施方式的帮助说明半导体封装件的特性的图的代表示例。
图8是例示根据实施方式的半导体封装件的代表示例的截面图。
图9是例示图8中例示的半导体封装件的第一半导体芯片和第二半导体芯片的代表示例的局部平面图。
图10是例示根据实施方式的半导体封装件的代表示例的截面图。
图11是例示可以应用根据各种实施方式的半导体封装件的电子系统的代表示例的框图。
图12是例示可以包括根据各种实施方式的半导体封装件的存储卡的代表示例的框图。
具体实施方式
在下文中，以下可以参照附图通过实施方式的各种示例来描述具有重分布线结构的堆叠型半导体封装件。
各种实施方式可以公开能够减小输入电容(Ci)的半导体封装件。另外，各种实施方式可以公开能够通过减小输入电容(Ci)来增大存储器模块的操作速度的半导体封装件。
在根据飞越(fly-by)拓扑的R-DIMM(注册的双列直插式存储器模块)中，存储控制器被设置在模块基板的中心部分处。存储控制器与设置在两侧上的存储器封装件串联联接，并且联接线的末端被联接至地以防止信号被反射和返回。
图1例示了R-DIMM当中的4列×4LR-DIMM(负载减小的DIMM)以及安装在DIMM中的存储器封装件。
参照图1，在DIMM 100中，RCD(寄存器时钟驱动器)20的左侧的10个存储器封装件30和RCD 20的右侧的8个存储器封装件30可以按照飞越拓扑被联接至作为存储控制器的RCD 20。虽然附图中没有例示，但由于存储器可以被安装至DIMM100的两个表面，所以可以总共安装36个存储器封装件30。在各个存储器封装件30是双管芯封装件的情况下，由于2个存储器芯片被包括在各个封装件中，所以总共72个存储器芯片可以被联接至RCD 20。
这种存储器模块的操作速度受到所安装的封装件的输入电容(Ci)的影响。因此，通过减小各个封装件的输入电容(Ci)，可以提高存储器模块的操作速度。
参照图1，参考符号1表示基板，3和5表示重分布线(RDL)，3a和5a表示重分布线绝缘层，7表示接合布线，8表示封装构件，9表示外部联接电极，10表示模块基板，并且40表示数据缓冲器。
参照图2，根据实施方式的半导体封装件200可以包括基板210、第一半导体芯片220和第二半导体芯片230。半导体封装件200还可以包括粘合剂240、接合布线250、封装构件260和外部联接电极270。
基板210可以是印刷电路板。基板210可以具有基本上四边形的板形状。基板210可以包括布置在顶表面210a上的多个接合指(bond finger)212a以及布置在底表面210b上的多个外部电极212b。在一个实施方式中，接合指212a可以被布置成与第一半导体芯片220的两个侧边缘相邻。基板210还可以包括按照使接合指212a和外部电极212b暴露的方式形成在顶表面210a和底表面210b上的阻焊剂214。
虽然没有例示，但基板210可以包括形成在其中的内部布线，并且接合指212a和外部电极212b可以通过内部布线彼此电联接。
第一半导体芯片220可以是存储器芯片。该存储器芯片可以包括，例如但不限于，DRAM芯片或NAND芯片。该存储器芯片可以包括其它类型的半导体存储器芯片中的任何一种。第一半导体芯片220可以具有基本上四边形的板形状。第一半导体芯片220可以具有第一有源表面220a和背向第一有源表面220a的第一背表面220b。第一半导体芯片220可以通过粘合剂240的媒介被设置在基板210的顶表面210a上，使得第一背表面220b面向基板210的顶表面210a。第一半导体芯片220可以包括被布置在第一有源表面220a上的多个第一接合焊盘222a和222b。第一接合焊盘222a和222b可以被布置在第一半导体芯片220的第一有源表面220a的中间部分上。第一半导体芯片220可以包括形成在第一有源表面220a上的多个重分布线224a和224b。
参照图3A和图3B，第一接合焊盘222a和222b可以被设置成在第一方向X上彼此分离，并且可以在第一半导体芯片220的第一有源表面220a的中间部分上沿着与第一方向X基本上垂直的第二方向Y被布置成两排。重分布线224a和224b可以包括布线接合焊盘224a-1和224b-1、重分布线焊盘224a-2和224b-2以及联接线224a-3和224b-3。
例如，为便于说明起见，将基于以下假设来进行下面的描述：在附图中，一侧指示左侧并且另一侧指示右侧。
重分布线224a和224b可以包括从中间部分延伸至第一半导体芯片220的第一有源表面220a的一侧边缘部分的第一重分布线224a以及从中间部分延伸至第一半导体芯片220的第一有源表面220a的另一侧边缘部分的第二重分布线224b。
各个第一重分布线224a可以包括第一布线接合焊盘224a-1、第一重分布线焊盘224a-2和第一联接线224a-3，第一联接线224a-3经由一侧第一接合焊盘222a联接第一布线接合焊盘224a-1和第一重分布线焊盘224a-2。各个第二重分布线224b可以包括第二布线接合焊盘224b-1、第二重分布线焊盘224b-2和第二联接线224b-3，第二联接线224b-3经由另一侧第一接合焊盘222b联接第二布线接合焊盘224b-1和第二重分布线焊盘224b-2。第一布线接合焊盘224a-1可以被设置成与第一半导体芯片220的一侧边缘相邻。第一重分布线焊盘224a-2可以被设置成在另一侧第一接合焊盘222b与第一半导体芯片220的另一侧边缘之间与另一侧第一接合焊盘222b相邻。第二布线接合焊盘224b-1可以被设置成与第一半导体芯片220的另一侧边缘相邻。第二重分布线焊盘224b-2可以被设置在一侧第一接合焊盘222a与另一侧第一接合焊盘222b之间。
在一个实施方式中，一侧第一接合焊盘222a、另一侧第一接合焊盘222b、第一重分布线焊盘224a-2和第二重分布线焊盘224b-2可以被设置成沿着第一方向X成一行对齐。根据该事实，当第二半导体芯片230被堆叠在第一半导体芯片220的上方时，第一半导体芯片220和第二半导体芯片230可以形成阶梯结构。
尽管稍后将再次进行描述，但第一接合焊盘222a和222b以及重分布线焊盘224a-2和224b-2可以被设计成使得它们之间的距离与第一半导体芯片220和第二半导体芯片230的偏移距离基本上相同。
第一半导体芯片220可以包括第一重分布线绝缘层221和第二重分布线绝缘层226。第一重分布线绝缘层221可以按照使第一接合焊盘222a和222b暴露的方式形成在第一有源表面220a上。第二重分布线绝缘层226可以按照覆盖重分布线224a和224b的方式形成在第一重分布线绝缘层221上。第二重分布线绝缘层226可以被形成为使重分布线224a和224b的第一布线接合焊盘224a-1和第二布线接合焊盘224b-1以及第一重分布线焊盘224a-2和第二重分布线焊盘224b-2暴露。
再次参照图2，第二半导体芯片230可以是具有与第一半导体芯片220基本上相同的尺寸和相同的芯片焊盘布置的存储器芯片。第二半导体芯片230可以具有基本上四边形的板形状。第二半导体芯片230可以具有第二有源表面230a和背向第二有源表面230a的第二背表面230b。第二半导体芯片230可以包括布置在第二有源表面230a上的第二接合焊盘232a和232b。
参照图4A和图4B，第二接合焊盘232a和232b可以被设置成在第一方向X上彼此分离。第二接合焊盘232a和232b可以在第二半导体芯片230的第二有源表面230a的中间部分上沿着与第一方向X基本上垂直的第二方向Y布置成两排。在一个实施方式中，第二半导体芯片230的第二接合焊盘232a和232b可以具有与第一半导体芯片220的第一接合焊盘222a和222b相同的布置结构。
第二半导体芯片230可以包括分别形成在第二接合焊盘232a和232b上的凸块234a和234b。例如，凸块234a和234b中的每一个可以是铜后凸块、焊锡凸块和堆叠有多层金属层的凸块当中的任何一种。
再次参照图2，第二半导体芯片230可以被设置在第一半导体芯片220的第一有源表面220a的上方，使得第二有源表面230a面向第一半导体芯片220的第一有源表面220a。例如，第二半导体芯片230可以是通过凸块234a和234b的媒介接合至第一半导体芯片220的倒装芯片。第二半导体芯片230可以被设置成使得其与第一半导体芯片220不完全重叠，并且相对于第一半导体芯片220偏离预定距离d1。换句话说，第二半导体芯片230可以被设置在第一半导体芯片220的上方以形成阶梯形状。凸块234a和234b可以被设置成分别与重分布线焊盘224a-2和224b-2交叠。
在一个实施方式中，第二半导体芯片230的一侧第二接合焊盘232b通过一侧凸块234b与第二重分布线焊盘224b-2电联接，该第二重分布线焊盘224b-2与第一半导体芯片220的另一侧第一接合焊盘222b联接。第二半导体芯片230的另一侧第二接合焊盘232a通过另一侧凸块234a与第一重分布线焊盘224a-2电联接，该第一重分布线焊盘224a-2与第一半导体芯片220的一侧第一接合焊盘222a联接。
第二半导体芯片230与第一半导体芯片220之间的偏移距离d1可以与一侧第一接合焊盘222a和第二重分布线焊盘224b-2之间的间距d2相同。一侧第一接合焊盘222a与第二重分布线焊盘224b-2之间的间距d2和另一侧第一接合焊盘222b与第一重分布线焊盘224a-2之间的间距d2相同。即，第二半导体芯片230可以按照偏移一侧第一接合焊盘222a与第二重分布线焊盘224b-2之间的间距d2的方式设置在第一半导体芯片220的上方。
接合布线250可以被形成为电联接基板210的接合指212a以及第一半导体芯片220的布线接合焊盘224a-1和224b-1。在一个实施方式中，接合布线250可以被形成为将第一半导体芯片220的第一布线接合焊盘224a-1与设置成与基板210的一侧边缘相邻的接合指212a联接。接合布线250可以被形成为将第一半导体芯片220的第二布线接合焊盘224b-1与设置成与基板210的另一侧边缘相邻的接合指212a联接。
封装构件260可以被形成为保护第一半导体芯片220和第二半导体芯片230免受外部影响。封装构件260可以按照覆盖被堆叠成彼此偏移的第一半导体芯片220和第二半导体芯片230以及接合布线250的方式形成在基板210的包括阻焊剂214的顶表面210a上。封装构件260可以被形成为填充第一半导体芯片220与第二半导体芯片230之间的空间。封装构件260可以由环氧模制化合物形成。
外部联接构件270可以被形成为用于在制造存储器模块时将根据所述实施方式的半导体封装件200安装至模块基板的装置。外部联接构件270可以分别被形成布置在基板210的底表面210b上的外部电极212b上。外部联接构件270可以包括焊锡球。在一个实施方式中，外部联接构件270可以包括导电引脚或导电浆料。
根据实施方式的上述半导体封装件200可以提供芯片被设置成彼此面对并且芯片的相应焊盘通过单条重分布线与基板联接的结构。当与常规双管芯封装件相比时，具有这种结构的半导体封装件200可以具有减小的输入电容(Ci)。
例如，图1中例示的常规双管芯封装件的输入电容Ci可以用下面的式1来表示。
输入电容(Ci)＝[(2×Crdl)+(2×Cdie)+Csub] 式1
下面给出的表1描述了常规双管芯封装件的输入电容Ci的测量值。
[表1]
分类 Cdie Crdl Csub 总和
单个Ci[pF] 0.5 0.4 0.7 -
Ci总和[pF] 1.0 0.8 0.7 2.5
百分比[％] 40％ 32％ 28％ 100％
在表1中，Cdie(管芯电容)表示芯片的输入电容，Crdl(RDL电容)表示重分布线的输入电容，Csub(基板电容)表示基板的输入电容，并且Ci总和表示总输入电容。由于常规双管芯封装件具有包含相应重分布线的2个芯片被安装至一个基板的结构，所以根据Cdie和Crdl中的每一个的Ci总和是单个Ci的两倍，并且根据Csub的Ci总和与单个Ci相同。
参照表1，可以看出，常规双管芯封装件的总输入电容Ci为2.5pF，并且重分布线的输入电容Crdl占据了约32％。在如图1中所例示的DIMM通过使用这种封装件来实现的情况下预期的总输入电容Ci变为90pF，如下面的式2所示。
DIMM的总输入电容(Ci)＝2.5pF×36＝90pF 式2
然而，根据实施方式的半导体封装件的输入电容Ci可以用下面的式3来表示。
输入电容(Ci)＝[(Crdl)+(2×Cdie)+Csub] 式3
在根据实施方式的半导体封装件中，由于与常规技术相比时Crdl分量减小了50％，因此因为从常规技术的总输入电容2.5pF中减去了0.4pF，所以总输入电容变为2.1pF。因此，在如图1中例示的DIMM通过使用根据实施方式的半导体封装件来实现的情况下预期的存储器模块的总输入电容Ci变为75.6pF，如下面的式4所示。
DIMM的总输入电容(Ci)＝2.1pF×36＝75.6pF 式4
与常规双管芯封装件相比时，根据实施方式的半导体封装件可以具有减小的输入电容(Ci)。因此，安装了根据实施方式的半导体封装件的DIMM的总输入电容Ci也减小。
图5A和图5B是对常规双管芯封装件和根据实施方式的半导体封装件的各个信号引脚的不包括Cdie分量的总输入电容Ci进行仿真的结果的图的代表示例。如所例示的，可以看出，针对根据实施方式的半导体封装件的各个信号引脚的总输入电容Ci与常规双管芯封装件的总输入电容相比显著减小。例如，可以观察出，与常规双管芯封装件的总输入电容相比，针对根据实施方式的半导体封装件的各个信号引脚的总输入电容Ci减小了约45％。
图6A、图6B、图7A和图7B是通过使用常规双管芯封装件和根据实施方式的半导体封装件而缩小的DIMM的安装评估图的代表示例。这里，CMD+意指命令地址引脚的摆动电压高于0.6V，CMD-意指命令地址引脚的摆动电压低于0.6V，并且有效窗口是CMD+与CMD-之和。
作为根据速度来测量相同样品的结果，如图6A和图6B所例示，与通过使用常规双管芯封装件而缩小的DIMM的CMD电压裕度相比，通过使用根据实施方式的半导体封装件而缩小的DIMM的CMD电压裕度在2400Mbps速率和2667Mbps速率二者处增大。另外，如图7A和图7B所例示，与通过使用常规双管芯封装件而缩小的DIMM的有效窗口相比，通过使用根据实施方式的半导体封装件而缩小的DIMM的有效窗口增大。
因此，通过使用根据实施方式的半导体封装件而缩小的DIMM的电压摆动电平大于通过使用常规双管芯封装件而缩小的DIMM的电压摆动电平，使得读取发送信号时出现的错误减少。因此，可以看出，提高了操作特性。
基板中的信号的延迟时间可以简单地用下面的式5来表示。可以看出，因为C小，所以延迟时间短。
在式5中，L表示电感，并且C表示电容。
结果，在一个实施方式中，通过改变封装件结构并且优化芯片设计，当与常规技术相比时，输入电容Ci可以显著地减小。因此，在通过使用根据实施方式的半导体封装件来实现诸如DIMM的高容量存储器模块的情况下，当与通过使用常规双管芯封装件而实现的存储器模块相比时，可以通过减小总输入电容Ci来缩短信号延迟时间，并且因此可以提高存储器模块的操作速度。
参照图8和图9，根据实施方式的半导体封装件300可以包括基板310、第一半导体芯片320和第二半导体芯片330。半导体封装件300还可以包括粘合剂340、接合布线350、封装构件360和外部联接电极370。
基板310可以是具有基本上四边形的板形状的印刷电路板。基板310可以包括布置在顶表面310a上的接合指312a和布置在底表面310b上的外部电极312b。接合指312a可以被布置成与第一半导体芯片320的两个侧边缘相邻。基板310可以包括按照使接合指312a和外部电极312b暴露的方式形成在顶表面310a和底表面310b上的阻焊剂314。
第一半导体芯片320可以是具有基本上四边形的板形状的存储器芯片。第一半导体芯片320可以具有第一有源表面320a和背向第一有源表面320a的第一背表面320b。第一半导体芯片320可以通过粘合剂340的媒介而被设置在基板310的顶表面310a上，使得第一背表面320b面向基板310的顶表面310a。第一半导体芯片320可以包括在第一有源表面320a的中间部分上布置成两排的第一接合焊盘322a和322b。第一半导体芯片320可以包括形成在第一有源表面320a上的重分布线324a和324b。
例如，为便于说明起见，将基于以下假设来进行下面的描述：在附图中，一侧指示左侧并且另一侧指示右侧。
重分布线324a和324b可以包括从中间部分延伸至第一半导体芯片320的第一有源表面320a的一侧边缘部分的第一重分布线324a以及从中间部分延伸至第一半导体芯片320的第一有源表面320a的另一侧边缘部分的第二重分布线324b。各个第一重分布线324a可以包括第一布线接合焊盘324a-1、第一重分布线焊盘324a-2和第一联接线324a-3，第一联接线324a-3经由一侧第一接合焊盘322a联接第一布线接合焊盘324a-1和第一重分布线焊盘324a-2。各个第二重分布线324b可以包括第二布线接合焊盘324b-1、第二重分布线焊盘324b-2和第二联接线324b-3，第二联接线324b-3经由第二重分布线焊盘324b-2联接第二布线接合焊盘324b-1和另一侧第一接合焊盘322b。第一布线接合焊盘324a-1可以被设置成与第一半导体芯片320的一侧边缘相邻。第一重分布线焊盘324a-2可以被设置成在另一侧第一接合焊盘322b与第一半导体芯片320的另一侧边缘之间与另一侧第一接合焊盘322b相邻。第二布线接合焊盘324b-1可以被设置成与第一半导体芯片320的另一侧边缘相邻。第二重分布线焊盘324b-2可以被设置在另一侧第一接合焊盘322b与第一重分布线焊盘324a-2之间。
在一个实施方式中，一侧第一接合焊盘322a、另一侧第一接合焊盘322b、第一重分布线焊盘324a-2和第二重分布线焊盘324b-2可以被设置成沿着第一方向X成一行对齐。根据该事实，当第二半导体芯片330被堆叠在第一半导体芯片320的上方时，第一半导体芯片320和第二半导体芯片330可以形成阶梯结构。
第一半导体芯片320可以包括第一重分布线绝缘层321和第二重分布线绝缘层326。第一重分布线绝缘层321可以按照使第一接合焊盘322a和322b暴露的方式形成在第一有源表面320a上。第二重分布线绝缘层326可以按照覆盖重分布线324a和324b的方式形成在第一重分布线绝缘层321上。另外，第二重分布线绝缘层326可以被形成为使重分布线324a和324b的第一布线接合焊盘324a-1和第二布线接合焊盘324b-1以及第一重分布线焊盘324a-2和第二重分布线焊盘324b-2暴露。
第二半导体芯片330可以是具有与第一半导体芯片320基本上相同的尺寸和相同的芯片焊盘布置的存储器芯片。第二半导体芯片330可以具有第二有源表面330a和背向第二有源表面330a的第二背表面330b。第二半导体芯片330可以包括被布置在第二有源表面330a上的第二接合焊盘332a和332b。第二接合焊盘332a和332b可以在第二半导体芯片330的第二有源表面330a的中间部分上沿着第二方向Y布置成两排。第二半导体芯片330可以包括分别形成在第二接合焊盘332a和332b上的凸块334a和334b。凸块334a和334b中的每一个可以例如是但不限于铜后凸块、焊料凸块和堆叠有多层金属层的凸块当中的任何一种。
第二半导体芯片330可以被设置在第一半导体芯片320的第一有源表面320a的上方，使得第二有源表面330a面向第一半导体芯片320的第一有源表面320a。也就是说，第二半导体芯片可以是通过凸块334a和334b的媒介接合至第一半导体芯片320的倒装芯片。第二半导体芯片330可以被设置成使得其与第一半导体芯片320不完全重叠，并且相对于第一半导体芯片320偏离预定距离。换句话说，第二半导体芯片330可以被设置在第一半导体芯片320的上方以形成阶梯形状。凸块334a和334b可以被设置成分别与重分布线焊盘324a-2和324b-2交叠。在一个实施方式中，一侧第一接合焊盘322a与第二重分布线焊盘324b-2之间的间距和第一半导体芯片320与第二半导体芯片330之间的偏移距离相同。
在一个实施方式中，第二半导体芯片330的一侧第二接合焊盘332b通过一侧凸块334b与第二重分布线焊盘324b-2电联接，该第二重分布线焊盘324b-2与第一半导体芯片320的另一侧第一接合焊盘322b联接。第二半导体芯片330的另一侧第二接合焊盘332a通过另一侧凸块334a与第一重分布线焊盘324a-2电联接，该第一重分布线焊盘324a-2与第一半导体芯片320的一侧第一接合焊盘322a联接。
接合布线350可以被形成为电联接基板310的接合指312a以及第一半导体芯片320的布线接合焊盘324a-1和324b-1。也就是说，接合布线350可以被形成为将第一半导体芯片320的第一布线接合焊盘324a-1与设置成与基板310的一侧边缘相邻的接合指212a联接。接合布线350可以被形成为将第一半导体芯片320的第二布线接合焊盘324b-1与设置成与基板310的另一侧边缘相邻的接合指312a联接。
封装构件360可以按照覆盖堆叠成彼此偏移的第一半导体芯片320和第二半导体芯片330以及接合布线350的方式形成在基板310的包括阻焊剂314的顶表面310a上。封装构件360可以被形成为填充第一半导体芯片320与第二半导体芯片330之间的空间。封装构件360可以由环氧模制化合物形成。
外部联接构件370可以分别被形成在布置在基板310的底表面310b上的外部电极312b上。外部联接构件370可以包括焊锡球。在一个实施方式中，外部联接构件370可以包括，例如但不限于，导电引脚或导电浆料。
参照图10，根据实施方式的半导体封装件1000可以包括基板610、底部堆叠芯片700和顶部堆叠芯片800。半导体封装件1000可以包括粘合剂910、接合布线920、封装构件930和外部联接电极940。
基板610可以是印刷电路板。基板610可以包括布置在顶表面610a上的接合指612a以及布置在底表面610b上的外部电极612b。接合指612a可以被布置成与底部堆叠芯片700的两个侧边缘相邻。基板610可以包括按照使接合指612a和外部电极612b暴露的方式形成在顶表面610a和底表面610b上的阻焊剂614。
底部堆叠芯片700可以包括堆叠成彼此偏移的第一半导体芯片720和第二半导体芯片730。
第一半导体芯片720可以是存储器芯片。第一半导体芯片720可以具有第一有源表面720a和背向第一有源表面720a的第一背表面720b。第一半导体芯片720可以通过粘合剂910的媒介设置在基板610的顶表面610a上，使得第一背表面720b面向基板610的顶表面610a。第一半导体芯片720可以包括按照彼此分离的方式布置在第一有源表面720a的中间部分上的第一接合焊盘722a和722b。第一半导体芯片720可以包括形成在第一有源表面720a上的重分布线724a和724b。
按照与图2中所例示的实施方式的重分布线224a和224b相同的方式，重分布线724a和724b可以包括从中间部分延伸至第一半导体芯片720的第一有源表面720a的一侧边缘部分的第一重分布线724a以及从中间部分延伸至第一半导体芯片720的第一有源表面720a的另一侧边缘部分的第二重分布线724b。各个第一重分布线724a可以包括第一布线接合焊盘724a-1、第一重分布线焊盘724a-2和第一联接线724a-3，第一联接线724a-3经由一侧第一接合焊盘722a联接第一布线接合焊盘724a-1和第一重分布线焊盘724a-2。各个第二重分布线724b可以包括第二布线接合焊盘724b-1、第二重分布线焊盘724b-2和第二联接线724b-3，第二联接线724b-3经由另一侧第一接合焊盘722b联接第二布线接合焊盘724b-1和第二重分布线焊盘724b-2。
第一布线接合焊盘724a-1可以被设置成与第一半导体芯片720的一侧边缘相邻。第一重分布线焊盘724a-2可以被设置成在另一侧第一接合焊盘722b与第一半导体芯片720的另一侧边缘之间与另一侧第一接合焊盘722b相邻。第二布线接合焊盘724b-1可以被设置成与第一半导体芯片720的另一侧边缘相邻。第二重分布线焊盘724b-2可以被设置在一侧第一接合焊盘722a与另一侧第一接合焊盘722b之间。第一接合焊盘722a和722b、第一重分布线焊盘724a-2以及第二重分布线焊盘724b-2可以被设置成按照如图3A中所例示沿着第一方向X成一行对齐。
第一半导体芯片720可以包括第一重分布线绝缘层721和第二重分布线绝缘层726。第一重分布线绝缘层721可以按照使第一接合焊盘722a和722b暴露的方式形成在第一有源表面720a上。第二重分布线绝缘层726可以按照覆盖重分布线724a和724b的方式形成在第一重分布线绝缘层721上。另外，第二重分布线绝缘层726可以被形成为使重分布线724a和724b的第一布线接合焊盘724a-1和第二布线接合焊盘724b-1以及第一重分布线焊盘724a-2和第二重分布线焊盘724b-2暴露。
第二半导体芯片730可以是具有与第一半导体芯片720基本上相同的尺寸和相同的芯片焊盘布置的存储器芯片。第二半导体芯片730可以具有第二有源表面730a和背向第二有源表面730a的第二背表面730b。第二半导体芯片730可以包括布置在第二有源表面730a上的第二接合焊盘732a和732b。第二半导体芯片730可以包括分别形成在第二接合焊盘732a和732b上的凸块734a和734b。
第二半导体芯片730可以被设置在第一半导体芯片720的第一有源表面720a的上方，使得第二半导体芯片730的第二有源表面730a面向第一半导体芯片720的第一有源表面720a。也就是说，第二半导体芯片730可以是通过凸块734a和734b的媒介接合至第一半导体芯片720的倒装芯片。凸块734a和734b可以被设置成分别与重分布线焊盘724a-2和724b-2交叠。第二半导体芯片730可以被设置成使得其与第一半导体芯片720不完全重叠，并且相对于第一半导体芯片720偏移预定距离。换句话说，第二半导体芯片730可以被设置在第一半导体芯片720的上方以形成阶梯形状。
第二半导体芯片730与第一半导体芯片720之间的偏移距离可以和一侧第一接合焊盘722a与第二重分布线焊盘724b-2之间的间距相同。一侧第一接合焊盘722a与第二重分布线焊盘724b-2之间的间距和另一侧第一接合焊盘722b与第一重分布线焊盘724a-2之间的间距相同。即，第二半导体芯片730可以按照偏移一侧第一接合焊盘722a与第二重分布线焊盘724b-2之间的间距的方式设置在第一半导体芯片720的上方。
在一个实施方式中，第二半导体芯片730的一侧第二接合焊盘732b通过一侧凸块734b与第二重分布线焊盘724b-2电联接，该第二重分布线焊盘724b-2与第一半导体芯片720的另一侧第一接合焊盘722b联接。第二半导体芯片730的另一侧第二接合焊盘732a通过另一侧凸块734a与第一重分布线焊盘724a-2电联接，该第一重分布线焊盘724a-2与第一半导体芯片720的一侧第一接合焊盘722a联接。
按照与底部堆叠芯片700相同的方式，顶部堆叠芯片800可以包括堆叠成彼此偏移的第一半导体芯片720和第二半导体芯片730。顶部堆叠芯片800的第一半导体芯片720和第二半导体芯片730与底部堆叠芯片700的第一半导体芯片720和第二半导体芯片730具有相同的结构。
顶部堆叠芯片800可以通过粘合剂910的媒介而设置在底部堆叠芯片700的第二半导体芯片730的第二背表面730b上。
接合布线920可以被形成为电联接基板610的接合指612a以及底部堆叠芯片700和顶部堆叠芯片800的第一半导体芯片720的相邻布线接合焊盘724a-1和724b-1。
封装构件930可以按照覆盖底部堆叠芯片700、顶部堆叠芯片800和接合布线920的方式形成在基板610的包括阻焊剂614的顶表面610a上。封装构件930可以被形成为填充底部堆叠芯片700和顶部堆叠芯片800中的第一半导体芯片720与第二半导体芯片730之间的空间。
外部联接构件940可以分别被形成在布置在基板610的底表面610b上的外部电极612b上。外部联接构件940可以包括焊锡球。在一个实施方式中，外部联接构件270可以包括，例如但不限于，导电引脚或导电浆料。
根据上述各种实施方式的半导体封装件可以应用于各种类型的电子系统和存储卡。
参照图11，电子系统1100可以包括根据上述各种实施方式的半导体封装件。电子系统1100可以包括控制器1110、输入和输出(输入/输出)单元1120以及存储装置1130。控制器1110、输入和输出(输入/输出)单元1120以及存储装置1130可以通过提供数据移动路径的总线1150彼此联接。
例如，控制器1110可以包括微处理器、数字信号处理器、微控制器和能够执行与这些组件类似的功能的逻辑器件中的至少任何一个。控制器1110和存储装置1130可以包括根据上述各种实施方式的半导体封装件。输入/输出单元1120可以包括小键盘、键盘、显示装置等当中选择的任何一个。
存储装置1130可以存储要由控制器1110执行的数据和/或命令。存储装置1130可以包括诸如DRAM这样的易失性存储装置和/或诸如闪速存储器这样的非易失性存储装置。例如，闪速存储器可以被安装到诸如移动终端和台式计算机这样的信息处理系统。这种闪速存储器可以由SSD(固态驱动器)配置。在这种情况下，电子系统1100可以将大量数据稳定地存储在闪速存储器系统中。
这种电子系统1100还可以包括用于向通信网络发送数据或者从通信网络接收数据的接口1140。接口1140可以是有线类型或无线类型。例如，接口1140可以包括天线或者有线/无线收发器。
尽管没有例示，但电子系统1100还可以包括应用芯片组、相机图像处理器(CIP)等。
电子系统1100可以被实现为移动系统、个人计算机、用于工业用途的计算机或者执行各种功能的逻辑系统。例如，移动系统可以是个人数字助理(PDA)、便携式计算机、网络平板计算机、移动电话、智能电话、无线电话、膝上型计算机、存储卡、数字音乐系统以及信息发送/接收系统当中的任何一个。
在电子系统1100是能够执行无线通信的设备的情况下，电子系统1100可以用于诸如CDMA(码分多址)、GSM(全球移动通信系统)、NADC(北美数字蜂窝)、E-TDMA(增强型时分多址)、WCDMA(宽带码分多址)、CDMA2000、LTE(长期演进)和Wibro(无线宽带互联网)这样的通信系统中。
参照图12，存储卡可以包括根据上述各种实施方式的半导体封装件。例如，存储卡1200可以包括诸如非易失性存储装置这样的存储器1210和存储控制器1220。存储器1210和存储控制器1220可以存储数据或者读取所存储的数据。存储器1210可以包括应用根据上述各种实施方式的半导体封装件的非易失性存储装置当中的至少任何一个。存储控制器1220可以控制存储器1210响应于来自主机1230的读和写(读/写)请求而读取所存储的数据或存储数据。
尽管以上已描述了各种实施方式，但本领域技术人员将理解的是，这些实施方式仅是通过示例的方式来描述的。因此，本文中所描述的具有重分布线结构的堆叠型半导体封装件不应基于上述实施方式而被限制。
相关申请的交叉引用
本申请要求于2016年11月16日在韩国知识产权局提交的韩国专利申请No.10-2016-0152358的优先权，该韩国专利申请通过引用方式全部并入本文中。

Claims (20)

1.一种半导体封装件，该半导体封装件包括：
第一半导体芯片，所述第一半导体芯片具有在第一有源表面的中间部分上布置成两排的第一接合焊盘；
第二半导体芯片，所述第二半导体芯片具有与所述第一半导体芯片基本上相同的尺寸，并且具有在第二有源表面的中间部分上布置成两排的第二接合焊盘；
重分布线，所述重分布线形成在所述第一有源表面上，并且具有与所述第一接合焊盘联接的重分布线焊盘和布线接合焊盘；以及
凸块，所述凸块分别形成在所述第二半导体芯片的所述第二接合焊盘上，
其中，所述第一接合焊盘和所述第二接合焊盘按照相同的焊盘布置结构来设置，
其中，所述第一半导体芯片和所述第二半导体芯片被堆叠成使得所述第一有源表面和所述第二有源表面彼此面对，并且被设置成彼此偏移，并且
其中，所述凸块被设置成分别与所述重分布线焊盘交叠。
2.根据权利要求1所述的半导体封装件，
其中，所述重分布线包括：
第一重分布线，所述第一重分布线与布置成两排的所述第一接合焊盘的一侧第一接合焊盘联接，并且朝向所述第一半导体芯片的一侧边缘延伸；以及
第二重分布线，所述第二重分布线与布置成两排的所述第一接合焊盘的另一侧第一接合焊盘联接，并且朝向所述第一半导体芯片的另一侧边缘延伸，
其中，所述第二半导体芯片的所述第二接合焊盘包括一侧第二接合焊盘和另一侧第二接合焊盘，并且
其中，所述凸块包括形成在所述一侧第二接合焊盘上的一侧凸块以及形成在所述另一侧第二接合焊盘上的另一侧凸块。
3.根据权利要求2所述的半导体封装件，
其中，所述第一重分布线包括：
第一布线接合焊盘，所述第一布线接合焊盘被设置成与所述一侧边缘相邻；
第一重分布线焊盘，所述第一重分布线焊盘被设置成在所述另一侧第一接合焊盘和所述另一侧边缘之间与所述另一侧第一接合焊盘相邻；以及
第一联接线，所述第一联接线经由所述一侧第一接合焊盘联接所述第一布线接合焊盘和所述第一重分布线焊盘，并且
其中，所述第二重分布线包括：
第二布线接合焊盘，所述第二布线接合焊盘被设置成与所述另一侧边缘相邻；
第二重分布线焊盘，所述第二重分布线焊盘被设置在所述一侧第一接合焊盘与所述另一侧第一接合焊盘之间；以及
第二联接线，所述第二联接线经由所述另一侧第一接合焊盘联接所述第二布线接合焊盘和所述第二重分布线焊盘。
4.根据权利要求3所述的半导体封装件，其中，所述一侧第一接合焊盘和所述另一侧第一接合焊盘以及所述第一重分布线焊盘和所述第二重分布线焊盘被设置成在所述第一半导体芯片的所述第一有源表面上成一行对齐。
5.根据权利要求3所述的半导体封装件，其中，所述一侧第一接合焊盘与所述第二重分布线焊盘之间的间距和所述第一半导体芯片与所述第二半导体芯片之间的偏移距离相同。
6.根据权利要求3所述的半导体封装件，
其中，所述一侧第二接合焊盘通过所述一侧凸块与所述第二重分布线焊盘电联接，并且
其中，所述另一侧第二接合焊盘通过所述另一侧凸块与所述第一重分布线焊盘电联接。
7.根据权利要求6所述的半导体封装件，
其中，所述第一半导体芯片的所述一侧第一接合焊盘与所述第二半导体芯片的所述另一侧第二接合焊盘通过第一重分布线焊盘和形成在所述另一侧第二接合焊盘上的所述另一侧凸块彼此电联接，所述第一重分布线焊盘与所述另一侧凸块电联接并且与所述一侧第一接合焊盘联接，并且
其中，所述第一半导体芯片的所述另一侧第一接合焊盘与所述第二半导体芯片的所述一侧第二接合焊盘通过第二重分布线焊盘和形成在所述一侧第二接合焊盘上的所述一侧凸块彼此电联接，所述第二重分布线焊盘与所述一侧凸块电联接并且与所述另一侧第一接合焊盘联接。
8.根据权利要求2所述的半导体封装件，
其中，所述第一重分布线包括：
第一布线接合焊盘，所述第一布线接合焊盘被设置成与所述一侧边缘相邻；
第一重分布线焊盘，所述第一重分布线焊盘被设置成在所述另一侧第一接合焊盘与所述另一侧边缘之间与所述另一侧第一接合焊盘相邻；以及
第一联接线，所述第一联接线经由所述一侧第一接合焊盘联接所述第一布线接合焊盘和所述第一重分布线焊盘，并且
其中，所述第二重分布线包括：
第二布线接合焊盘，所述第二布线接合焊盘被设置成与所述另一侧边缘相邻；
第二重分布线焊盘，所述第二重分布线焊盘被设置在所述另一侧第一接合焊盘与所述第一重分布线焊盘之间；以及
第二联接线，所述第二联接线经由所述第二重分布线焊盘联接所述第二布线接合焊盘和所述另一侧第一接合焊盘。
9.根据权利要求8所述的半导体封装件，其中，所述一侧第一接合焊盘和所述另一侧第一接合焊盘以及所述第一重分布线焊盘和所述第二重分布线焊盘被设置为成一行对齐。
10.根据权利要求8所述的半导体封装件，其中，所述一侧第一接合焊盘与所述第二重分布线焊盘之间的间距和所述第一半导体芯片与所述第二半导体芯片之间的偏移距离相同。
11.根据权利要求8所述的半导体封装件，
其中，所述第二半导体芯片的所述一侧第二接合焊盘通过所述一侧凸块与所述第一半导体芯片的所述第二重分布线焊盘电联接，并且
其中，所述第二半导体芯片的所述另一侧第二接合焊盘通过所述另一侧凸块与所述第一半导体芯片的所述第一重分布线焊盘电联接。
12.根据权利要求11所述的半导体封装件，
其中，所述第一半导体芯片的所述一侧第一接合焊盘与所述第二半导体芯片的所述另一侧第二接合焊盘通过第一重分布线焊盘和形成在所述另一侧第二接合焊盘上的所述另一侧凸块彼此电联接，所述第一重分布线焊盘与所述另一侧凸块电联接并且与所述一侧第一接合焊盘联接，并且
其中，所述第一半导体芯片的所述另一侧第一接合焊盘与所述第二半导体芯片的所述一侧第二接合焊盘通过第二重分布线焊盘和形成在所述一侧第二接合焊盘上的所述一侧凸块彼此电联接，所述第二重分布线焊盘与所述一侧凸块电联接并且与所述另一侧第一接合焊盘联接。
13.根据权利要求1所述的半导体封装件，其中，所述第一半导体芯片还具有第一重分布线绝缘层和第二重分布线绝缘层，所述第一重分布线绝缘层按照使所述第一接合焊盘暴露的方式形成在所述第一有源表面的上方，所述第二重分布线绝缘层按照覆盖所述重分布线并且使所述重分布线的所述布线接合焊盘和所述重分布线焊盘暴露的方式形成在所述第一重分布线绝缘层上。
14.根据权利要求1所述的半导体封装件，该半导体封装件还包括：
基板，所述基板具有布置有接合指的顶表面以及布置有外部电极的底表面，并且所述基板被设置成使得所述顶表面面向第一背表面，所述第一背表面背向所述第一半导体芯片的所述第一有源表面；以及
接合布线，所述接合布线被形成为联接所述接合指和所述布线接合焊盘。
15.根据权利要求14所述的半导体封装件，
其中，所述接合指被布置在所述基板的所述顶表面的与所述第一半导体芯片的两个侧边缘相邻的部分上，并且
其中，所述接合布线被形成为联接与所述第一半导体芯片的两个侧边缘相邻的所述接合指和所述布线接合焊盘。
16.根据权利要求14所述的半导体封装件，该半导体封装件还包括：
粘合剂，所述粘合剂被插置于所述第一半导体芯片的所述第一背表面与所述基板的所述顶表面之间。
17.根据权利要求14所述的半导体封装件，该半导体封装件还包括：
第三半导体芯片，所述第三半导体芯片具有面向所述第二半导体芯片的第二背表面的第一背表面以及背向所述第二半导体芯片的所述第二背表面的第一有源表面；
第四半导体芯片，所述第四半导体芯片具有面向所述第三半导体芯片的所述第一有源表面的第二有源表面以及背向所述第三半导体芯片的所述第一有源表面的第二背表面；以及
粘合剂，所述粘合剂被插置于所述第三半导体芯片的所述第一背表面与所述第二半导体芯片的所述第二背表面之间，
其中，所述第三半导体芯片和所述第四半导体芯片被设置成彼此偏移。
18.根据权利要求14所述的半导体封装件，该半导体封装件还包括：
封装构件，所述封装构件按照覆盖所述第一半导体芯片和所述第二半导体芯片以及所述接合布线的方式形成在所述基板的所述顶表面上；以及
外部联接端子，所述外部联接端子形成在所述外部电极上。
19.根据权利要求18所述的半导体封装件，其中，所述封装构件被填充在所述第一半导体芯片与所述第二半导体芯片之间的空间中。
20.一种半导体封装件，该半导体封装件包括：
第一半导体芯片，所述第一半导体芯片具有布置在所述第一半导体芯片的第一有源表面上的第一接合焊盘；
第二半导体芯片，所述第二半导体芯片具有布置在所述第二半导体芯片的第二有源表面上的第二接合焊盘；
重分布线，所述重分布线形成在所述第一有源表面上，并且具有与所述第一接合焊盘联接的重分布线焊盘和布线接合焊盘；以及
凸块，所述凸块分别形成在所述第二半导体芯片的所述第二接合焊盘上，
其中，所述第一接合焊盘和所述第二接合焊盘按照相同的焊盘布置结构来设置，
其中，所述第一半导体芯片和所述第二半导体芯片被堆叠成使得所述第一有源表面和所述第二有源表面彼此面对，并且被设置成彼此偏移，并且
其中，所述凸块被设置成分别与所述重分布线焊盘交叠。
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