CN108022965B - Fin field effect transistor and forming method thereof - Google Patents

Fin field effect transistor and forming method thereof Download PDF

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CN108022965B
CN108022965B CN201610935251.8A CN201610935251A CN108022965B CN 108022965 B CN108022965 B CN 108022965B CN 201610935251 A CN201610935251 A CN 201610935251A CN 108022965 B CN108022965 B CN 108022965B
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isolation
fin
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CN108022965A (en
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邓浩
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A fin field effect transistor and a forming method thereof are provided, and the forming method comprises the following steps: forming a substrate and a plurality of fin parts which are arranged on the substrate in an array manner, wherein the extending direction of the fin parts is a first direction, and the direction which is vertical to the extending direction of the fin parts is a second direction; forming isolation material layers between the fin parts, wherein the isolation material layers between the fin parts in the first direction are isolation layers; forming an ultraviolet absorption layer having a first opening on the isolation layer; hardening the isolation layer exposed from the bottom of the first opening through ultraviolet hardening treatment to form an initial step layer; removing the ultraviolet absorption layer; etching back the isolation material layer to form an isolation structure, and thinning the initial step layer to form a step layer in the process of etching back the isolation material layer; and forming a gate structure on the fin part, wherein the gate structure stretches across the fin part and covers the top and the side wall surface of the fin part, and a pseudo gate structure is formed on the step layer in the process of forming the gate structure. The technical scheme provided by the invention improves the performance of the transistor.

Description

Fin field effect transistor and forming method thereof
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a fin type field effect transistor and a forming method thereof.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration. As the transistor is currently widely used as the most basic semiconductor device, as the element density and the integration degree of the semiconductor device are improved, the gate size of the planar transistor is shorter and shorter, and the conventional planar transistor has weak control capability on channel current, generates a short channel effect, generates leakage current, and finally affects the electrical performance of the semiconductor device.
In order to overcome the short channel effect of the transistor and suppress the leakage current, a Fin field effect transistor (Fin FET) is proposed in the prior art, and the Fin FET is a common multi-gate device. The structure of the fin field effect transistor comprises: the isolation layer covers a part of the side wall of the fin part, and the surface of the isolation layer is lower than the top of the fin part; a gate structure spanning the fin and covering the top and sidewall surfaces of the fin portion; and the source and drain doped regions are positioned in the fin parts at two sides of the grid structure.
With the continuous reduction of the size of the semiconductor device, the distance between adjacent fins is reduced, and the difficulty of the process for forming the isolation layer between the adjacent fins is increased, so that the performance of the formed fin field effect transistor is affected.
Disclosure of Invention
The invention provides a fin field effect transistor and a forming method thereof, and aims to improve the performance of the fin field effect transistor.
In order to solve the above problems, the present invention provides a method for forming a fin field effect transistor, including: forming a substrate, wherein the substrate is provided with a plurality of fin parts which are arranged in an array manner, the extending direction of the fin parts is a first direction, and the direction which is vertical to the extending direction of the fin parts is a second direction; forming isolation material layers between the fin parts in the first direction and between the fin parts in the second direction, wherein the isolation material layers between the fin parts in the first direction are isolation layers; forming an ultraviolet absorption layer with a first opening on the isolation layer, wherein the first opening exposes the top surface of the isolation layer; hardening the isolation layer exposed from the bottom of the first opening through ultraviolet hardening treatment to form an initial step layer; removing the ultraviolet absorption layer; etching the isolation material layer back to form an isolation structure, exposing partial side wall surfaces of the fins, thinning the initial step layer to form a step layer in the process of etching the isolation material layer back, wherein the removal rate of the isolation material layer in the etching back step is greater than that of the initial step layer; and forming a gate structure on the fin part, wherein the gate structure stretches across the fin part and covers the top of the fin part and the surface of the side wall, and a pseudo gate structure is formed on the step layer in the process of forming the gate structure.
Optionally, the ultraviolet absorbing layer is a nanoparticle layer.
Optionally, the nanoparticles are zinc oxide nanoparticles or titanium dioxide nanoparticles.
Optionally, the step of forming the ultraviolet absorption layer includes: the zinc oxide nanoparticles are prepared by an alcohol solution synthesis method.
Optionally, the alcohol solution is methanol, ethanol or propanol.
Optionally, the nanoparticles have a particle size of 1-4 nm.
Optionally, the thickness of the ultraviolet absorption layer is
Figure BDA0001138740900000021
Optionally, the time of the ultraviolet hardening treatment is 3-6 min.
Optionally, the step of forming the substrate includes: providing a substrate; forming a first mask layer on the substrate; etching the substrate by taking the first mask layer as a mask to form a substrate and a plurality of fin parts arranged in an array form on the substrate; the forming method further includes: after the step of removing the ultraviolet absorption layer and before the step of etching back, enabling the initial step layer and the isolation material layer to be flush with the surface of the first mask layer through a planarization process; the forming method further includes: and removing the first mask layer after the back etching step and before forming the gate structure.
Optionally, the step of hardening the isolation layer exposed at the bottom of the first opening by an ultraviolet hardening treatment includes: and carrying out light radiation on the isolation layer exposed at the bottom of the first opening by adopting an ultraviolet lamp, wherein the wavelength range of light emitted by the ultraviolet lamp is 200-600 nm.
Optionally, the wavelength range of the light emitted by the ultraviolet lamp is 200-400 nm.
Optionally, the forming method further includes: after the ultraviolet absorption layer with the first opening is formed and before ultraviolet hardening treatment is carried out, silicon ion implantation and nitrogen ion implantation are carried out on the ultraviolet absorption layer and the isolation layer exposed from the bottom of the first opening.
Optionally, the dose range of the silicon ion implantation is 5E14-5E16atm/cm2Energy rangeThe circumference is 5-10 keV.
Optionally, the dosage range of the nitrogen ion implantation is 5E14-5E16atm/cm2The energy range is 5-10 keV.
Optionally, in the step of forming the step layer, the sum of the thicknesses of the step layer and the isolation layer is 150-200 nm.
Optionally, the forming method further includes: and after the ultraviolet absorption layer is removed and before the isolation layer is etched back, carrying out steam annealing process treatment on the isolation material layer, the isolation layer and the initial stage layer.
Optionally, the isolation material layer is made of silicon dioxide, and the step layer is made of a silicon-rich oxide layer.
Correspondingly, the invention also provides a fin field effect transistor, which comprises: the substrate is provided with a plurality of fin parts which are arranged in an array mode, the extending direction of the fin parts is a first direction, and the direction perpendicular to the extending direction of the fin parts is a second direction; an isolation layer on the substrate between the first direction fin portions; a step layer on the isolation layer; the isolation structures are positioned between the fin parts, part of the side wall surfaces of the fin parts are exposed out of the isolation structures, and the top surfaces of the isolation structures are lower than the top surfaces of the step layers; the grid electrode structure is positioned on the fin part and stretches across the fin part and covers the top of the fin part and the surface of the side wall; and the pseudo gate structure is positioned on the step layer.
Optionally, the sum of the thicknesses of the step layer and the isolation layer is 150-200 nm.
Optionally, the isolation structure is made of silicon dioxide, and the step layer is a silicon-rich oxide layer.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the technical scheme of the fin field effect transistor forming method, an ultraviolet absorption layer with a first opening is formed on an isolation layer, and the first opening exposes the top surface of the isolation layer; hardening the isolation layer exposed from the bottom of the first opening through ultraviolet hardening treatment to form an initial step layer; then, etching back the isolation material layer and the initial step layer to form an isolation structure and a step layer; and forming a grid structure and a pseudo-grid structure on the fin part and the step layer respectively. Because the density of the initial step layer formed by ultraviolet hardening treatment is higher, in the back etching step, the etching rate of the back etching to the initial step layer is lower than that to the isolation material layer, so that the removal amount of the initial step layer in the back etching process is lower than that to the isolation material layer, and the surface of the formed step layer can be higher than that of the isolation structure. In addition, in the prior art, an initial step layer is usually formed by a high aspect ratio process, and then the initial step layer is subjected to high-temperature thermal hardening treatment to form a step layer with higher density. Compared with the prior art, the high-density step layer is formed through ultraviolet hardening treatment and is not subjected to high-temperature treatment, so that the thermal budget of the transistor is reduced, performance degradation of the device can be caused by excessive thermal budget, and the electrical performance and stability of the transistor are improved.
In addition, the step layer is formed by hardening the isolation layer, so that the interface performance of the step layer and the isolation layer is good, the density of the step layer is high, and the performance is excellent. Therefore, the pseudo gate structure formed on the step layer has good stability, and the pseudo gate structure is prevented from contacting with the fin part, so that the electric isolation effect of the pseudo gate structure is improved, and the performance of the formed fin field effect transistor is improved.
In an alternative scheme, after an ultraviolet absorption layer with a first opening is formed and before ultraviolet hardening treatment is carried out, silicon ion implantation and nitrogen ion implantation are carried out on the ultraviolet absorption layer and an isolation layer exposed at the bottom of the first opening, so that the silicon content and the nitrogen content in the isolation layer can be improved, the silicon content and the nitrogen content in a subsequently formed step layer are improved, and the density of the step layer is further improved.
Drawings
Fig. 1 to 6 are schematic structural views corresponding to steps of a method for forming a finfet;
fig. 7 to 15 are schematic structural views corresponding to steps of a method for forming a finfet device according to an embodiment of the present invention.
Detailed Description
As can be seen from the background, the finfet in the prior art has performance problems. The reason for the performance problem of the FinFET is analyzed in combination with the formation process of the FinFET.
As the size of semiconductor devices and transistors decreases, the distance between adjacent finfets decreases. The stress layers of adjacent finfets are prone to coupling (merge), which causes bridging between the source and drain regions of adjacent finfets. To prevent bridging between source and drain regions of adjacent finfets, the prior art introduces a Single Diffusion Barrier (SDB) structure.
Fig. 1 to 6 are schematic structural diagrams corresponding to steps of a method for forming a finfet with a single diffusion blocking structure.
Reference is made to fig. 1 and 2, wherein fig. 2 is a schematic cross-sectional view along aa1 in fig. 1.
As shown in fig. 1 and fig. 2, a substrate 10 is formed, where the substrate 10 has a plurality of first fin portions 11a parallel to each other and a plurality of second fin portions 11b parallel to each other, and the second fin portions 11b are located in an extending direction of the first fin portions 11 a; a first isolation structure 12a is arranged between the first fin portion 11a and the second fin portion 11b, a second isolation structure 12b is arranged between the adjacent first fin portion 11a and the adjacent second fin portion 12b, and top surfaces of the first isolation structure 12a and the second isolation structure 12b are flush with top surfaces of the first fin portion 11a and the second fin portion 11 b.
Referring to fig. 3, a mask layer 13 having an opening 14 is formed, the mask layer 13 covers the first fin portion 11a, the second fin portion 11b, and the top surface of the second isolation structure 12b, and the first isolation structure 11a is exposed at the bottom of the opening 14.
Referring to fig. 4, a step layer 15 is formed in the opening 14 (shown in fig. 3), and a top surface of the step layer 15 is flush with a top surface of the mask layer 13.
Referring to fig. 5, the mask layer 13 is removed (as shown in fig. 4), exposing the second isolation structure 12 b.
Referring to fig. 6, the second isolation structure 12b is etched back to expose a portion of the sidewall surfaces of the first fin portion 11a and the second fin portion 11 b; and thinning the step layer 15 in the process of etching back the second isolation structure 12 b.
In the prior art, in the step of forming the step, a high aspect ratio process is usually used to form the step, however, a high temperature thermal hardening process is required to form the step with higher density in the high aspect ratio process, which increases the thermal budget of the transistor, and excessive thermal budget may cause degradation of device performance, thereby reducing the electrical performance and stability of the finfet.
In addition, the step layer and the first isolation structure are formed by two filling processes, and since the step layer and the first isolation structure are formed in different processes, the interface performance of the step layer and the first isolation structure is poor, so that the stability performance of a subsequently formed pseudo gate structure is poor, the electrical isolation effect of the pseudo gate structure is poor, and the performance of the formed fin field effect transistor is reduced.
In order to solve the technical problem, the invention provides a method for forming a fin field effect transistor, which comprises the following steps: forming a substrate, wherein the substrate is provided with a plurality of fin parts which are arranged in an array manner, the extending direction of the fin parts is a first direction, and the direction which is vertical to the extending direction of the fin parts is a second direction; forming isolation material layers between the fin parts in the first direction and between the fin parts in the second direction, wherein the isolation material layers between the fin parts in the first direction are isolation layers; forming an ultraviolet absorption layer with a first opening on the isolation layer, wherein the first opening exposes the top surface of the isolation layer; hardening the isolation layer exposed from the bottom of the first opening through ultraviolet hardening treatment to form an initial step layer; removing the ultraviolet absorption layer; etching the isolation material layer back to form an isolation structure, exposing partial side wall surfaces of the fins, thinning the initial step layer to form a step layer in the process of etching the isolation material layer back, wherein the removal rate of the isolation material layer in the etching back step is greater than that of the initial step layer; and forming a gate structure on the fin part, wherein the gate structure stretches across the fin part and covers the top of the fin part and the surface of the side wall, and a pseudo gate structure is formed on the step layer in the process of forming the gate structure.
The ultraviolet absorption layer with the first opening is formed on the isolation layer, and the first opening exposes the top surface of the isolation layer; hardening the isolation layer exposed from the bottom of the first opening through ultraviolet hardening treatment to form an initial step layer; then, etching back the isolation material layer and the initial step layer to form an isolation structure and a step layer; and forming a grid structure and a pseudo-grid structure on the fin part and the step layer respectively. Because the density of the initial step layer formed by ultraviolet hardening treatment is higher, in the back etching step, the etching rate of the back etching to the initial step layer is lower than that to the isolation material layer, so that the removal amount of the initial step layer in the back etching process is lower than that to the isolation material layer, and the surface of the formed step layer can be higher than that of the isolation structure. In addition, in the prior art, an initial step layer is usually formed by a high aspect ratio process, and then the initial step layer is subjected to high-temperature thermal hardening treatment to form a step layer with higher density. Compared with the prior art, the high-density step layer is formed through ultraviolet hardening treatment and is not subjected to high-temperature treatment, so that the thermal budget of the transistor is reduced, performance degradation of the device can be caused by excessive thermal budget, and the electrical performance and stability of the transistor are improved.
In addition, the step layer is formed by hardening the isolation layer, so that the interface performance of the step layer and the isolation layer is good, the density of the step layer is high, and the performance is excellent. Therefore, the pseudo gate structure formed on the step layer has good stability, and the pseudo gate structure is prevented from contacting with the fin part, so that the electric isolation effect of the pseudo gate structure is improved, and the performance of the formed fin field effect transistor is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Referring to fig. 7 to 15, which are schematic structural diagrams of a finfet formation process according to the present invention,
in this embodiment, a finfet with a single diffusion blocking structure is formed as an example.
Referring to fig. 7, a substrate 100 is formed, where the substrate 100 has a plurality of fins 120 arranged in an array, an extending direction of the fins 120 is a first direction AA1, and a direction perpendicular to the extending direction of the fins 120 is a second direction BB 1.
The substrate 100 is used to provide a process platform for subsequently forming devices. The substrate 100 is made of silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide; the substrate 100 may also be a silicon-on-insulator substrate, a germanium-on-insulator substrate, or a germanium-on-insulator substrate. In this embodiment, the substrate 100 is a silicon substrate.
Specifically, the step of forming the substrate 100 includes: providing a substrate (not labeled); forming a first mask layer 110 on the substrate; and etching the base by using the first mask layer 110 as a mask to form the substrate 100 and a plurality of fin portions 120 arranged in an array on the substrate 100, wherein the extending direction along the fin portions 120 is a first direction AA1, and the extending direction perpendicular to the fin portions 120 is a second direction BB 1.
The first mask layer 110 is used to serve as a mask in the process of etching the substrate to form the fin 120. In addition, the surface of the first mask layer 110 can serve as a stop position for the planarization process and protect the fin 120 in the subsequent semiconductor process, so that the fin 120 has good top surface performance.
The step of forming the first mask layer 110 includes: forming a first initial mask material layer on the surface of the substrate; forming a first pattern layer on the surface of the first initial mask material layer; and etching the first initial mask material layer by taking the first pattern layer as a mask until the surface of the substrate is exposed to form a first mask layer 110. Specifically, the first initial mask layer is made of silicon nitride.
In this embodiment, before forming the first mask layer 110, the forming method further includes: a buffer layer (not shown) is formed on the surface of the substrate to improve the lattice mismatch between the first initial mask layer and the substrate. Specifically, the material of the buffer layer may be an oxide.
In this embodiment, the first pattern layer is a photoresist layer and may be formed through a coating process and a photolithography process. In order to reduce the feature size of the subsequently formed fins 120 and the distance between adjacent fins 120, and further improve the integration of the formed transistor, the first pattern layer may also be a mask formed by a multiple patterning process. The multiple patterning mask process comprises the following steps: a Self-aligned Double patterning (SaDP) process, a Self-aligned Triple patterning (SaTP) process, or a Self-aligned quadruple patterning (SaDDP) process.
The process for etching the substrate is an anisotropic dry etching process. The sidewalls of the formed fins 120 are thus perpendicular or oblique with respect to the surface of the substrate 100, and the bottom dimension of the fins 120 is larger than the top dimension when the sidewalls of the fins 120 are oblique with respect to the substrate 100 surface. In this embodiment, the sidewalls of the fins 120 are inclined with respect to the surface of the substrate 100.
It should be noted that, in order to repair the surface damage or the unevenness of the substrate 100 and the fin 120 to improve the performance of the formed transistor, in this embodiment, after the substrate 100 and the fin 120 are formed, the forming method further includes: a liner oxide layer (liner oxide) (not shown) is formed on the surfaces of the substrate 100 and the fin portion 120. The liner oxide layer may also round off sharp corners of the surfaces of the substrate 100 and the fin 120 and act as a buffer layer between subsequent layers and the substrate 100 and the fin 120 to reduce lattice mismatch. Specifically, the step of forming the liner oxide layer includes: and forming the lining oxide layer by adopting an in-situ water vapor generation oxidation process.
In this embodiment, the fin 120 is made of silicon, and the liner oxide layer is correspondingly made of silicon oxide.
Referring to fig. 8, fig. 8 is a schematic cross-sectional view along the first direction AA 1. Forming isolation material layers 130 between the fins 120 in the first direction AA1 and between the fins 120 in the second direction BB1, wherein the isolation material layers 130 between the fins 120 in the first direction AA1 are isolation layers 140;
the isolation material layer 130 provides a process foundation for the subsequent formation of isolation structures, and the isolation layer 140 provides a process foundation for the subsequent formation of step layers.
The material of the isolation material layer 130 may be selected from silicon oxide, silicon nitride, silicon oxynitride, a low-K dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9), or an ultra-low-K dielectric material (dielectric constant less than 2.5). In this embodiment, the material of the isolation material layer 130 is silicon oxide.
As the integration of the transistor increases, the distance between the fins 120 and other semiconductor structures decrease accordingly, so that the aspect ratio of the trench between the fins 120 increases and the aspect ratio of the trench between the fins 120 and other semiconductor structures increases. In order to achieve sufficient filling of the isolation material layer 130, in this embodiment, the isolation material layer 130 is formed by means of Fluid Chemical Vapor Deposition (FCVD). In other embodiments, the isolation material layer may also be formed by a high aspect ratio chemical vapor deposition process.
It should be noted that the formed isolation material layer 130 is not yet annealed and is in a fluid state, and an annealing process is subsequently performed after the initial step layer is formed, so as to improve the compactness of the initial step layer and the isolation material layer 130.
Referring to fig. 9, an ultraviolet absorbing layer 150 having a first opening exposing a top surface of the isolation layer 140 is formed on the isolation layer 140.
In the subsequent uv hardening process, on one hand, the uv absorbing layer 150 with the first opening can be used as a mask to harden the isolation layer 140 exposed at the bottom of the first opening, so as to form an initial step layer; on the other hand, the ultraviolet absorption layer 150 may also serve as a protective layer, and in the ultraviolet hardening process, ultraviolet light is absorbed, so that damage to the fin portion 120 caused by the ultraviolet light is reduced, and thus the performance of the formed fin field effect transistor is improved.
Specifically, the step of forming the ultraviolet absorbing layer 150 having the first opening includes: forming an initial uv absorbing layer (not shown) covering the spacer material layer 130; forming a second mask layer (not shown) on the initial ultraviolet absorption layer; and etching the initial ultraviolet absorption layer by taking the second mask layer as a mask to form an ultraviolet absorption layer 150 with a first opening.
The initial uv absorbing layer may be coated on the spacer material layer 130 by spin coating.
Note that the thickness of the ultraviolet absorbing layer 150 is not too thick nor too thin. If the thickness of the uv absorbing layer 150 is too thick, the cost and process difficulty of forming the uv absorbing layer 150 may be increased, and the difficulty of removing the uv absorbing layer 150 in the subsequent planarization process may be increased. If the thickness of the ultraviolet absorption layer 150 is too thin, the ultraviolet absorption layer 150 is difficult to achieve a better ultraviolet light absorption effect, so that the purpose of reducing the damage of ultraviolet light to the fin 120 is difficult to achieve, and the performance of the formed fin field effect transistor is difficult to improve. Therefore, in this embodiment, the thickness of the ultraviolet absorption layer 150 is
Figure BDA0001138740900000101
The ultraviolet absorbing layer 150 may be a nanoparticle layer. The nanoparticle layer may absorb ultraviolet light, thereby reducing damage to the fins 120 due to ultraviolet radiation. Specifically, the nanoparticles may be zinc oxide nanoparticles or titanium dioxide nanoparticles. In this embodiment, the nanoparticles are zinc oxide nanoparticles.
Specifically, the zinc oxide nanoparticles can be obtained by various alcohol solution synthesis methods, such as methanol, ethanol, propanol, and the like.
It should be noted that, in order to make the ultraviolet absorption layer 150 have a good ultraviolet absorption effect, in this embodiment, the particle size of the nanoparticles is 1 to 4 nm.
In addition, the forming method further includes: after the ultraviolet absorption layer 150 having the first opening is formed, silicon ion implantation and nitrogen ion implantation are performed on the ultraviolet absorption layer 150 and the isolation layer 140 exposed at the bottom of the first opening.
The silicon ion implantation and the nitrogen ion implantation can improve the silicon content and the oxygen content of the isolation layer 140 exposed at the bottom of the first opening, so that the density of the isolation layer 140 exposed at the bottom of the first opening is improved, and a process foundation is provided for the subsequent formation of a high-density step layer.
Specifically, the dosage range of the silicon ion implantation is 5E14-5E16atm/cm2The energy range is 5-10 keV; the dosage range of the nitrogen ion implantation is 5E14-5E16atm/cm2The energy range is 5-10 keV.
It should be noted that the first hard mask layer 110 may play a role in protecting the fin 120 during the processes of silicon ion implantation and nitrogen ion implantation.
Referring to fig. 10, the isolation layer 140 exposed at the bottom of the first opening is cured by a uv curing process 160 to form an initial step layer 170.
The ultraviolet hardening treatment 160 is to harden the isolation layer 140 by using ultraviolet light to form the initial step layer 170 with high density, so that in the subsequent etching back step, the etching rate of the etching back process on the initial step layer 170 is less than the etching rate on the isolation material layer 130, and therefore the removal amount of the initial step layer 170 in the subsequent etching back process is less than the removal rate on the isolation material layer 130, so that the surface of the formed step layer is higher than the surface of the isolation structure.
It should be noted that, in the prior art, the initial step layer 170 is usually formed by a high aspect ratio process, and then the initial step layer 170 is subjected to a high temperature thermal hardening process to form a step layer with higher density. Compared with the prior art, the high-density initial step layer 170 and the step layers formed subsequently in this embodiment are formed by the ultraviolet hardening treatment 160 and are not subjected to the high-temperature treatment, so that the thermal budget of the transistor is reduced, and the performance of the device is degraded due to the excessive thermal budget, thereby improving the electrical performance and stability of the transistor.
In addition, since the step layer formed subsequently is formed by etching back the initial step layer 170, the interface performance between the step layer and the isolation layer 140 is better, and the step layer has high density and excellent performance. Therefore, the pseudo gate structure formed on the step layer subsequently has good stability, and the pseudo gate structure is prevented from contacting the fin portion 120, so that the electrical isolation effect of the pseudo gate structure is improved, and the performance of the formed fin field effect transistor is improved.
The isolation layer 140 provides support for the initial step layer 170 and subsequently formed step layers, and serves to electrically isolate the fins 120 from each other in the first direction AA 1.
In this embodiment, the isolation material layer 130 is made of silicon oxide, however, the isolation material layer 130 usually contains hydrogen, and during the uv curing 160, the uv light can break Si-H bonds to form Si-Si bonds, thereby forming a dense initial step layer 170, where the initial step layer 170 is a nitrogen-doped silicon-rich oxide layer.
Specifically, the step of hardening the isolation layer 140 exposed at the bottom of the first opening by the ultraviolet hardening treatment 160 includes: and carrying out light radiation on the isolation layer 140 exposed at the bottom of the first opening by using an ultraviolet lamp, wherein the wavelength range of light emitted by the ultraviolet lamp is 200-600 nm.
In order to achieve a good ultraviolet curing treatment effect, in this embodiment, the wavelength range of the light emitted by the ultraviolet lamp is 200-.
It should be noted that the time for the uv curing treatment 160 is not necessarily too long, nor too short. If the uv curing treatment 160 is too long, the fin portion 120 is easily damaged, so that the formed transistor has poor electrical properties; if the time of the uv curing treatment 160 is too short, the thickness of the initial step layer 170 is too thin, and it is difficult to achieve that the bottom surface of the initial step layer 170 is lower than the top surface of the first mask layer 110, so that it is difficult to form a step layer whose top surface is higher than the top surface of the fin 120 or flush with the top surface of the fin 120 by etching back, and it is difficult to form a pseudo gate structure with high stability, thereby affecting the performance of the transistor. Therefore, in this embodiment, the time of the ultraviolet curing treatment 160 is 3 to 6 min.
Referring to fig. 11, the ultraviolet absorbing layer 150 is removed (as shown in fig. 10).
In this embodiment, the step of removing the ultraviolet absorption layer 150 includes: and removing the ultraviolet absorption layer 150 by using a nitric acid solution, a mixed solution of sulfuric acid and hydrogen peroxide or a mixed solution of hydrochloric acid and hydrogen peroxide.
In addition, the forming method further includes: after the uv absorbing layer 150 is removed, a steam annealing process is performed on the isolation material layer 130, the isolation layer 140 and the initial step layer 170.
Since the isolation material layer 130, the isolation layer 140 and the initial step layer 170 are formed by a cvd process, and the density still needs to be improved, the density of the isolation material layer 130, the isolation layer 140 and the initial step layer can be further improved during the steam annealing process, thereby providing a process basis for the subsequent formation of an isolation structure with high density and a step layer.
Referring to fig. 12 and 13, the isolation material layer 130 is etched back to form an isolation structure 180, the isolation structure exposes a portion of the sidewall surface of the fin 120, the initial step layer 170 is thinned during the etching back of the isolation material layer 130 to form a step layer 190, and the removal rate of the isolation material layer 130 in the etching back step is greater than the removal rate of the initial step layer 170.
Referring to fig. 12, the forming method further includes: before the etching back step is performed, the top surfaces of the initial step layer 170 and the isolation material layer 130 are made flush with the surface of the first mask layer 110 by a planarization process.
Specifically, the step of the planarization process treatment comprises the following steps: the isolation material layer 130 (refer to fig. 11) and the initial step layer 170 above the top surface of the first mask layer 110 are removed.
In the planarization process, the surface of the first mask layer 110 serves as a stop position of the planarization process, so that the initial step layer 170 higher than the top surface of the first mask layer 110 can be removed, a process foundation is provided for forming a step layer by a subsequent etching-back process, and the first mask layer 110 can protect the fin portion 120, so that the fin portion 120 has good top surface performance.
In this embodiment, the planarization process is performed by chemical mechanical polishing.
The isolation structures 180 are used for electrical isolation between the fins 120. In this embodiment, the isolation structure 180 is made of silicon oxide.
The step layer 190 has high density and excellent performance, and provides a stable support platform for a pseudo gate structure formed on the step layer 190 subsequently, so that the stability of the pseudo gate structure is improved, the pseudo gate structure is prevented from contacting the fin portion 120, the electrical isolation effect of the pseudo gate structure is improved, and the performance of the formed fin field effect transistor is improved. The material of the step layer 190 may be a silicon-rich oxide layer. In this embodiment, the step layer 190 is made of a nitrogen-doped silicon-rich oxide layer.
Since the fin field effect transistor is to be formed, the isolation material layer 130 is etched back to remove a portion of the thickness of the isolation material layer 130 to form the isolation structure 180, so as to expose a portion of the sidewall surface of the fin 120, and thus a gate structure formed subsequently can cover a portion of the sidewall surface of the fin 120.
Specifically, the step of etching back the isolation material layer 130 includes etching back the isolation material layer 130 by using a fluorine-containing gas. In this embodiment, the fluorine-containing gas includes C4F6Or C4F8A gas.
Since the surface of the initial step layer 170 is exposed, the initial step layer 170 is also thinned during the etching back of the isolation material layer 130, forming a step layer 190. In addition, since the density of the initial step layer 170 is high, in the etching back step, the etching rate of the etching back on the initial step layer 170 is smaller than that on the isolation material layer 130, so that the removal amount of the initial step layer 170 in the etching back process is smaller than that on the isolation material layer 130, so that the surface of the formed step layer 190 is higher than that of the isolation structure 180.
In the step of forming the step layer 190, a sum of thicknesses of the step layer 190 and the isolation layer 140 is not too high or too low. If the sum of the thicknesses of the step layer 190 and the isolation layer 140 is too low, that is, the thickness of the formed step layer 190 is too thin, the cost and difficulty of the etching process are increased, and the stability of the subsequently formed pseudo gate structure is poor, so that the electrical isolation effect of the pseudo gate structure is difficult to improve, and the performance of the formed fin field effect transistor is difficult to improve; if the sum of the thicknesses of the step layer 190 and the isolation layer 140 is too high, and the thickness of the correspondingly formed isolation structure 180 is too high, it is difficult to expose a proper amount of the sidewall surface of the fin portion 120, so that it is difficult to subsequently form a gate structure with excellent performance, and further it is difficult to form a fin field effect transistor with excellent performance. Therefore, in the present embodiment, the sum of the thicknesses of the step layer 190 and the isolation layer 140 is 150-200 nm.
Referring to fig. 14 and 15, a gate structure 200 is formed on the fin 120, the gate structure 200 crosses the fin 120 and covers a portion of the top and sidewall surfaces of the fin 120, and a dummy gate structure 210 is formed on the step layer 190 during the formation of the gate structure 200.
Referring to fig. 14, the forming method further includes: before the gate structure 200 and the dummy gate structure 210 are formed, the first mask layer 110 is removed (refer to fig. 13).
In this embodiment, the first mask layer 110 is made of silicon nitride. The first mask layer 110 is removed by a wet etching process. Specifically, the etching solution adopted by the wet etching process is a phosphoric acid solution.
In other embodiments, a dry etching process may also be employed; or, the first mask layer is removed by a process combining a dry etching process and a wet etching process.
Referring to fig. 15, the forming process of the gate structure 200 and the dummy gate structure 210 includes: forming a gate material layer (not shown) on the fins 120 and the step layer 190, and forming a gate pattern layer (not shown) on the gate material layer, wherein the gate pattern layer is used for defining the size and the position of the gate structure 200 and the dummy gate structure 210; and etching the gate material layer by using the gate pattern layer as a mask to form the gate structure 200 and the dummy gate structure 210, wherein the gate structure 200 is located on the fin 120 and covers part of the top and part of the sidewall of the fin 120, and the dummy gate structure 210 is located on the step 190.
In this embodiment, the dummy gate structure 210 is a dummy gate structure 210 in a Single Diffusion Barrier (SDB) process, and is used to implement isolation between source and drain doped regions formed in the fin portion 120 subsequently, and avoid a problem of bridging between the source and drain doped regions.
Accordingly, the present invention further provides a fin field effect transistor, and with continued reference to fig. 15, a schematic cross-sectional structure diagram of the fin field effect transistor is shown.
The fin field effect transistor of the present embodiment includes: the substrate 100 is provided with a plurality of fin portions 120 arranged in an array manner, the extending direction of the fin portions 120 is a first direction, and the direction perpendicular to the extending direction of the fin portions 120 is a second direction; an isolation layer 140 on the substrate 110 between the first direction fins 120; a step layer 190 on the isolation layer 140; isolation structures 180 between fins 120, wherein the isolation structures 180 expose a portion of sidewall surfaces of the fins 120, and a top surface of the isolation structures 180 is lower than a top surface of the step layer 190; a gate structure 200 on the fin 120, the gate structure 200 crossing the fin 120 and covering a portion of the top and sidewall surfaces of the fin 120; a dummy gate structure 210 on the mesa layer 190.
The substrate 100 is used to provide a process platform for subsequently forming devices. In this embodiment, the transistor is a fin field effect transistor, so the substrate 100 has a plurality of fins 120 arranged in an array. The extending direction of the fins 120 is a first direction, and the direction perpendicular to the extending direction of the fins 120 is a second direction.
The substrate 100 is made of silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide; the substrate 100 may also be a silicon-on-insulator substrate 100, a germanium-on-insulator substrate, or a germanium-on-insulator substrate. In this embodiment, the substrate 100 is a silicon substrate, and the corresponding fin portion 120 is made of silicon.
An isolation layer 140 on the substrate 110 between the first direction fins 120. The isolation layer 140 is used to provide support for the step layer 190 formed on the isolation layer 140, and the isolation layer 140 is also used to electrically isolate the fins 120 along the extending direction of the fins 120.
The material of the isolation layer 140 may be selected from silicon oxide, silicon nitride, silicon oxynitride, a low-K dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9), or an ultra-low-K dielectric material (dielectric constant less than 2.5). In this embodiment, the material of the isolation layer 140 is silicon oxide.
A step layer 190 on the isolation layer 140, a top surface of the step layer 190 being higher than a top surface of the fins 120 or flush with the top surface of the fins 120.
The stage 190 has high density and excellent performance, and provides a stable support platform for the dummy gate structure 210 on the stage 190, so that the stability of the dummy gate structure 210 is improved, the dummy gate structure 210 is prevented from contacting the fin portion 120, the electrical isolation effect of the dummy gate structure 210 is improved, and the performance of the formed fin field effect transistor is improved.
The material of the step layer 190 may be a silicon-rich oxide layer. In this embodiment, the step layer 190 is made of a nitrogen-doped silicon-rich oxide layer.
It should be noted that the sum of the thicknesses of the step layer 190 and the isolation layer 140 should not be too high or too low. If the sum of the thicknesses of the step layer 190 and the isolation layer 140 is too low, that is, the thickness of the step layer 190 is too thin, this will increase the process cost and difficulty, and cause the stability of the dummy gate structure on the step layer 190 to be poor, so that it is difficult to improve the electrical isolation effect of the dummy gate structure, and further difficult to improve the performance of the formed fin field effect transistor; if the sum of the thicknesses of the step layer 190 and the isolation layer 140 is too high, and the thickness of the correspondingly formed isolation structure 180 is too high, it is difficult to expose a proper amount of the sidewall surface of the fin portion 120, and thus it is difficult to form a gate structure with excellent performance, and further it is difficult to form a fin field effect transistor with excellent performance. Therefore, in the present embodiment, the sum of the thicknesses of the step layer 190 and the isolation layer 140 is 150-200 nm.
Isolation structures 180 are located between fins 120, wherein the isolation structures 180 expose a portion of the sidewall surfaces of the fins 120, and a top surface of the isolation structures 180 is lower than a top surface of the step layer 190.
The isolation structures 180 are used for electrical isolation between the fins 120. In this embodiment, the isolation structure 180 is made of silicon oxide.
The material of the isolation structure 180 may be selected from silicon oxide, silicon nitride, silicon oxynitride, a low-K dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9), or an ultra-low-K dielectric material (dielectric constant less than 2.5). In this embodiment, the isolation structure 180 is made of silicon oxide.
A gate structure 200 on the fin 120, the gate structure 200 crossing the fin 120 and covering a portion of the top and sidewall surfaces of the fin 120; a dummy gate structure 210 on the mesa layer 190.
In this embodiment, the dummy gate structure 210 is a dummy gate structure 210 in a Single Diffusion Barrier (SDB) process, and is used to implement isolation between source and drain doped regions formed in the fin portion 120 subsequently, and avoid a problem of bridging between the source and drain doped regions.
In summary, the ultraviolet absorption layer having the first opening is formed on the isolation layer, and the first opening exposes the top surface of the isolation layer; hardening the isolation layer exposed from the bottom of the first opening through ultraviolet hardening treatment to form an initial step layer; then, etching back the isolation material layer and the initial step layer to form an isolation structure and a step layer; and forming a grid structure and a pseudo-grid structure on the fin part and the step layer respectively. Because the density of the initial step layer formed by ultraviolet hardening treatment is higher, in the back etching step, the etching rate of the back etching to the initial step layer is lower than that to the isolation material layer, so that the removal amount of the initial step layer in the back etching process is lower than that to the isolation material layer, and the surface of the formed step layer can be higher than that of the isolation structure. In addition, in the prior art, an initial step layer is usually formed by a high aspect ratio process, and then the initial step layer is subjected to high-temperature thermal hardening treatment to form a step layer with higher density. Compared with the prior art, the high-density step layer is formed through ultraviolet hardening treatment and is not subjected to high-temperature treatment, so that the thermal budget of the transistor is reduced, performance degradation of the device can be caused by excessive thermal budget, and the electrical performance and stability of the transistor are improved.
In addition, the step layer is formed by hardening the isolation layer, so that the interface performance of the step layer and the isolation layer is good, the density of the step layer is high, and the performance is excellent. Therefore, the pseudo gate structure formed on the step layer has good stability, and the pseudo gate structure is prevented from contacting with the fin part, so that the electric isolation effect of the pseudo gate structure is improved, and the performance of the formed fin field effect transistor is improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (17)

1. A method for forming a fin field effect transistor (FinFET), comprising:
forming a substrate, wherein the substrate is provided with a plurality of fin parts which are arranged in an array manner, the extending direction of the fin parts is a first direction, and the direction which is vertical to the extending direction of the fin parts is a second direction;
forming isolation material layers between the fin parts in the first direction and between the fin parts in the second direction, wherein the isolation material layers between the fin parts in the first direction are isolation layers;
forming an ultraviolet absorption layer covering the isolation material layer, wherein the ultraviolet absorption layer is provided with a first opening, and the first opening exposes the top surface of the isolation layer;
hardening the isolation layer exposed from the bottom of the first opening through ultraviolet hardening treatment to form an initial step layer;
removing the ultraviolet absorption layer;
etching the isolation material layer back to form an isolation structure, exposing partial side wall surfaces of the fins, thinning the initial step layer to form a step layer in the process of etching the isolation material layer back, wherein the removal rate of the isolation material layer in the etching back step is greater than that of the initial step layer;
and forming a gate structure on the fin part, wherein the gate structure stretches across the fin part and covers the top of the fin part and the surface of the side wall, and a pseudo gate structure is formed on the step layer in the process of forming the gate structure.
2. The method of claim 1, wherein the UV absorbing layer is a nanoparticle layer.
3. The method of claim 2, wherein the nanoparticles are zinc oxide nanoparticles or titanium dioxide nanoparticles.
4. The method of claim 3, wherein forming the UV absorbing layer comprises: the zinc oxide nanoparticles are prepared by an alcohol solution synthesis method.
5. The method of claim 4, wherein the alcohol solution is methanol, ethanol, or propanol.
6. The method of claim 2, wherein the nanoparticle has a particle size of 1-4 nm.
7. The method of claim 1, wherein the UV absorber layer has a thickness of about 300-800 angstroms.
8. The method of claim 1, wherein the UV cure time is 3-6 min.
9. The method of claim 1, wherein forming the substrate comprises: providing a substrate; forming a first mask layer on the substrate; etching the substrate by taking the first mask layer as a mask to form a substrate and a plurality of fin parts arranged in an array form on the substrate;
the forming method further includes: after the step of removing the ultraviolet absorption layer and before the step of etching back, enabling the initial step layer and the isolation material layer to be flush with the surface of the first mask layer through a planarization process;
the forming method further includes: and removing the first mask layer after the back etching step and before forming the gate structure.
10. The method of claim 1, wherein hardening the exposed isolation layer at the bottom of the first opening by an ultraviolet hardening process comprises: and carrying out light radiation on the isolation layer exposed at the bottom of the first opening by adopting an ultraviolet lamp, wherein the wavelength range of light emitted by the ultraviolet lamp is 200-600 nm.
11. The method of claim 10, wherein the wavelength of light emitted by the UV lamp is in the range of 200-400 nm.
12. The method of forming the fin field effect transistor of claim 1, further comprising: after the ultraviolet absorption layer with the first opening is formed and before ultraviolet hardening treatment is carried out, silicon ion implantation and nitrogen ion implantation are carried out on the ultraviolet absorption layer and the isolation layer exposed from the bottom of the first opening.
13. The method of claim 12, wherein the silicon ion implantation is performed at a dose in a range from 5E14 atm/cm to 5E16atm/cm2The energy range is 5-10 keV.
14. The method of claim 12, wherein the nitrogen ion implantation is performed at a dose in a range from 5E14 atm/cm to 5E16atm/cm2The energy range is 5-10 keV.
15. The method of claim 1, wherein in the step of forming the step layer, the sum of the step layer and the spacer layer thickness is 150-200 nm.
16. The method of forming the fin field effect transistor of claim 15, further comprising: and after the ultraviolet absorption layer is removed and before the isolation layer is etched back, carrying out steam annealing process treatment on the isolation material layer, the isolation layer and the initial stage layer.
17. The method of claim 1, wherein the isolation material layer is silicon dioxide and the step layer is a silicon-rich oxide layer.
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