CN107731751B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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CN107731751B
CN107731751B CN201610662867.2A CN201610662867A CN107731751B CN 107731751 B CN107731751 B CN 107731751B CN 201610662867 A CN201610662867 A CN 201610662867A CN 107731751 B CN107731751 B CN 107731751B
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isolation
forming
layer
substrate
barrier layer
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CN107731751A (en
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周飞
周鸣
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate, and forming a plurality of fin parts on the substrate; filling an isolation material between the adjacent fin parts; removing the second fin portion and the second isolation layer to form an opening; forming a barrier layer on the side wall of the opening, wherein the density of the barrier layer is greater than that of the first isolation layer; an isolation structure is formed in the opening. In the invention, after the second fin part and the second isolation layer are removed to form the opening, the barrier layer is formed on the side wall of the opening, and the density of the barrier layer is greater than that of the first isolation layer. Due to the fact that the density of the blocking layer is high, diffusion of oxygen atoms in the first isolation layer can be effectively blocked, contact between the oxygen atoms and the first fin portion is reduced, the possibility that the first fin portion is oxidized is reduced, and therefore uniformity of the fin portion in the formed semiconductor structure can be effectively improved.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
As the integrated circuit is developed to the ultra-large scale integrated circuit, the circuit density inside the integrated circuit is increased, the number of the contained components is increased, and the sizes of the components are reduced. As the size of MOS devices decreases, the channels of MOS devices shrink accordingly. Due to the shortened channel, the graded channel approximation of MOS devices is no longer true, and various adverse physical effects (especially short channel effects) are highlighted, which degrade device performance and reliability, limiting further device scaling.
In order to further reduce the size of the MOS device, a multi-plane gate field effect transistor structure is developed to improve the control capability of the gate of the MOS device and suppress the short channel effect. The finfet is a common multi-plane gate transistor.
The fin field effect transistor is of a three-dimensional structure and comprises a substrate, wherein one or more protruding fins are formed on the substrate, and insulating isolation components are arranged among the fins; a gate spans the fin and covers the top and sidewalls of the fin. Since such a three-dimensional structure is greatly different from a transistor of a conventional planar structure, part of the process may have a great influence on the electrical properties of the formed device if it is not operated properly.
The source region, the drain region and the channel of the fin field effect transistor are all located in the fin portion, and the performance of the formed transistor is directly influenced by the forming process of the fin portion. However, the semiconductor structure formed in the prior art has the problem of insufficient fin uniformity.
Disclosure of Invention
The present invention provides a semiconductor structure and a method for forming the same, which can improve the uniformity of a fin portion and the performance of the formed semiconductor structure.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a plurality of first areas and second areas positioned between the adjacent first areas; forming a plurality of fin parts on the substrate, wherein the fin parts on the substrate in the first region are first fin parts, and the fin parts on the substrate in the second region are second fin parts; filling an isolation material between the adjacent fin parts to form an isolation layer, wherein the isolation layer positioned on the first region substrate is a first isolation layer, and the isolation layer positioned on the second region substrate is a second isolation layer; removing the second fin part and the second isolation layer to form an opening, wherein the side wall of the opening exposes the first isolation layer, and the bottom of the opening exposes the substrate of the second region; forming a barrier layer on the side wall of the opening, wherein the density of the barrier layer is greater than that of the first isolation layer; an isolation structure is formed in the opening.
Optionally, the step of forming a barrier layer on the sidewall of the opening includes: and forming the barrier layer by adopting a plasma treatment mode.
Optionally, in the step of forming the barrier layer by using a plasma treatment, the plasma treatment uses a nitrogen-containing gas.
Optionally, the nitrogen-containing gas comprises nitric oxide, nitrous oxide or ammonia.
Optionally, in the step of forming the barrier layer on the sidewall of the opening by using a nitrogen-containing gas, the process parameters include: the process gas pressure is in the range of 1mTorr to 500mTorr, the process gas flow is in the range of 10sccm to 1000sccm, the process temperature is in the range of 20 ℃ to 300 ℃, and the process time is in the range of 2s to 500 s.
Optionally, in the step of forming the isolation layer, the isolation layer is made of silicon oxide; in the step of forming the barrier layer, the barrier layer is a nitrogen-containing barrier layer.
Optionally, in the step of forming the barrier layer, the material of the barrier layer is silicon oxynitride.
Optionally, in the step of forming a barrier layer on the sidewall of the opening, the thickness of the barrier layer is within
Figure BDA0001076551150000021
To
Figure BDA0001076551150000022
Within the range.
Optionally, the step of forming an isolation structure in the opening includes: filling an isolation material into the opening; and annealing the isolation material to form an isolation structure.
Optionally, the step of annealing the isolation material includes: the annealing treatment is performed by means of water vapor annealing.
Optionally, one or both of the step of forming the isolation layer and the step of forming the isolation structure includes: the isolation material is filled by means of fluid chemical vapor deposition.
Optionally, in the step of filling the isolation material by means of fluid chemical vapor deposition, the isolation material is in a fluid state; in the step of annealing the isolation material to form the isolation structure, the annealing cures the isolation material in a fluid state.
Optionally, the isolation material is a polymer containing one or more of Si-H bonds, and Si-O bonds.
Optionally, the step of removing the second fin portion and the second isolation layer to form an opening includes: and removing the second fin part and the second isolation layer in a dry etching mode, exposing the substrate of the second area and the side wall of the first isolation layer, and forming the opening.
Optionally, in the step of providing a substrate, the substrate in the first region is used to form a semiconductor device having a fin portion, and the substrate in the second region is used to form an isolation structure.
Optionally, after the step of forming the isolation structure, the forming method further includes: and removing partial thicknesses of the isolation structure, the first isolation layer and the barrier layer to expose partial surfaces of the top and the side wall of the first fin portion. .
Accordingly, the present invention also provides a semiconductor structure comprising:
a substrate including a plurality of first regions and second regions located between adjacent first regions; the isolation layer is filled between the adjacent fin parts; an isolation structure on the second region substrate; a barrier layer between the isolation structure and the isolation layer, the barrier layer having a density greater than a density of the isolation layer.
Optionally, the barrier layer is a nitrogen-containing barrier layer; the isolation layer is made of oxide.
Optionally, the material of the barrier layer is silicon oxynitride.
Optionally, the thickness of the barrier layer is within
Figure BDA0001076551150000031
To
Figure BDA0001076551150000032
Within the range.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the invention, after the second fin part and the second isolation layer are removed to form the opening, the barrier layer is formed on the side wall of the opening, and the density of the barrier layer is greater than that of the first isolation layer. Due to the fact that the density of the blocking layer is high, diffusion of oxygen atoms in the first isolation layer can be effectively blocked, contact between the oxygen atoms and the first fin portion is reduced, the possibility that the first fin portion is oxidized is reduced, and therefore uniformity of the fin portion in the formed semiconductor structure can be effectively improved.
Drawings
FIGS. 1-3 are schematic cross-sectional views of a semiconductor structure forming method illustrating steps of the method;
FIGS. 4-13 are schematic cross-sectional views of steps of a method for forming a semiconductor structure according to an embodiment of the present invention;
FIG. 14 is a cross-sectional view of a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As can be seen from the background art, the prior art fin formation process has a problem of insufficient uniformity. Now combine the formation process analysis uniformity among the prior art not enough reason of problem:
referring to fig. 1-3, cross-sectional views of a semiconductor structure forming method corresponding to various steps are shown.
As shown in fig. 1, a substrate 10 is first provided, where a surface of the substrate 10 has a plurality of fins 11; an isolation layer 12 is formed between adjacent fins 11. The substrate 10 includes a plurality of first regions 10a and second regions 10b located between adjacent first regions 10a, the first regions 10a being used to form semiconductor devices, and the second regions 10b being used to form isolation structures.
As shown in fig. 2, the fin 11 on the surface of the substrate 10 in the second region 10b and the isolation layer 12 on the surface of the substrate 10 in the second region 10b are removed to form a first opening 13.
Referring to fig. 3, a precursor is filled into the first opening 13, and the precursor is annealed to form an isolation structure 14.
As the size of the semiconductor device decreases, the distance between adjacent fins 11 decreases, and the size of the first opening 13 also decreases. In order to improve the filling effect of the isolation layer 12 and the isolation structure 14 and reduce the occurrence of cavities, the isolation layer 12 and the isolation structure 14 are often formed by means of fluid chemical vapor deposition.
Therefore, the spacer material filled in the first opening 13 is in a fluid state, and the spacer material is cured by annealing to form the spacer structure 14. The annealing treatment often includes a water vapor annealing treatment, and on the other hand, the density of the isolation layer 12 formed by the fluid chemical vapor deposition method is low, and the barrier property is poor. Therefore, during the annealing process, oxygen atoms easily penetrate through the isolation layer 12 to contact the fin 11 (as shown by the circle 15 in fig. 3) located near the edge of the second region 10b of the first region 10a, so that the fin 11 is oxidized. Subsequently, when the heights of the isolation layer 12 and the isolation structure 14 are reduced to expose the top and sidewall surfaces of the fin 11, the oxidized fin 11 is easily partially removed, so that the size is reduced, which affects the size uniformity of the formed fin 11 and the performance of the formed semiconductor device.
To solve the above technical problem, the present invention provides a method for forming a semiconductor structure, including:
providing a substrate, wherein the substrate comprises a plurality of first areas and second areas positioned between the adjacent first areas; forming a plurality of fin parts on the substrate, wherein the fin parts on the substrate in the first region are first fin parts, and the fin parts on the substrate in the second region are second fin parts; filling an isolation material between the adjacent fin parts to form an isolation layer, wherein the isolation layer positioned on the first region substrate is a first isolation layer, and the isolation layer positioned on the second region substrate is a second isolation layer; removing the second fin part and the second isolation layer to form an opening, wherein the side wall of the opening exposes the first isolation layer, and the bottom of the opening exposes the substrate of the second region; forming a barrier layer on the side wall of the opening, wherein the density of the barrier layer is greater than that of the first isolation layer; an isolation structure is formed in the opening.
According to the invention, after the second fin part and the second isolation layer are removed to form the opening, the barrier layer is formed on the side wall of the opening, and the density of the barrier layer is greater than that of the first isolation layer. Due to the fact that the density of the blocking layer is high, diffusion of oxygen atoms in the first isolation layer can be effectively blocked, contact between the oxygen atoms and the first fin portion is reduced, the possibility that the first fin portion is oxidized is reduced, and therefore uniformity of the fin portion in the formed semiconductor structure can be effectively improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Referring to fig. 4 to 13, schematic cross-sectional structures corresponding to steps of a semiconductor structure forming method according to an embodiment of the invention are shown.
Referring to fig. 4, a substrate 100 is provided, the substrate 100 including a plurality of first regions 100a and second regions 100b located between adjacent first regions 100 a.
The substrate 100 is an operation platform for a subsequent semiconductor process; the substrate 100 of the first region 100a is used to form a semiconductor device having a fin, and the substrate 100 of the second region 100b is used to form an isolation structure.
In this embodiment, the substrate 100 includes a PMOS region for forming a PMOS transistor and an NMOS region for forming an NMOS transistor, and an isolation region between the PMOS region and the NMOS region for electrical isolation.
The PMOS region is used for forming a P-type fin field effect transistor, the NMOS region is used for forming an N-type fin field effect transistor, and the isolation region is used for forming an isolation structure for realizing electrical isolation between the PMOS region and the NMOS region. The first region 100a includes the PMOS region and the NMOS region, and the second region 100b includes the isolation region.
Referring to fig. 5, a plurality of fins 110 located on the substrate 100 are formed, where a fin located on the substrate 100 in the first region 100a is a first fin 110a, and a fin located on the substrate 100 in the second region 100b is a second fin 110 b.
Since the second region 100b is used to form an isolation structure, the second fin 110b needs to be removed later. Specifically, the number of the second fins 110b on the surface of the substrate 100 in the second region 100b is greater than or equal to 1.
In this embodiment, the substrate 100 and the fin 110 are formed by etching a substrate. Referring to fig. 4 and 5 in combination, therefore, the steps of providing the substrate 100 and forming the fin 110 include: providing a substrate sub; and etching the substrate sub to form the substrate 100 and a plurality of fin portions 110 on the surface of the substrate 100.
Specifically, referring to fig. 4, a substrate sub is provided.
The substrate sub is used for providing an operation platform for subsequent processes and etching to form the fin portion 110. The material of the substrate sub is selected from monocrystalline silicon, polycrystalline silicon or amorphous silicon; the substrate sub may also be selected from silicon, germanium, gallium arsenide or silicon germanium compounds; the substrate sub may also be another semiconductor material. In this embodiment, the base sub material is monocrystalline silicon, so that the substrate 100 and the fin portion 110 are both made of monocrystalline silicon.
In other embodiments of the present invention, the substrate may also be selected to have an epitaxial layer or a silicon-on-epitaxial layer structure. Specifically, the substrate may include a substrate and a semiconductor layer on a surface of the substrate. The semiconductor layer may be formed on the substrate surface using a selective epitaxial deposition process. The substrate can be a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator substrate, a germanium-on-insulator substrate, a glass substrate, or a III-V compound substrate, such as a gallium nitride substrate or a gallium arsenide substrate; the material of the semiconductor layer is silicon, germanium, silicon carbide, silicon germanium or the like. The selection of the substrate and the semiconductor layer is not limited, and the substrate suitable for the process requirement or easy integration and the material suitable for forming the fin part can be selected. And the thickness of the semiconductor layer can be controlled through an epitaxial process, so that the height of the formed fin part can be accurately controlled.
Then, referring to fig. 5, the substrate sub is etched to form the substrate 100 and the fin 110 on the surface of the substrate 100.
The step of etching the substrate sub to form the substrate 100 and the fin 110 on the surface of the substrate 100 includes: forming a patterned mask 102 on the surface of the substrate sub; and etching the substrate sub by taking the patterned mask 102 as a mask to form the substrate 100 and the fin part 110 on the surface of the substrate 100.
The patterned mask 102 is used to define the location and dimensions of the fins 110. The step of forming the patterned mask 102 includes: forming a first mask material layer on the surface of the substrate sub; forming a patterning layer on the surface of the first mask material layer; and etching the first mask material layer by taking the patterning layer as a mask until the surface of the substrate sub is exposed to form the mask 102. Specifically, the mask 102 is made of silicon nitride.
It should be noted that, in this embodiment, before the step of forming the patterned mask 102, the forming method further includes forming a buffer layer 101 on the surface of the substrate sub to reduce lattice mismatch between the mask 102 and the substrate sub. Specifically, in this embodiment, the material of the buffer layer 101 is an oxide.
The patterned layer may be a patterned photoresist layer formed using a coating process and a photolithography process. In addition, in order to reduce the feature size of the fins and the distance between adjacent fins, the patterning layer can be formed by adopting a multiple patterning mask process. The multiple patterning mask process comprises the following steps: a Self-aligned Double patterning (SaDP) process, a Self-aligned Triple patterning (Self-aligned Triple patterning) process, or a Self-aligned quadruple patterning (SaDDP) process.
And the process for etching the substrate sub is an anisotropic dry etching process. The sidewalls of the formed fins 110 are thus perpendicular or oblique with respect to the surface of the substrate 100, and when the sidewalls of the fins 110 are oblique with respect to the substrate 100 surface, the bottom dimension of the fins 110 is larger than the top dimension.
It should be noted that, in the process of forming the fin portion 110, there may be damage or minute unevenness on the surface of the etched semiconductor substrate, and in order to repair the damage or the unevenness on the surface of the semiconductor substrate to improve the performance of the formed semiconductor structure, in this embodiment, after the step of forming the fin portion 110, the forming method further includes: a repair oxide layer (not shown) is formed on the surface of the substrate 100 and the fin 110. The repair oxide layer may also round off sharp corners of the surfaces of the substrate 100 and the fin 110 and act as a buffer layer between a subsequently formed film and the substrate 100 and the fin 110 to reduce lattice mismatch. Specifically, the repair oxide layer may be formed by chemical vapor deposition or thermal oxidation. However, in other embodiments of the present invention, the damage may be repaired by annealing the substrate and the fin portion without forming the repair oxide layer.
Referring to fig. 6 and 7, an isolation material is filled between adjacent fins 110 to form an isolation layer 120, where the isolation layer 120 on the substrate 100 in the first region 100a is a first isolation layer 120a, and the isolation layer 120 on the substrate 100 in the second region 100b is a second isolation layer 120 b.
The isolation layer 120 is used to achieve electrical isolation between adjacent fins 110. In this embodiment, the first isolation layer 120a is used to achieve electrical isolation between the first fins 110 a. The second isolation layer 120b is subsequently removed.
The material of the isolation layer 120 may be silicon oxide. Specifically, the step of forming the isolation layer 120 includes: as shown in fig. 6, an isolation material is filled between adjacent fins 110, and the top surface of the isolation material is higher than the top surface of the mask 102; as shown in fig. 7, the isolation material is planarized until the mask 102 is exposed.
In order to make the isolation layer 120 fully fill the gap between the adjacent fins 110 and reduce the generation of holes in the isolation layer 120, the step of filling the isolation layer 120 includes: the isolation material is filled by means of Fluid Chemical Vapor Deposition (FCVD).
Specifically, in the step of filling the isolation material by means of fluid chemical vapor deposition, the isolation material is in a fluid state, and the surface of the isolation material is higher than the surface of the mask 102. Therefore, the step of forming the isolation layer 120 further includes: the isolation material is annealed to form the isolation layer 120.
The isolation material is a polymer containing one or more polymers of Si-H bonds, Si-N bonds and Si-O bonds. Therefore, the density of the isolation layer 120 formed by solidifying the fluid-state isolation material through the annealing process is low, and the barrier property is poor.
Note that, as shown in fig. 7, in this embodiment, after the forming the isolation layer 120, the forming method further includes: the isolation layer 120 is planarized such that the top surface of the isolation layer 120 is flush with the top surface of the mask 102.
Referring to fig. 8, the second fin 110b (shown in fig. 7) and the second isolation layer 120b (shown in fig. 7) are removed to form an opening 140, wherein a sidewall of the opening 140 exposes the first isolation layer 120a and a bottom of the opening exposes the substrate 100 of the second region 100 b.
Since the second region 100b is used to form an isolation structure. The second fin 110b needs to be removed. In addition, the second isolation region 120b on the surface of the substrate 100 in the second region 100b is also removed.
Specifically, the second fin 110b and the second isolation layer 120b may be removed by a mask dry etching method, so as to expose the surface of the substrate 100 in the second region 100b and the sidewall of the first isolation layer 120 a.
In the step of forming the substrate 100, the number of the second fins 110b is greater than or equal to 1. Therefore, in the step of removing the second fins 110b, the number of the second fins 110b to be removed is greater than or equal to 1. Specifically, in the present embodiment, 2 of the second fins 110b on the surface of the substrate 100 in the second region 100b are removed.
In the present embodiment, the isolation region is located between the PMOS region and the NMOS region, that is, the second region 100b is located between the two first regions 100 a. Therefore, after the second fin 110b and the second isolation layer 120b are removed, the exposed sidewall of the first isolation layer 120a and the surface of the substrate 100 of the second region 100b enclose an opening 140.
Referring to fig. 9, a barrier layer 150 is formed on the sidewall of the opening 140, and the density of the barrier layer 150 is greater than that of the first isolation layer 120 a.
The blocking layer 150 is used for blocking diffusion of oxygen ions in the first isolation layer 120a in a subsequent process, thereby reducing the possibility of contact between the oxygen ions and the first fin portion 110a, reducing the probability of oxidation of the first fin portion 110a, and improving the uniformity of the fin portion in the formed semiconductor structure.
The density of the barrier layer 150 is greater than that of the first isolation layer 120a, so that the barrier layer 150 has a strong blocking capability, can effectively block the diffusion of oxygen ions, reduces the possibility of oxidation of the first fin portion 110a, and improves the uniformity of the fin portion in the formed semiconductor structure.
The step of forming the barrier layer 150 includes: the barrier layer 150 is formed on the sidewall of the opening 140 by plasma treatment. In this embodiment, in the step of forming the barrier layer 150 by plasma treatment, since the plasma treatment is performed using a nitrogen-containing gas, the barrier layer formed is a nitrogen-containing barrier layer. Wherein the nitrogen-containing gas comprises nitric oxide, nitrous oxide or ammonia gas
Specifically, in the step of forming the barrier layer 150 on the sidewall of the opening by using the nitrogen-containing gas, the process parameters include: the process gas pressure is in the range of 1mTorr to 500mTorr, the process gas flow is in the range of 10sccm to 1000sccm, the process temperature is in the range of 20 ℃ to 300 ℃, and the process time is in the range of 2s to 500 s.
Specifically, in this embodiment, the material of the isolation layer 120 is silicon oxide, that is, the material of the first isolation layer 120a is silicon oxide, and the material of the barrier layer 150 is silicon oxynitride. The compact silicon oxynitride barrier layer can effectively prevent the diffusion of oxygen ions.
It should be noted that if the thickness of the barrier layer 150 is too small, it is difficult to achieve the function of blocking the diffusion of oxygen atoms; if the thickness of the barrier layer 150 is too large, material waste is easily caused, and the process difficulty is increased. In this embodiment, the thickness of the barrier layer 150 is within
Figure BDA0001076551150000101
To
Figure BDA0001076551150000102
Within the range.
Referring to fig. 10 to 13, an isolation structure 160 is formed in the opening 140 (shown in fig. 9).
The isolation structure 160 is used to electrically isolate semiconductor devices on the substrate 100 adjacent to the first region 100 a. Specifically, in this embodiment, the isolation structure 160 is located between the PMOS region and the NMOS region as the first region 100a, so that the isolation structure 160 is used to realize electrical isolation between the two first regions 100a (i.e., the PMOS region and the NMOS region).
The isolation structure 160 is made of silicon oxide and may be formed by chemical vapor deposition. Furthermore, in order to ensure that the isolation structure 160 is sufficiently filled in the opening 140 and reduce the possibility of void formation in the isolation structure 160, the isolation structure 160 may be formed by fluid chemical vapor deposition.
Specifically, the step of forming the isolation structure 160 includes:
referring to fig. 10, the opening 140 (shown in fig. 9) is filled with a spacer material 160 f.
Specifically, in the step of filling the isolation material 160f, the isolation material 160f is filled by means of fluid chemical vapor deposition. The isolation material 160f is in a fluid state during the step of filling the isolation material 160f by means of fluid chemical vapor deposition.
The isolation material 160f is a polymer containing one or more of Si-H bonds, Si-N bonds, and Si-O bonds. The isolation material 160f in a fluid state is used for filling, so that the filling degree of the isolation material 160f to the opening 140 can be effectively improved, and the formation of a gap is reduced.
It should be noted that in the present embodiment, the top surface of the fin 110 further has the mask 102 thereon, so the top surface of the isolation material 160f is higher than the top surface of the mask 102.
Next, referring to fig. 11 in combination, the isolation material 160f is annealed to form the isolation structure 160.
The annealing process solidifies the isolation structure 160f in a fluid state, forming the isolation structure 160. Specifically, in this embodiment, the isolation structure 160 for isolating the PMOS and the NMOS is formed by annealing.
Specifically, the step of annealing the isolation material 160f includes: the annealing treatment is performed by means of water vapor annealing. Oxygen atoms can diffuse during annealing, particularly during water vapor annealing.
However, since the barrier layer 150 is formed on the sidewall of the first isolation layer 120a, the barrier layer 150 is dense, so that the diffusion of oxygen atoms in the first isolation layer 120a can be effectively inhibited, and the first fin portion 110a is prevented from being oxidized due to the contact of the diffused oxygen atoms with the first fin portion 110a, thereby effectively reducing the possibility of oxidation of the first fin portion 110a, and further effectively improving the uniformity of the fin portion in the formed semiconductor structure.
Referring to fig. 12 and 13, in the present embodiment, the substrate 100 in the first region 100a is used to form a finfet, so that a portion of the surface of the top and the sidewall of the first fin 110a needs to be exposed, so that a gate structure formed later can cover the sidewall and the top surface of the first fin 110 a. Therefore, after forming the isolation structure 160, the forming method further includes: a portion of the thickness of the isolation structure 160, the first isolation layer 120a, and the barrier layer 150 is removed, exposing a portion of the surface of the top and sidewalls of the first fin 110 a.
Specifically, the step of removing the partial thicknesses of the isolation structure 160, the first isolation layer 120a, and the barrier layer 150 includes:
it should be noted that, in this embodiment, the isolation structure 160 is further located on the top surfaces of the first isolation layer 120a and the first fin 110a, and the buffer layer 101 and the mask 102 are further sequentially formed on the top surface of the first fin 110 a. The isolation structure 160 thus also covers the first isolation layer 120a and the top surface of the mask 102.
Referring first to fig. 12, the isolation structure 160 is planarized to remove a portion of the thickness of the isolation structure 160.
In this embodiment, the isolation structure 160 is planarized by chemical mechanical polishing. The chemical mechanical polishing is stopped when the top surface of the mask 102 is exposed, so as to remove the isolation structures 160, the mask 102 and the buffer layer 101 on top of the fins 110, exposing the top surface of the fins 110.
Referring to fig. 13, the isolation structure 160, the first isolation layer 120a and the barrier layer 150 are etched back to expose the top and a portion of the sidewall surface of the first fin 110 a.
The isolation structure 160, the first isolation layer 120a, and the oxidation resistant layer 150 are partially removed by a back etching process to expose the top and a portion of the sidewall of the first fin 110 a. The specific processes for etching back the isolation structure 160 and the isolation layer 120 are the same as those in the prior art, and the detailed description of the present invention is omitted here.
Correspondingly, the invention also provides a semiconductor structure.
Referring to fig. 14, a cross-sectional structure diagram of an embodiment of a semiconductor structure of the invention is shown.
As shown in fig. 14, the semiconductor structure includes:
a substrate 200, the substrate 200 including a plurality of first regions 200a and second regions 200b located between adjacent first regions 200 a; a plurality of fins 210 on the substrate 200 in the first region 200a and an isolation layer 220 filled between adjacent fins 210; an isolation structure 260 on the substrate 200 in the second region 200 b; a barrier layer 250 between the isolation structure 260 and the isolation layer 220, the barrier layer 250 having a density greater than a density of the isolation layer 220.
The substrate 200 is an operation platform for subsequent semiconductor processes; the first region 200a is used to form a semiconductor structure having fins, and the second region 200b is used to form a semiconductor structure without fins. Fin 210 is used to form a finfet.
In this embodiment, the substrate 200 includes a PMOS region, an NMOS region, and an isolation region between the PMOS region and the NMOS region. The PMOS region is used for forming a PMOS transistor, the NMOS region is used for forming an NMOS transistor, and the isolation region is used for realizing electric isolation between the PMOS region and the NMOS region.
The PMOS region is used for forming a P-type fin field effect transistor, the NMOS region is used for forming an N-type fin field effect transistor, and the isolation region is used for forming an isolation structure for realizing electrical isolation between the PMOS region and the NMOS region. The first region 200a includes the PMOS region and the NMOS region, and the second region 200b includes the isolation region.
The isolation layer 220 and the isolation structure 260 are used to achieve electrical isolation. Specifically, the isolation layer 220 is used for realizing electrical isolation between adjacent fins 210; the isolation structure 260 is used to achieve electrical isolation between semiconductor devices on the substrate 200 in adjacent first regions 200 a.
In this embodiment, the second region 200b is an isolation region and is located between the PMOS region and the NMOS region that are the first regions 200a, so that the isolation structure 260 on the surface of the substrate 200 of the second region 200b is used to realize electrical isolation between the two first regions 200a (i.e., the PMOS region and the NMOS region). Specifically, the isolation layer 220 and the isolation structure 260 are made of silicon oxide.
The barrier layer 250 is used to prevent oxygen atoms from diffusing into the isolation layer 220 during the process of forming the isolation structure 260, so as to avoid contact between oxygen atoms and the fin 210, reduce the possibility of oxidation of the fin 210, and improve the uniformity of the fin 210. In this embodiment, the barrier layer 250 is a nitrogen-containing barrier layer. Specifically, the material of the barrier layer 250 is silicon oxynitride.
It should be noted that if the thickness of the barrier layer 250 is too small, it is difficult to achieve the function of blocking the diffusion of oxygen atoms; if the thickness of the barrier layer 250 is too large, material waste is easily caused, and the process difficulty is increased. In this embodiment, the thickness of the barrier layer 250 is within
Figure BDA0001076551150000131
To
Figure BDA0001076551150000132
Within the range.
In summary, in the present invention, after the second fin portion and the second isolation layer are removed to form the opening, a blocking layer is formed on the sidewall of the opening, and the density of the blocking layer is greater than that of the first isolation layer. Due to the fact that the density of the blocking layer is high, diffusion of oxygen atoms in the first isolation layer can be effectively blocked, contact between the oxygen atoms and the first fin portion is reduced, the possibility that the first fin portion is oxidized is reduced, and therefore uniformity of the fin portion in the formed semiconductor structure can be effectively improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (17)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a plurality of first areas and second areas positioned between the adjacent first areas;
forming a plurality of fin parts on the substrate, wherein the fin parts on the substrate in the first region are first fin parts, and the fin parts on the substrate in the second region are second fin parts;
filling an isolation material between the adjacent fin parts to form an isolation layer, wherein the isolation layer positioned on the first region substrate is a first isolation layer, and the isolation layer positioned on the second region substrate is a second isolation layer;
removing the second fin part and the second isolation layer to form an opening, wherein the side wall of the opening exposes the first isolation layer, and the bottom of the opening exposes the substrate of the second region;
forming a barrier layer on the side wall of the opening, wherein the barrier layer only covers the first isolation layers on two sides of the opening, and the density of the barrier layer is greater than that of the first isolation layers;
forming an isolation structure in the opening, comprising: filling an isolation material into the opening; performing water vapor annealing treatment on the isolation material to form an isolation structure, wherein the barrier layer is used for inhibiting the diffusion of oxygen atoms in the first isolation layer in the water vapor annealing treatment process;
and removing partial thicknesses of the isolation structure, the first isolation layer and the barrier layer to expose partial surfaces of the top and the side wall of the first fin portion.
2. The method of forming as claimed in claim 1, wherein the step of forming a barrier layer on the sidewall of the opening includes: and forming the barrier layer by adopting a plasma treatment mode.
3. The method of claim 2, wherein the step of forming the barrier layer is performed by plasma treatment using a nitrogen-containing gas.
4. The method of forming of claim 3, wherein the nitrogen-containing gas comprises nitric oxide, nitrous oxide, or ammonia.
5. The method of claim 3, wherein in the step of forming a barrier layer on sidewalls of the opening using a nitrogen-containing gas, process parameters include: the process gas pressure is in the range of 1mTorr to 500mTorr, the process gas flow is in the range of 10sccm to 1000sccm, the process temperature is in the range of 20 ℃ to 300 ℃, and the process time is in the range of 2s to 500 s.
6. The forming method according to claim 1, wherein in the step of forming the spacer, a material of the spacer is silicon oxide;
in the step of forming the barrier layer, the barrier layer is a nitrogen-containing barrier layer.
7. The forming method according to claim 6, wherein in the step of forming the barrier layer, a material of the barrier layer is silicon oxynitride.
8. The method of claim 1, wherein in the step of forming a barrier layer on sidewalls of the opening, the barrier layer has a thickness of
Figure FDA0002421443010000021
To
Figure FDA0002421443010000022
Within the range.
9. The method of forming of claim 1, wherein one or both of the step of forming an isolation layer and the step of forming an isolation structure comprises: the isolation material is filled by means of fluid chemical vapor deposition.
10. The method of claim 9, wherein in the step of filling the isolation material by fluid chemical vapor deposition, the isolation material is in a fluid state;
in the step of annealing the isolation material to form the isolation structure, the annealing cures the isolation material in a fluid state.
11. The method of forming of claim 1, wherein the isolation material is a polymer containing one or more of Si-H bonds, and Si-O bonds.
12. The method of claim 1, wherein removing the second fin and the second isolation layer forming an opening comprises: and removing the second fin part and the second isolation layer in a dry etching mode, exposing the substrate of the second area and the side wall of the first isolation layer, and forming the opening.
13. The method of claim 1, wherein in the step of providing a substrate, the substrate in the first region is used for forming a semiconductor device having a fin, and the substrate in the second region is used for forming an isolation structure.
14. A semiconductor structure formed by the method of forming of any of claims 1 to 13, comprising:
a substrate including a plurality of first regions and second regions located between adjacent first regions;
the isolation layer is filled between the adjacent fin parts;
an isolation structure on the second region substrate;
the isolation structure and the first isolation layer expose the top of the first fin part and partial surface of the side wall;
a barrier layer between the isolation structure and the isolation layer, the barrier layer having a density greater than a density of the isolation layer.
15. The semiconductor structure of claim 14, wherein the barrier layer is a nitrogen-containing barrier layer; the isolation layer is made of oxide.
16. The semiconductor structure of claim 15, wherein the material of the barrier layer is silicon oxynitride.
17. The semiconductor structure of claim 14, wherein the barrier layer has a thickness in the range of
Figure FDA0002421443010000032
To
Figure FDA0002421443010000031
Within the range.
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