CN107994011A - 半导体封装体和制造半导体封装体的方法 - Google Patents

半导体封装体和制造半导体封装体的方法 Download PDF

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Publication number
CN107994011A
CN107994011A CN201610949420.3A CN201610949420A CN107994011A CN 107994011 A CN107994011 A CN 107994011A CN 201610949420 A CN201610949420 A CN 201610949420A CN 107994011 A CN107994011 A CN 107994011A
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China
Prior art keywords
conductive pattern
component
side wall
naked core
naked
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CN201610949420.3A
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CN107994011B (zh
Inventor
邱进添
邰恩勇
钱开友
廖致钦
H.塔基亚
G.辛格
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Shandi Trading Shanghai Co ltd
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SanDisk Information Technology Shanghai Co Ltd
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Priority to CN201610949420.3A priority Critical patent/CN107994011B/zh
Priority to KR1020170113300A priority patent/KR101963035B1/ko
Priority to US15/704,984 priority patent/US11031371B2/en
Publication of CN107994011A publication Critical patent/CN107994011A/zh
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Abstract

本技术涉及一种半导体封装体。所述半导体封装体包含：包含多个上下叠置的第一裸芯的第一部件，第一裸芯中的每一个包含至少一个侧表面，和暴露在所述侧表面上的电接触，并且多个第一裸芯对齐，使得全部第一裸芯的对应的侧表面相对于彼此实质上共平面，以形成共同的侧壁；第一导电图案，形成在侧壁之上，并且从侧壁至少部分地间隔开，第一导电图案将多个第一裸芯的电接触电互连；至少一个第二部件；以及形成在第二部件的表面上的第二导电图案，第二导电图案固定并且电连接到第一导电图案。

Description

半导体封装体和制造半导体封装体的方法
技术领域
本技术涉及半导体封装体。
背景技术
对于便携式消费电子产品需求的强势增长正在驱动对于高容量存储部件的需求。半导体存储器部件(例如闪速存储器存储卡)正变得被广泛使用，以迎合数字信息存储和交换日益增长的需求。它们的便携性、多功能性和坚固设计，以及它们的高可靠性和大容量，使得这样的存储器部件理想地使用在多种多样的电子部件中，包括例如数字相机、数字音乐播放器、视频游戏机、PDA和移动电话。
尽管各种封装体配置是已知的，闪速存储器存储卡典型地被制造为单封装系统(SiP)或多芯片模块(MCM)，其中多个裸芯安装并且互连到基板上，并且包封在模塑料之中。图1A和图1B是常规半导体封装体100的俯视图和侧视图。半导体封装体100包含基板110和多个裸芯，多个裸芯包含并排地布置在基板110上的存储器裸芯120和控制器裸芯130。可以分别通过焊料球122或键合引线132将存储器裸芯120和控制器裸芯130连接到基板110。图2A和图2B示出另一常规半导体封装体200。半导体封装体200包含基板210和多个裸芯，多个裸芯包含垂直地堆叠在基板210上的存储器裸芯220和控制器裸芯230。可以分别通过焊料球222和键合引线232将存储器裸芯220和控制器裸芯230连接到基板210。在两种配置中，半导体封装体包含基板，用于支撑和容纳裸芯和其他元件(未示出)，例如无源器件，无源器件包含电阻、电容或电感。
发明内容
概括起来，本技术的一个方面中，一种半导体封装体包含：包含：包含多个上下叠置的第一裸芯的第一部件，第一裸芯中的每一个包含至少一个侧表面，和暴露在所述侧表面上的电接触，并且多个第一裸芯对齐，使得全部第一裸芯的对应的侧表面相对于彼此实质上共平面，以形成共同的侧壁；第一导电图案，形成在侧壁之上，并且从侧壁至少部分地间隔开，第一导电图案将多个第一裸芯的电接触电互连；至少一个第二部件；以及形成在第二部件的表面上的第二导电图案，第二导电图案固定并且电连接到第一导电图案。
本技术的另一方面中，一种半导体系统包含多个部件，所述多个部件布置为三维矩阵配置，并且通过设置在相邻的部件的相对表面上的相对的导电图案物理地和电气地互连，每个部件包含上下叠置的多个裸芯，堆叠体中的裸芯对齐且控制其尺寸使得全部裸芯的对应的侧表面相对于彼此实质上共平面，以形成四个共同侧壁。所述导电图案包含侧壁导电图案和端面导电图案，侧壁导电图案形成在部件的各自的侧壁之上，并且从各自的侧壁至少部分地间隔开，侧壁导电图案电互连各自的部件中的多个裸芯，端面导电图案形成于各自的部件的端表面上。
本技术的另一方面中，一种形成半导体封装体的方法包含：制备多个第一裸芯，第一裸芯的每一个包含至少一个侧表面和暴露在侧表面上的电接触；对齐并且堆叠多个第一裸芯，使得全部第一裸芯的对应的侧表面相对于彼此实质上共平面，以形成共同的侧壁；在第一部件的侧壁之上形成第一导电图案，并且第一导电图案从第一部件侧壁至少部分地间隔开，第一导电图案电互连多个第一裸芯的电接触；第二部件的表面上形成第二导电图案；以及通过将第一导电图案与第二导电图案互连，将第二部件固定到第一部件的侧壁上。
附图说明
图1A和图1B是常规半导体封装体的示意俯视图和示意侧视图。
图2A和图2B是另一常规半导体封装体的示意俯视图和示意侧视图。
图3A至图3D分别是根据本技术实施例的半导体封装体的示意立体图、示意正视图、示意俯视图和沿图3B和3C中的线D-D’取的示意截面图。
图4是示出依据本技术实施例的半导体封装体的制造方法的流程图。
图5A至图11B是根据如图4所示的本技术实施例的半导体封装体的制造方法的不同步骤的示意图。
图12A和图12B分别是根据本技术的另一实施例的半导体封装体的示意正视图和示意俯视图。
图13A至图13C根据本技术的另一实施例的半导体封装体的示意立体图、沿图13A的平面B-B’取的示意截面图和沿图13B的线C-C’取的截面图。
图14A和图14B是根据本技术的另一实施例的半导体封装体的示意立体图和示意俯视图。
图15A、图15B和图15C是根据本技术的另一实施例的半导体封装体的示意正视图和沿图15A中的线B-B’和线C-C’取的示意截面图。
图16是根据本技术的另一实施例的半导体封装体的示意立体图。
图17A和图17B是根据本技术的另一实施例的半导体封装体的示意立体图和沿图17A中的平面B-B’取的示意截面图。
图18是示出了在根据本技术实施例的裸芯堆叠体的侧壁上形成导电图案的方法的流程图。
图19A至图23B示出在根据本技术实施例的裸芯堆叠体的侧壁上形成导电图案的方法的不同步骤的示意图。
具体实施方式
实施例将参考图3A至图23B描述，其涉及一种半导体封装体、一种半导体系统和一种半导体封装体的制造方法。可以理解本技术可以以许多不同的形式实现且不应解释为限于本文所阐述的实施例。而是，这些实施例被提供，使得本公开将是充分和完整的，且将本发明完全传递给本领域的技术人员。本技术旨在覆盖这些实施例的替换、修改和等同物，这些实施例被包括在由所附权利要求界定的本发明的范围和精神内。另外，在本技术的所附详细说明中，阐述了许多特定的细节，以提供本技术的完整理解。然而，对于本领域人员而言清楚的是，本技术可以在没有这样的特定细节的情况下被实现。
在本文中使用的术语“左”，“右”，“顶部”，“底部”，“上”，“下”，“垂直”和/或“横向”仅是为方便和说明的目的，而并不旨在限制本技术的描述，这是因为涉及的项目可以交换位置。同样，如本文使用的，冠词旨在包含单数和复数的形式，除非内容明确指明相反的含义。术语“实质上”和/或“约”是指具体的尺寸或参数可以在给定应用的可以接受的制造公差范围内变动。在一个实施例中，可以接受的制造公差是±0.25％。
附图的自始至终，相同或相似的部件用相同的方式标记，具有相同的末两位数字。
本技术的一个实施例将参考根据本技术实施例的示意立体图图3A、示意正视图图3B、示意俯视图图3C和沿的图3B和图3C所示线D-D’取的半导体封装体的示意截面图图3D进行描述。
参考图3A至图3D，半导体封装体300包含第一部件310，第一部件310包含经由粘接层垂直地堆叠的多个裸芯311，粘接层是例如DAF(裸芯贴附膜)层(未示出)。裸芯311可以包含存储器裸芯，例如具有相同尺寸的存储器裸芯。第一部件310中的全部裸芯311对齐，其至少一个对应的侧表面相对于彼此实质上共平面，以形成共同的侧壁313。第一部件310中的裸芯311的数量可以改变，包含例如2、4、8、16或32个裸芯。在其他实施例中，堆叠体中的裸芯可以有其他数量。裸芯311中的每一个包含导电图案316，导电图案316形成在制造电子元件和电路的有效表面315上。如图3D所示，导电图案316可以具有与相应的裸芯311的上表面共平面的上表面，并且可以由金、铜、铝或其合金制成。导电图案316的至少一部分暴露在侧壁313上，以形成电接触317(其中只有一个被标记)。导电图案316可以包含延伸到侧壁313的迹线314(其中只有一个被标记)，从而这样的电接触317是迹线314暴露的端部。可选择地，导电图案316可以还包含多个接合垫312，接合垫312沿裸芯311中相应的一个的边缘布置，并且与裸芯311中相应的一个的边缘间隔开，并且迹线314从相应的接合垫312延伸到侧壁313。在本实施例中包含接合垫312的这样的导电图案316使得可以利用常规裸芯，常规裸芯包含在其上进行引线键合工艺的接合垫312。导电图案316还电连接到裸芯311中相应的一个的其他电路，为图示简洁未将其示出。可替换地，侧壁上的电接触可以包含直接沿侧壁对齐的接合垫的暴露的边缘。此情况中，通过接合垫形成的电接触比通过迹线形成的电接触具有更大的暴露的面积，从而改善后续在电接触上形成的电连接的可靠性。根据本技术的裸芯311中的每一个有效表面315上的导电图案316可以具有与上面描述的配置不同的各种配置。
半导体封装体300还包含第一导电图案326，第一导电图案326形成在第一部件310的侧壁313之上，并且从侧壁313至少部分地间隔开。第一导电图案326与第一裸芯311的在侧壁313上暴露的电接触317直接接触，以电耦合到第一部件310的第一裸芯311。在部件的裸芯堆叠体的侧壁上形成的这样的导电图案可以称为“侧壁”(TSW)结构。第一导电图案326可以充当重分配层(RDL)，扇出第一部件310的侧壁313上暴露的电接触317。第一导电图案326可以包含多个接合垫322(其中只有一个被标记)和多个迹线324(其中只有一个被标记)，迹线324从相应的接合垫322延伸。接合垫322中的每一个可以配置为正方形、矩形、圆形、椭圆形等形状，它们提供比从相应的接合垫322延伸的线形迹线324更大的接合面积。包含接合垫322的第一导电图案326的这样的侧壁图案设计为后续工艺中附接到侧壁上的任何部件提供更大的接合面积，其中将更详细描述。第一导电图案326可以由导电材料制成，例如铜、金、铝、钨、镍或其合金。
半导体封装体300还包含第二部件330，第二部件330附接在第一部件310的侧壁311上。为了清晰，第二部件330在图3B中以虚线表示的透视部件示出。第二部件330可以具有比第一部件311更小的尺寸。例如，第二部件330可以包含控制器裸芯、插入器、电荷泵或无源器件，配置为裸芯形式或SMT形式(例如BGA)，无源器件例如是电阻、电容或电感。可替换地，第二部件可以配置为与第一部件相似或甚至更大的尺寸。例如，第二部件330可以包含多层印刷电路板，多层印刷电路板包含交替的导电图案层和绝缘层间层。第二部件330包含电接触332(其中只有一个被标记)，例如在第二部件330的表面333上形成的接合垫。
此外，半导体封装体300可以包含第二导电图案346，第二导电图案346形成在第二部件330的表面333之上。第二导电图案346电连接到第二部件330的电接触332，充当重分配层(RDL)，以扇出第二部件300的表面333上的电接触332。相似地，第二导电图案346可以还包含接合垫342和迹线344，迹线344从相应的接合垫342延伸。接合垫342布置为使得第二部件330相对于第一部件310对齐时，对应的第二导电图案346的接合垫342与第一导电图案326的接合垫322在位置上彼此相对，如图3D所示。例如，接合垫322和接合垫342两者都布置为阵列，阵列相邻的接合垫之间具有实质上相等的间隔。以此方式，对齐的第一部件310和第二部件330的相对的接合垫322和接合垫342可以提供在侧壁313上分布的多个接合位置，从而将第二部件330附接到第一部件310的侧壁313上时改善可靠性和稳定性。第二导电图案346可以嵌入表面333上的绝缘层345，如图3D所示。可替换地，没有绝缘层345的情况下，第二导电图案346也可以形成在表面333上。第二导电图案346可以由导电材料制成，例如铜、金、铝、钨、镍或其合金。
半导体封装体300可以还包含多个连接体，连接体接合在第一导电图案326与第二导电图案346之间，充当将第二部件330固定到第一部件311的侧壁313上的接合部件，并且经由连接体和RDL(例如第一导电图案326和第二导电图案346)将第一部件310与第二部件330电连接。如图3D所示，连接体可以包含设置在第一导电图案326(例如接合垫322)上的第一连接体328(其中只有一个被标记)，以及设置在第二导电图案346(例如接合垫342)上的第二连接体348(其中只有一个被标记)。此情况中，在相应接合垫324和接合垫344上的对应的第一连接体328和第二连接体348接合到一起，将对应的第一导电图案326和第二导电图案346物理地和电气地连接，进而将第二部件330固定到第一部件311的侧壁313上。可替换地，可以通过将第一连接体328和第二连接体348中的仅一个接合到第一导电图案326和第二导电图案346的两者，将第二部件330固定到侧壁313上。在本实施例中，连接体不仅充当物理地接合第一部件310和第二部件330的接合部件，也充当将第一部件310和第二部件330电耦合的电连接体。第一连接体328和第二连接体348可以包含导电的球或凸块，导电的球或凸块是例如焊料球、金球、金凸块或铜凸块，并且通过本领域技术人员已知的金属沉积工艺接合在相应的接合垫上。
由于用于固定第一部件310和第二部件330的连接体设置在接合垫322和342上，接合垫322和342具有比直线迹线更大的接合面积，所以连接体可以形成有更大的足印(footprint)和在第一导电图案和第二导电图案上对应的更大的接合面积，从而提高第一部件310与第二部件330之间的接合强度。这样可以显著地改善半导体封装体300的可靠性。
半导体封装体300可以还包含保护性材料(未示出)，保护性材料将第一部件和第二部件与对应的第一导电图案和第二导电图案包封在其中，保护性材料是例如保护半导体封装体免受环境影响的模塑料。
根据本技术的半导体封装体可以制造为闪速存储器器件，例如存储卡或固态驱动器或者刀片。
根据本技术的半导体封装体中，将部件(例如控制器裸芯或无源器件)附接到第一部件的侧壁上，第一部件包含例如为所谓的TSW配置的存储器裸芯堆叠体。以此方式，具有与堆叠的存储器裸芯不同功能的各种部件可以整合到半导体封装体之中，从而显著改善TSW配置的封装体的设计灵活性。由于存储器裸芯堆叠体垂直对齐，半导体封装体具有在主机装置(未示出)上最小化的足印(footprint)。此外，根据本实施的半导体封装体可以配置为无基板封装体，无基板封装体不带有常规半导体封装体中用来支撑和容纳诸部件的附加的基板(如图1A至图2B所示)。此情况中，可以缩小半导体封装体的尺寸，以允许半导体封装体的进一步微型化。
此外，包含接合垫的侧壁导电图案设计允许设置在相对的第一导电图案和第二导电图案上的具有更大接合面积的连接体，从而提高第一部件与附接到第一部件侧壁上的第二部件之间的接合强度。此外，本实施例的半导体封装体利用包含第一导电图案的侧壁导电图案和连接体，将存储器裸芯和其他封装体中的部件电互连，而没有任何的引线键合体。由于信号通道的长度缩短，这使电路可以快速运行，并且通过消除引线键合工艺改善半导体封装体的可靠性和鲁棒性。
将通过参考流程图图4和示意图图5A-11B解释根据本技术实施例的半导体封装体的制造方法。
如图4所示，本方法始于制备多个裸芯311的步骤S410。裸芯311中的一个如示意俯视图图5A、示意正视图图5B和沿图5A中的线C-C’取的示意截面图图5C所示。裸芯311中的每一个包含导电图案316，导电图案316形成在相应的裸芯的有效表面315上。导电图案316(例如)包含接合垫312和迹线314，迹线314自接合垫312中的至少一些延伸到相应裸芯的侧表面319。迹线314在侧表面319上暴露的端面成为相应的侧表面319上的电接触317。导电图案316可以在晶片制造阶段通过已知的光刻工艺在制备电子元件和电路互连的步骤中形成，光刻工艺包含金属层的沉积、曝光并显影光掩模、光掩模的蚀刻和移除的步骤。此情况中，可以通过实施光刻工艺的新掩模，省去接合垫312，以通过迹线314将裸芯311中的每一个的电路直接布线到侧表面319。可替换地，可以在多个阶段制造导电图案316的接合垫312和迹线314。例如在晶片制造阶段，制备仅包含接合垫312的裸芯。接合垫312被制造用于常规制造方法的引线键合工艺。然后可以在分开的步骤中将导电图案316的迹线314制造为低轮廓连接杆。例如，从晶片单一化裸芯311之后，裸芯311中的每一个经过附加的金属化工艺(例如丝网印刷或光刻工艺)，来制造迹线314的连接杆。此情况中，在晶片制造阶段期间，可以在不更换掩模设计的情况下使用常规裸芯。导电图案316可以由金、铜、铝或其合金制成。
接下来，在步骤S420，如示意正视图图6A和沿图6A中的线B-B’取的示意截面图图6B所示，裸芯311对齐并且垂直地堆叠，使得裸芯311的对应的侧表面319相对于彼此实质上共平面，以形成共同的侧壁313。裸芯311通过贴附层(例如DAF，未示出)彼此固定。第一部件310的其他细节已在前面的实施例中描述，并因此将不在此重复。
接下来，在步骤S430，如示意正视图图7A和沿图7A中的线B-B’取的示意截面图图7B中所示，第一导电图案326形成在第一部件310的侧壁313之上，并且从侧壁313至少部分地间隔开。第一导电图案326直接接触侧壁313上的电接触317(其中只有一个被标记)，以电耦合到第一部件310的裸芯311。电接触317可以经过表面处理，例如清洁和粗糙化，以改善与第一导电图案326的欧姆接触。第一导电图案326可以包含接合垫322和迹线324，其中迹线324从接合垫322延伸。第一导电图案326可以由导电金属(例如金、铜、镀金的铜或其类似材料)制成。将在说明书的后面更详细描述在裸芯堆叠体的侧壁之上形成导电图案的方法。
接下来，在可选的步骤S440，如示意正视图图8A和沿图8A中的线B-B’取的示意截面图图8B中所示，一个或多个第一连接体328设置在第一导电图案326(例如在接合垫322)上。可以由导电材料形成第一连接体328，导电材料是例如通过已知的方法沉积在第一导电图案326的接合垫322上的焊料球、金球、金凸块或铜凸块。
接下来，在步骤S450，如示意俯视图图9A和示意截面图图9B所示，第二导电图案346形成在第二部件330的表面333上，第二部件330包含表面333上形成的电接触332。在本实施例中，第二部件330可以包含控制器裸芯、插入器、电荷泵或例如为电阻、电容或电感的无源器件，其配置为裸芯形式或SMT形式(例如BGA)。电接触332可以包含接合垫，接合垫沿第二部件330的侧表面排列，并且从第二部件330的侧表面间隔开。可以如下形成第二导电图案346。首先在第二部件310的整个表面313上形成绝缘层345，然后构图以暴露特定的电接触332，并且留下用于填充导电材料的开口。接下来施加导电材料填充开口，以形成第二导电图案346。可以重复以上工艺，以形成多级导电层，从而(一个或多个)导电层间层可以互连底层电接触332和暴露的第二导电图案346。
例如，第二导电图案346可以包含接合垫342和迹线344，迹线344从接合垫342延伸到暴露的电接触332。第二导电图案346的接合垫342可以具有与第一导电图案326的对应的接合垫322相似的布置，使得在对齐时，对应的接合垫322和接合垫342可以彼此相对。可以或者经由迹线344(如图9A所示)，或者通过在电接触332中对应的一个的顶部上直接形成相应的一个接合垫342(如图9B所示)，或者甚至经由导电层间层(未示出)，将第二导电图案346的接合垫342中的至少一些电连接到下面的第二部件330的电接触332。接合垫342中的一些可以是虚设垫，虚设垫不电连接到任何电接触332。此情况中，第二导电图案346还充当第二部件330的RDL。
接下来，在可选的步骤S460，如示意俯视图图10A和沿图10A中的线B-B’取的示意截面图图10B所示，在第二导电图案346上设置一个或多个第二连接体348。例如，通过已知的方法将第二连接体348沉积到相应的接合垫342上。第二连接体348可以由导电材料形成，例如焊料球、金球、金凸块或铜凸块。
接下来，在步骤S470，通过互连第一导电图案326和第二导电图案346，将第二部件330对齐并固定到第一部件310的侧壁313上。例如，第一部件310和第二部件320相对于彼此对齐，使得对应的第一导电图案326的接合垫322与第二导电图案346的接合垫342彼此相对。如示意正视图图11A和沿图11A中的线B-B’取的示意截面图图11B所示，以此方式，可以在连接体由焊料球制成的情况下通过回流焊接工艺，或者在连接体由金或铜凸块制成的情况下通过在升温的热压工艺，将位于相应接合垫322和接合垫342上的对应的第一连接体328和第二连接体348接合到一起。将第二部件330压到第一部件330上时，第一连接体328和第二连接体348可以充当接合工艺的缓冲体，其可以降低接合工艺期间第一导电图案326和第二导电图案346损坏的风险。可替换地，可以仅使用第一连接体328或仅使用第二连接体348，将第二部件330固定到第一部件310的侧壁313上。
根据本实施例的半导体封装体的制造方法可以还包含包封工艺，以将第一部件310、第二部件330、导电图案326和346和连接体包封在保护性材料之中，保护性材料例如是模塑料，从而保护半导体封装体免受环境影响。
在上面的实施例中，一个第二部件固定到第一部件的侧壁上。根据本技术的半导体封装体不局限于此，而可以包含固定到第一部件的侧壁上并且电连接到第一部件的多个第二部件。如示意正视图图12A和示意俯视图图12B所示，根据本技术的另一实施例的半导体封装体1200包含两个固定到第一部件1210的侧壁1213上的第二部件1230和1230’。例如，分别地，第二部件1230可以是控制器裸芯，而第二部件1230’可以是芯片形式的无源器件。在本实施例中，可以将具有不同功能的多个第二部件固定到第一部件的侧壁上，并且电连接到第一部件，从而增强根据本技术的半导体封装体的功能。本实施例的其他方面与前面的实施例诸方面实质上相同，并将不在此重复。
在前面提及的实施例中，第二部件是单片部件。根据本技术的半导体封装体不局限于此，并且可以包含由多个裸芯组成的第二部件。根据另一实施例的半导体封装体1300将参考示意立体图图13A、沿图13A中的X-Z平面B-B’取的截面图图13B和沿图13B中的线C-C’取的截面图图13C更详细地描述。
半导体封装体1300包含第一部件1310和第二部件1330。为了图示，在图13A中将第一部件1310示出为透视部件。第一部件1310和第二部件1330两者都配置为相似的TSW结构。即第一部件1310包含多个裸芯1311，多个裸芯1311垂直地堆叠并且对齐，以形成共同的侧壁1313，而第一导电图案1326形成在第一部件1310的侧壁1313之上，并且电连接到裸芯1311。第二部件1330包含多个裸芯1331，裸芯1331垂直地堆叠并且对齐，以形成共同的侧壁1333，而第二导电图案1346形成在第二部件1330的侧壁1333之上，并且电连接到裸芯1331。如图13B和图13C所示，第二导电图案1346形成在覆盖侧壁1333的绝缘层1345中，并且包含接合垫1342和迹线1344，迹线1344从接合垫1342延伸。第二部件1310和第二部件1330并排地布置，并且在相应的侧表面1313和侧表面1333上形成的第一导电图案1326和第二导电图案1346面相彼此。第一导电图案1326和第二导电图案1346可以具有相似的图案，使得第二导电图案1346的对应的接合垫1342可以与第一导电图案1326的接合垫相对。此情况中，或者在连接体由焊料球制成的情况下通过回流焊接工艺，或者在连接体由金或铜凸块制成的情况下通过在升温的热压工艺，可以使设置在第一导电图案1326和第二导电图案1346的对应的接合垫上的第一连接体1328和第二连接体1348彼此相对并接合到一起。以此方式，第一部件1310与第二部件1330物理地和电气地连接。根据本实施例，多个裸芯(例如存储器裸芯)可以分组为多个裸芯堆叠体，并且集成到单个半导体封装体中，从而提高存储器装置的容量。半导体封装体1300的其他方面与前面的实施例中的诸方面实质上相同，并将不更详细地描述。
在前面提到的半导体封装体中，多个第二部件固定到第一部件的裸芯堆叠体的单个侧壁上。根据本技术的半导体封装体不局限于此，并且可以包含固定到第一部件的裸芯堆叠体不同的对齐的共同侧壁上的多个部件。图14A和图14B分别示出根据本技术的另一实施例的半导体封装体1400的示意立体图和示意俯视图。半导体封装体1400包含布置为二维阵列的第一部件1410、第二部件1430、第三部件1450和第四部件1470。部件1410-1470中的每一个包含多个裸芯，多个裸芯垂直地堆叠，对齐以形成至少两个共同的平坦侧壁，并且配置为TSW结构。例如，第一部件1410的裸芯与它们在X方向上延伸的对应的侧表面对齐为相对于彼此实质上共平面，以形成共同的侧壁1413，并且与它们在Y方向上延伸的对应的侧表面相对于彼此实质上共平面，以形成共同的侧壁1417。此情况中，可以经由设置在相邻部件的相对侧壁上的导电图案和连接体将部件1410-1470物理地和电气地连接。例如，经由侧壁1413上的第一导电图案1426、侧壁1433上的第二导电图案1446以及设置在第一部件1410与第二部件1430之间的连接体1428和1448，将第一部件1410连接到第二部件1420。经由相对的第一部件1410的侧壁1417和第三部件1450的侧壁1453上的导电图案以及设置于第一部件1410与第三部件1450之间的连接体1468和1488，将第一部件1410也连接到第三部件1450。在本实施例中，可以在第一部件的存储器堆叠体的不同的侧壁上分布附加的多个部件，这改善封装体设计的灵活性，并且分布电负载和热负载，并且通过在单个封装体中集成更多的裸芯提高装置的容量。半导体封装体1500的其他方面与前面的实施例中的诸方面实质上相同，并将不更详细描述。
在前面提到的半导体封装体中，经由在裸芯堆叠体的至少一个侧壁之上形成的(一个或多个)导电图案，将多个部件互连。根据本技术的半导体封装体不局限于此，并且可以包含经由第一部件的裸芯堆叠体的端表面上形成的端面导电图案与裸芯堆叠体互连的(一个或多个)附加的部件。此处的端表面是指第一部件的一个端的表面，其可以或者是第一部件中的最顶部裸芯的顶部表面，或者是第一部件中的最底部裸芯的底部表面。
图15A、图15B和图15C分别是根据本技术的半导体封装体1500的示意正视图、沿图15A中所示的线B-B’和线C-C’取的示意截面图。半导体封装体1500包含第一部件1510、第二部件1530和第三部件1550。，半导体封装体1500与如图3A至图3C所示的半导体封装体300实质上相同，除了半导体封装体1500包含端面导电图案1566和附接到第一部件1510的裸芯堆叠体的端表面上的附加的第三部件1550之外。如图15C所示，端面导电图案1566形成在绝缘层1565中，绝缘层1565施加在第一部件1510的裸芯堆叠体的端表面1515上。端面导电图案1566可以包含接合垫1562和从相应的接合垫1562延伸的迹线1564，并且至少部分地电连接到导电图案1516，例如裸芯1511中的一个的接合垫1512和/或第一导电图案1526。此情况中，端面导电图案1566充当RDL，以便于第一部件1510与第三部件1550之间的电连接。第三部件1550可以包含多层PCB或插入器。经由端面导电图案1566和设置在第三部件1550表面上形成的接合垫1552与端面导电图案1566的接合垫1562之间的第三连接体1558，将第三部件1550物理地和电气地连接到第一部件1510。在本实施例中，第一部件1510和第二部件1530可以容纳和支撑在PCB板上，从而改善半导体封装体结构完整度和机械强度。本实施例的其他方面与如图3A至图3C所示的实施例中的诸方面实质上相同，并将不在此重复。相似地，如图12A至图12B和图13A至图13B所示，基板的第三部件可以附接到半导体封装体的第一部件的端表面上形成的端面导电图案之上，从而改善相应的半导体封装体的结构完整度和机械强度。为避免冗长，实施例的这样的改动的细节将不在此进一步描述。
本发明的另一实施例将参考示意立体图图16描述。在本实施例中，半导体封装体1600包含多个部件1610(其中只有一个被标记)。部件1610中的每一个包含多个裸芯1611(其中只有一个被标记)，多个裸芯1611垂直地堆叠并且对齐，全部四个侧表面相对于同一堆叠体中的裸芯对应的侧表面实质上共平面，以形成四个共同侧壁。部件1610中的每一个配置为TSW结构，即侧壁导电图案1626(其中只有一个被标记)形成在部件1610中的每一个的侧壁之上，并且电连接到相应的部件1610的裸芯1611。可以在绝缘层1625中形成侧壁导电图案。部件1610布置为3D矩阵配置，并且通过侧壁导电图案1626和设置于在X和Y方向上相邻的部件1610的相对的侧壁导电图案1626之间连接体(未示出)互连，以及通过相应的部件1610的(一个或多个)端表面上形成的端面导电图案1636和设置于在Z方向上相邻的部件1610的相对的端面导电图案1636之间的连接体(未示出)互连。以此方式，侧壁导电图案1626和端面导电图案1636的两者都充当互连相邻部件1610的RDL。还可以用保护性材料(例如模塑料，未示出)包封半导体封装体1600。
半导体封装体1600中的部件1610可以包含具有不同功能的裸芯1611，例如存储器裸芯、控制器裸芯、处理器裸芯、无源器件裸芯或甚至充当中继器件或插入器的虚设裸芯。以此方式，能够以模块化方式组建半导体封装体1600。此情况中，封装体1600的部件1610中的每一个起独立模块的功能，而封装体中的连接体和导电图案充当不同模块之间的通信通道。以此方式，如果相应地配置，根据本技术的半导体封装体可以被实施为具有潜在的无限容量和功能的新颖模块化半导体系统。例如，这样的半导体系统可以被实施为包含大量互连的存储装置和其他管理数据的功能性部件的数据中心，存储装置中的每一个包含多个存储器裸芯。
根据本发明的进一步实施例的半导体封装体1700将参考示意立体图图17A、示意截面图图17B描述。半导体封装体1700包含第一部件1710和第二部件1730。半导体封装体1700与半导体封装体300实质上相同，除了半导体封装体1700还包含引线键合体1738之外。引线键合体1738将背向第一半导体部件1710的第二部件1730的表面1735上的接合垫1736连接到在第一部件1710的侧壁1713之上形成的第一导电图案1726的接合垫1722上设置的相应的第一连接体1728。半导体封装体1700利用第二部件1730的两个表面来将第二部件1730连接到第一部件1710，从而提供第二部件1730电路排布设计的更高灵活性。实施例的其他方面与前面的实施例中的诸方面实质上相同，并将不在此重复。
在裸芯堆叠体的共同的平面侧壁之上形成侧壁导电图案的方法将参考流程图图18和示意图图19A至图23B更详细地描述。裸芯1811中的每一个具有表面导电图案1816，例如接合垫，接合垫沿相应的裸芯的边缘布置，并且暴露在侧壁1813上以形成电接触1817。如图19A和图19B所示，通过已知的沉积工艺(例如溅射)，在裸芯堆叠体1810的共同侧壁1813上形成绝缘层1825，裸芯堆叠体1810包含多个裸芯1811。绝缘层1825覆盖侧壁1813上暴露的电接触1817。绝缘层1825是例如硅氧化物或硅氮化物，或其他电绝缘体。绝缘层1825可以具有20μm至200μm的厚度，但在另一实施例中可以比其更薄或更厚。
接下来，在步骤S1820，如图20A和图20B所示，通过构图工艺(例如包括曝光、显影和蚀刻步骤的光刻工艺)将绝缘层1825构图，以形成开口1827，开口1827贯穿绝缘层1825，并且暴露侧壁1813上的电接触1817。
接下来在步骤S1830，如图21A和图21B所示，施加导电层1820到绝缘层1825之上，并且进入开口1827，以形成与电接触1817的接触。通过已知的方法，例如溅射或电镀，施加导电层1820。导电层1820由例如铜、金、铝、钨、镍或其合金制成。导电层1820可以是2μm-5μm厚，但在另一实施例中可以比其更厚或更薄。可以可选地进行退火，以调整导电层1820中的金属晶粒状态。
接下来在步骤S1840，如图22A和图22B所示，通过已知的构图工艺(例如包含使用掩模的曝光、显影和蚀刻步骤的光刻工艺)将导电层1820构图成为导电图案1826，导电图案1826包含接合垫1822和迹线1824。可替换地，可以通过丝网印刷法在绝缘层1825上构图导电图案1826。该工艺可以附加地或可替换地采用湿法或干法蚀刻方法和化学机械平坦化(CMP)工艺。
可选地在步骤S1850，如图23A和图23B所示，可以通过选择性蚀刻工艺将导电图案1826之下的绝缘层1825移除，以留下从侧壁1813间隔开的侧壁导电图案1826，导电图案1826包含接合垫1822和迹线1824。
本发明的前述详细说明为了图示和描述的目的呈现。其不旨在是穷尽的或将本发明限于所披露的准确形式。根据以上的教导，许多修改和变化是可能的。所描述的实施例被选择，从而最好地解释本发明的原理和其实际的应用，由此使得本领域的技术人员在各种实施例中最好地利用本发明且各种修改适于所考虑的具体用途。本发明的范围旨在由所附的权利要求所限定。

Claims (21)

1.一种半导体封装体，包含：
第一部件，所述第一部件包含多个上下叠置的第一裸芯，第一裸芯的每一个包含至少一个侧表面和暴露在所述侧表面上的电接触，并且所述多个第一裸芯对齐，使得全部第一裸芯的对应的侧表面相对彼此实质上共平面，以形成共同的侧壁；
第一导电图案，所述第一导电图案形成在所述侧壁之上，并且从所述侧壁至少部分地间隔开，所述第一导电图案与所述多个第一裸芯的电接触电互连；
至少一个第二部件；以及
第二导电图案，所述第二导电图案形成在所述第二部件的表面上，所述第二导电图案固定并电连接到所述第一导电图案。
2.如权利要求1所述半导体封装体，其中
所述第一部件的第一导电图案包含一个或多个第一接合垫，
所述第二部件的第二导电图案包含一个或多个第二接合垫，并且
对应的第一接合垫和第二接合垫相对于彼此对齐。
3.如权利要求2所述半导体封装体，还包含：
一个或多个连接体，所述一个或多个连接体接合在所述第一导电图案与所述第二导电图案之间。
4.如权利要求3所述半导体封装体，其中
所述一个或多个连接体包含一个或多个第一连接体和一个或多个第二连接体，所述一个或多个第一连接体设置在第一导电图案的所述第一接合垫上，所述一个或多个第二连接体设置在所述第二导电图案的第二接合垫上，在对应的所述第一接合垫上的第一连接体和所述第二接合垫上的第二连接体电连接。
5.如权利要求3所述半导体封装体，其中
所述连接体包含焊料球、金球、铜凸块或金凸块。
6.如权利要求1所述半导体封装体，其中
所述第一部件的第一裸芯包含存储器裸芯、控制器裸芯、处理器裸芯、无源器件裸芯、或虚设裸芯。
7.如权利要求1所述半导体封装体，其中
所述第二部件包含控制器裸芯、插入器、电荷泵、无源器件、或印刷电路板。
8.如权利要求1所述半导体封装体，其中
所述第二部件包含多个上下叠置的第二裸芯，第二裸芯的每一个包含至少一个侧表面和暴露在所述侧表面上的电接触，并且所述多个第二裸芯对齐，使得全部第二裸芯的对应的侧表面相对于彼此实质上共平面，以形成共同的侧壁；并且
所述第二导电图案形成在所述第二部件的侧壁之上，并且从所述第二裸芯的侧壁至少部分地间隔开，所述第二导电图案与所述多个第二裸芯的电接触电互连。
9.如权利要求1所述半导体封装体，还包含：
第三部件，所述第三部件经由端面导电图案贴附到所述第一部件的端表面上并与所述第一部件电连接，所述端面导电图案形成在所述第一部件的所述端表面上。
10.如权利要求9所述半导体封装体，其中
所述第一部件的端表面包含所述第一部件的最顶端裸芯的顶表面，或所述第一部件的最底端裸芯的底表面。
11.如权利要求10所述半导体封装体，其中
所述第三部件包含多个上下叠置的第三裸芯，第三裸芯的每个包含至少一个侧表面和暴露在所述侧表面上的电接触，并且所述多个第三裸芯对齐，使得全部第三裸芯的对应侧表面相对于彼此实质上共平面，以形成共同的侧壁。
12.如权利要求1所述半导体封装体，还包含：
引线键合体，所述引线键合体形成在所述第二部件的背对所述第一部件的表面上的接合垫与所述第一导电图案之间。
13.一种半导体系统，包含：
多个部件，所述多个部件布置为三维矩阵配置，并且通过设置在相邻的部件的相对表面上的相对的导电图案物理地和电气地互连，每个部件包含上下叠置的多个裸芯，堆叠体中的裸芯对齐且控制其尺寸使得全部裸芯的对应的侧表面相对于彼此实质上共平面，以形成四个共同侧壁，
其中所述导电图案包含侧壁导电图案和端面导电图案，所述侧壁导电图案形成在所述部件的各自的侧壁之上，并且从所述各自的侧壁至少部分地间隔开，所述侧壁导电图案电互连所述各自的部件中的所述多个裸芯，所述端面导电图案形成于所述各自的部件的端表面上。
14.如权利要求13所述半导体系统，其中所述侧壁导电图案和所述端面导电图案包含一个或多个接合垫，
相对的导电图案的所述接合垫相对于彼此对齐。
15.如权利要求14所述半导体系统，还包含一个或多个连接体，所述连接体设置于并接合到所述相对的导电图案的相对接合垫之间，用于互连相邻的部件。
16.如权利要求15所述半导体系统，其中
所述连接体包含焊料球、金球、铜凸块或金凸块。
17.一种形成半导体封装体的方法，包含：
制备多个第一裸芯，第一裸芯的每一个包含至少一个侧表面和暴露在所述侧表面上的电接触；
对齐并且堆叠所述多个第一裸芯，使得全部第一裸芯的对应的侧表面相对于彼此实质上共平面，以形成共同的侧壁；
在第一部件的所述侧壁之上形成第一导电图案，并且所述第一导电图案从所述第一部件侧壁至少部分地间隔开，所述第一导电图案电互连所述多个第一裸芯的电接触；
在第二部件的表面上形成第二导电图案；以及
通过将所述第一导电图案与所述第二导电图案互连，将所述第二部件固定到所述第一部件的侧壁上。
18.如权利要求17所述方法，其中所述将第二部件固定到所述第一部件的侧壁上还包含：
在所述第一导电图案上设置一个或多个第一连接体；
在所述第二导电图案上设置一个或多个第二连接体；以及
将在所述第一导电图案与所述第二导电图案之间的对应的第一连接体和第二连接体对齐并且接合到一起。
19.如权利要求17所述方法，其中
所述在所述第一部件的侧壁之上形成所述第一导电图案包含：
施加绝缘层，所述绝缘层覆盖所述侧壁；
通过光刻工艺构图所述绝缘层，暴露第一裸芯在所述侧壁上的电接触；
在所述绝缘层和所述电接触上施加导电层；以及
构图所述导电层，以形成所述第一导电图案。
20.如权利要求19所述方法，还包含移除所述绝缘层，以在构图所述导电层后，将所述侧壁之上形成的第一导电图案留下来。
21.如权利要求17所述方法，其中
所述第二部件包含控制器裸芯、插入器、电荷泵、无源器件、或印刷电路板，或
所述第二部件包含上下叠置的多个第二裸芯，第二裸芯的每一个包含至少一个侧表面和暴露在所述侧表面上的电接触，并且所述多个第二裸芯对齐，使得全部第二裸芯的对应的侧表面相对于彼此实质上共平面，以形成共同的侧壁，
所述第二导电图案形成在所述第二部件的侧壁之上，并且从所述第二部件的侧壁至少部分地间隔开，所述第二导电图案电互连所述多个第二裸芯的电接触。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111106078A (zh) * 2019-12-16 2020-05-05 山东砚鼎电子科技有限公司 一种多芯片集成封装结构
WO2023109048A1 (zh) * 2021-12-14 2023-06-22 生益电子股份有限公司 Pcb及其制作方法

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
MY192051A (en) * 2016-12-29 2022-07-25 Intel Corp Stacked dice systems
US11397687B2 (en) * 2017-01-25 2022-07-26 Samsung Electronics Co., Ltd. Flash-integrated high bandwidth memory appliance
CN112151514A (zh) * 2019-06-28 2020-12-29 西部数据技术公司 包括垂直堆叠半导体管芯的半导体器件
CN111952206B (zh) * 2020-08-14 2022-09-13 深圳市天成照明有限公司 一种电子元器件生产用封装装置
US11456272B2 (en) * 2020-09-11 2022-09-27 Western Digital Technologies, Inc. Straight wirebonding of silicon dies
TWI775352B (zh) 2021-03-19 2022-08-21 力晶積成電子製造股份有限公司 半導體封裝及其製造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090085224A1 (en) * 2007-10-02 2009-04-02 Samsung Electronics Co., Ltd. Stack-type semiconductor package
US20110169171A1 (en) * 2009-04-28 2011-07-14 Wafer-Level Packaging Portfolio Llc Dual Interconnection in Stacked Memory and Controller Module
CN102683331A (zh) * 2011-02-17 2012-09-19 苹果公司 侧装控制器及其制造方法
CN103545280A (zh) * 2012-07-11 2014-01-29 爱思开海力士有限公司 多芯片封装体

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2709020B1 (fr) * 1993-08-13 1995-09-08 Thomson Csf Procédé d'interconnexion de pastilles semi-conductrices en trois dimensions, et composant en résultant.
US6686654B2 (en) 2001-08-31 2004-02-03 Micron Technology, Inc. Multiple chip stack structure and cooling system
US7687400B2 (en) * 2005-06-14 2010-03-30 John Trezza Side stacking apparatus and method
JP4934053B2 (ja) 2005-12-09 2012-05-16 スパンション エルエルシー 半導体装置およびその製造方法
DE112012006625B4 (de) * 2012-06-25 2023-09-28 Intel Corporation Mehrchiplagenhalbleiterstruktur mit vertikalem Zwischenseitenchip und Halbleiterpaket dafür
US9082868B2 (en) * 2013-03-13 2015-07-14 Semiconductor Components Industries, Llc Semiconductor component and method of manufacture

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090085224A1 (en) * 2007-10-02 2009-04-02 Samsung Electronics Co., Ltd. Stack-type semiconductor package
US20110169171A1 (en) * 2009-04-28 2011-07-14 Wafer-Level Packaging Portfolio Llc Dual Interconnection in Stacked Memory and Controller Module
CN102683331A (zh) * 2011-02-17 2012-09-19 苹果公司 侧装控制器及其制造方法
CN103545280A (zh) * 2012-07-11 2014-01-29 爱思开海力士有限公司 多芯片封装体

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111106078A (zh) * 2019-12-16 2020-05-05 山东砚鼎电子科技有限公司 一种多芯片集成封装结构
WO2023109048A1 (zh) * 2021-12-14 2023-06-22 生益电子股份有限公司 Pcb及其制作方法

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