CN107895342A - A kind of implementation method of the high speed dithering method based on FPGA - Google Patents
A kind of implementation method of the high speed dithering method based on FPGA Download PDFInfo
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Abstract
The invention discloses a kind of implementation method of the high speed dithering method based on FPGA, this method carries out pixel division to the valid pixel number of a line of line array CCD collection first, starting pixels position and end pixel position are determined, and the pixel between starting point pixel and end pixel is divided into N number of lead to；Then single-point color judgement is carried out to each pixel, real-time judge is carried out to the pixel data of collection with the M groups color threshold received from host computer, if the pixel data collected falls at least one set of number range in eight groups of color thresholds, the pixel data of collection is saved as 1, is otherwise 0；Row of channels judgement is finally entered according to the comparative result of passage threshold value of the accumulated value of each passage with being received from host computer and determines dithering result；This method carries out processing judgement in real time by way of hardware to the view data of collection, substantially increases the speed of dithering, and reduce the integrated level that cost improves system.
Description
Technical field
The invention belongs to industrial machine visual field, and in particular to a kind of high speed dithering method based on FPGA
Implementation method.
Background technology
In industrial machine visual field, have to the dithering method for filtering out the detected material for meeting color requirement compared with
To be widely applied；And realize the key of this function of dithering of detected material is to design and Implement it is a set of efficient
Dithering algorithm, especially when detected material is in the state of high-speed motion；In the conventional technology, generally by view data
Collection separated with processing, on DSP or host computer carry out image processing algorithm realization, it is so not only with high costs but also
It is unfavorable for the system integration；And the data transmission bauds between image data collection system and processing system can also limit whole system
The operating rate of system.
The content of the invention
The present invention is in view of the shortcomings of the prior art, it is proposed that a kind of realization side of the high speed dithering method based on FPGA
Method：Pixel division is carried out to a line valid pixel number of line array CCD collection first, that is, determines starting pixels position and end pixel
Position, and the pixel between starting point pixel and end pixel is divided into N (60<=N<=64) individual passage, then to each
Pixel carries out single-point color judgement, with the M (8 received from host computer<=M<=16) pixel data of the color threshold to collection is organized
Carry out real-time judge；If the pixel data collected falls at least one set of number range in M group color thresholds, will adopt
The pixel data of collection saves as 1, is otherwise 0；Finally according to the accumulated value of each passage and the passage threshold value from host computer reception
Comparative result enter row of channels judgement, determine dithering result.
High speed dithering algorithm realizes that step includes：
Step 1：Pixel division is carried out to the valid pixel number of line array CCD
1-1, definition starting pixels location register PixelStart and end pixel location register PixelEnd, and by
Host computer is to the two register assignments；
1-2, define channel_pixel_num registers be divided into channel_pixel_num_min registers and
Channel_pixel_num_max registers；Wherein channel_pixel_num_min registers storage pixel count is less leads to
The number of pixels value in road, the value of this register is (PixelEnd-PixelStart)/N；channel_pixel_num_max
The number of pixels value of the more passage of register storage pixel count, the value of this register is channel_pixel_num_min+
1；
1-3, the number of pixels that a N-bit register channel_pixel_num_flag is used for representing N number of passage is defined,
In 0-N positions, if the numerical value of this is 1, the number of pixels of the passage is register channel_pixel_num_max value,
Otherwise the number of pixels of the passage is register channel_pixel_num_min value；
1-4, subtract channel_pixel_num_min*N with register PixelEnd and obtain numerical value of N 1,0<=N1<=N；
And by the 0 of register channel_pixel_num_flag to N1 positions 1, remaining position 0.
Step 2：Single-point color judgement is carried out to each pixel
2-1, M group color threshold registers are defined, every group 3, common 3*M is individual；3 registers in wherein every group are respectively
Color R threshold register R_max_min, color G threshold register G_max_min, color B threshold register B_max_
Min, it is 16 bit registers；Least-significant byte deposits Low threshold, most-significant byte deposit high threshold；And obtain 3*M color threshold from host computer
The value of value register；
2-2, a picture number data for collecting in real time, if its color R value is low more than or equal to R_max_min
The value of 8 and the value for being less than or equal to R_max_min most-significant byte, and least-significant byte of its color G value more than or equal to G_max_min
Value and less than or equal to G_max_min most-significant byte value, and its color B value more than or equal to B_max_min least-significant byte value and
The value of most-significant byte less than or equal to B_max_min, then result save as 1, be otherwise 0；
2-3, replicate the same comparative structure of M groups, by collect in real time view data with M groups color threshold simultaneously
It is compared, every group of comparative result that will produce 10 or 1, this M comparative result is combined into 1 M place value and is deposited at a M
The single-point comparative result register CMPout of position.
Step 3：Enter row of channels judgement and determine dithering result
3-1, delimiting period counter PeriodCnt, performance period cycle count, count value be line array CCD collection one
Capable valid pixel numerical value, is counted during valid pixel；
3-2, produce passage commencing signal channel_start；
3-2-1, linage-counter line_cnt is defined, and be initially a value more than 0；It can so avoid in week
Phase calculator PeriodCnt produces channel_start signals when being equal to 0；When cycle rate counter is equal to 1, i.e., one new
CCD collection period starts, and makes linage-counter line_cnt value be equal to the positional value of starting pixels；When passage commencing signal
Channel_start is that 1 and line_cnt value is less than the positional value of end pixel, makes line_cnt value be equal to line_cnt
Value of the value of itself plus the number of pixels of respective channel；Even line_cnt adds channel_pixel_ equal to line_cnt
Num_min adds channel_pixel_num_flag lowest order；And channel_pixel_num_flag is moved to right into shifting 1
Position：
3-2-2, when cycle rate counter PeriodCnt value be equal to linage-counter line_cnt value when, make opening for passage
Beginning signal channel_statr is 1, and remaining time is 0；
3-3, accumulator register pixel_accumulate is defined, added up and register accumulate_sum；With according to every
The single-point court verdict of individual pixel determines whether accumulator register is added up：If single-point comparative result register CMPout
In M positions at least 1 value be 1, then accumulator register add 1 otherwise accumulator register keep initial value；When passage starts letter
When number channel_statr is 1, accumulator register pixel_accumulate value is latched into cumulative and register
In accumulate_sum, and accumulator register pixel_accumulate is reset；
3-4, the characteristic due to line array CCD, a period of image data acquisition can be only done the collection of a line valid pixel；
Need the cumulative of multirow same channels during row of channels judgement entering and added up again, obtain the last cumulative knot of a passage
Fruit, so need to when the cumulative of each passage of row and storing, and to the cumulative of the same channels of multirow and add up；
3-4-1, call macro functional module generate a size
log2N positions, data width are K*M1 positions；Wherein K value is equal to log2(channel_pixel_num_max) the one of single file, is represented
The bit wide of the maximum pixel number of individual passage；M1 value is to need cumulative line number value into row of channels judgement.Deposited with different addresses
Store up the cumulative and data of different passages, it is therefore desirable to which N number of address stores the value of the cumulative sum of N number of passage.On each address
Data are K*M1 positions, a passage cumulative per K positions for a line and, so storing M1 row same channels on each address
It is cumulative and；
3-4-2, channel counter channel_cnt is defined, for realize channel counts；In passage commencing signal
Channel_start is that the value for making channel counter channel_cnt adds 1 for 1；It is arrived in cycle rate counter PeriodCnt meters
Channel counter is zeroed out during maximum；
3-4-3, realize RAM accesses and passage and accumulation state machine；When channel_cnt is more than or equal to 1, i.e., from second
Individual passage starts, and using passage commencing signal channel_statr as the enabling signal of this state machine, enters after startup and reads
RAM state, channel counter channel_cnt value is read into data as address from RAM；Subsequently enter and shift and write
RAM state, the data read from RAM are moved to left into K positions, and make the value of low K positions be equal to cumulative and register accumulate_sum
Value, the data newly obtained be stored back to RAM channel_cnt addresses and unloading give channel_accumulate registers,
Capable renewal is realized with this.Row accumulation state is subsequently entered, channel_accumulate every K positions are added up, is added up
As a result it is assigned to register channel_sum；Subsequently enter and compare state, by channel_sum and the passage from host computer reception
Threshold value is compared, and if being 1 more than or equal to result if passage threshold value, otherwise result is 0, is deposited at register comp.Then enter
Enter result storage state, define N position result register result, result register result is moved to right N-1 positions, and by highest order
Value be assigned to comp.Subsequently enter Idle state and wait next passage commencing signal from new starting state machine；
3-5, result register result is latched to register when cycle rate counter PeriodCnt is remembered to its maximum
ResultChannel；And reset register result, register ResultChannel value is exported to obtain dithering
As a result.
Compared with prior art, the beneficial effects of the invention are as follows：Realize a kind of high speed dithering based on FPGA
Algorithm, processing judgement in real time is carried out to the view data of collection by way of hardware, substantially increases the speed of dithering
Degree, and reduce the integrated level that cost improves system.
Brief description of the drawings
Fig. 1 is dithering algorithm flow chart
Embodiment
A kind of implementation method of the high speed dithering algorithm based on FPGA is by the way that line array CCD to be gathered to effective picture of a line
Prime number carries out pixel division, and valid pixel is divided into 64 (N=64) individual passages, is carried out in the view data to gathering in real time single
Point color judgement, saves as 1 to falling the pixel result in the range of at least one set of color threshold, is otherwise 0.To in a passage
Single-point court verdict added up, and by the cumulative of the same channels of multirow and added up, as a result do ratio with passage threshold value
Compared with, realize passage adjudicate, determine dithering result.
As shown in Figure 1：Dithering algorithm first obtains color threshold parameter, passage threshold parameter and pixel from host computer
Divide parameter.Then wait for sensor to start to gather valid pixel, then to the view data and face of the pixel collected
Chromatic threshold value is compared, and decides whether to add up to accumulator, and cumulative and result is stored after a channel end,
And it is cumulative to the multirows of same channels and add up, then by accumulation result compared with passage threshold value determination current channel
Dithering result, finally after N number of passage all completes dithering export dithering result, afterwards wait sensor open
The valid pixel of beginning collection next line.
High speed dithering algorithm realizes that step includes：
Step 1：Pixel division is carried out to the valid pixel number of line array CCD
1-1, definition starting pixels location register PixelStart and end pixel location register PixelEnd, and by
Host computer is to the two register assignments；
1-2, the number of pixels value for defining the less passage of channel_pixel_num_min registers storage pixel count,
The value of this register is (PixelEnd-PixelStart)/64；
1-3, the number of pixels value for defining the more passage of channel_pixel_num_max registers storage pixel count,
The value of this register is channel_pixel_num_min+1；
1-4, define the pixel that a 64 bit register channel_pixel_num_flag are used for representing 64 passages
Number, if the numerical value of this of 0-64 positions is 1, the number of pixels of the passage is register channel_pixel_num_max value,
Otherwise the number of pixels of the passage is register channel_pixel_num_min value；
1-5, subtract channel_pixel_num_min*64 with register PixelEnd and obtain numerical value of N 1 (0<=N1<=
64)；And by the 0 of register channel_pixel_num_flag to N1 positions 1, remaining position 0.
Step 2：Single-point color judgement is carried out to each pixel
8 groups of 2-1, definition color threshold registers, every group 3, totally 24；3 registers in wherein every group are respectively
Color R threshold register R_max_min, color G threshold register G_max_min, color B threshold register B_max_
Min, it is 16 bit registers；
Least-significant byte deposits Low threshold, most-significant byte deposit high threshold；And the value of 24 color threshold registers is obtained from host computer；
2-2, a picture number data for collecting in real time, if its color R value is low more than or equal to R_max_min
The value of 8 and the value for being less than or equal to R_max_min most-significant byte, and least-significant byte of its color G value more than or equal to G_max_min
Value and less than or equal to G_max_min most-significant byte value, and its color B value more than or equal to B_max_min least-significant byte value and
The value of most-significant byte less than or equal to B_max_min, then result save as 1, be otherwise 0；
2-3,8 groups of same comparative structures are replicated, by collect in real time view data and 8 groups of color thresholds simultaneously
It is compared, every group of comparative result that will produce 10 or 1, this 8 comparative results is combined into 18 place value and are deposited at one 8
The single-point comparative result register CMPout of position.
Step 3：Enter row of channels judgement and determine dithering result
3-1, delimiting period counter PeriodCnt, performance period cycle count, count value be line array CCD collection one
Capable valid pixel numerical value, is counted during valid pixel；
3-2, produce passage commencing signal channel_start；
3-2-1, linage-counter line_cnt is defined, and be initially a value more than 0；It can so avoid in week
Phase calculator PeriodCnt produces channel_start signals when being equal to 0；
When cycle rate counter is equal to 1, i.e., one new CCD collection period starts, order row
Counter line_cnt value is equal to the positional value of starting pixels；When passage commencing signal channel_start is 1
And line_cnt value is less than the positional value of end pixel, value of the line_cnt value equal to line_cnt itself is made plus corresponding
The value of the number of pixels of passage；Even line_cnt adds equal to line_cnt plus channel_pixel_num_min
Channel_pixel_num_flag lowest order；And channel_pixel_num_flag is moved to right into shifting 1：
3-2-2, when cycle rate counter PeriodCnt value be equal to linage-counter line_cnt value when, make opening for passage
Beginning signal channel_statr is 1, and remaining time is 0；
3-3, accumulator register pixel_accumulate is defined, added up and register accumulate_sum；With according to every
The single-point court verdict of individual pixel determines whether accumulator register is added up：If single-point comparative result register CMPout
In 8 at least 1 value be 1, then accumulator register add 1 otherwise accumulator register keep initial value；When passage starts letter
When number channel_statr is 1, accumulator register pixel_accumulate value is latched into cumulative and register
In accumulate_sum, and accumulator register pixel_accumulate is reset；
3-4, the characteristic due to line array CCD, a period of image data acquisition can be only done the collection of a line valid pixel；
Need the cumulative of multirow same channels during row of channels judgement entering and added up again, obtain the last cumulative knot of a passage
Fruit, so need to when the cumulative of each passage of row and storing, and to the cumulative of the same channels of multirow and add up；
3-4-1, call macro functional module generate a size
8, data width is 6*44 positions；The bit wide of the maximum pixel number of one passage of single file is 6, therefore can be stored up on each address
Deposit the cumulative of 44 row same channels and；
3-4-2, channel counter channel_cnt is defined, for realize channel counts；In passage commencing signal
Channel_start is that the value for making channel counter channel_cnt adds 1 for 1；It is arrived in cycle rate counter PeriodCnt meters
Channel counter is zeroed out during maximum；
3-4-3, realize RAM accesses and passage and accumulation state machine；When channel_cnt is more than or equal to 1, i.e., from second
Individual passage starts, and using passage commencing signal channel_statr as the enabling signal of this state machine, enters after startup and reads
RAM state is by channel counter channel_cnt value reads data as address from RAM；Subsequently enter and shift and write
RAM state, the data read from RAM are moved to left 6, and make the value of low 6 be equal to cumulative and register accumulate_sum
Value, the data newly obtained be stored back to RAM channel_cnt addresses and unloading give channel_accumulate registers,
Capable renewal is realized with this.Row accumulation state is subsequently entered, every 6 of channel_accumulate are added up, is added up
As a result it is assigned to register channel_sum；Subsequently enter and compare state, by channel_sum and the passage from host computer reception
Threshold value is compared, and if being 1 more than or equal to result if passage threshold value, otherwise result is 0, is deposited at register comp.Then enter
Enter result storage state, define 64 result register result, result register result is moved to right 63, and by highest order
Value be assigned to comp.Subsequently enter Idle state and wait next passage commencing signal from new starting state machine；
3-5, result register result is latched to register when cycle rate counter PeriodCnt is remembered to its maximum
ResultChannel；And reset register result, register ResultChannel value is exported to obtain dithering
As a result.
Claims (1)
1. a kind of implementation method of the high speed dithering method based on FPGA, it is characterised in that this method specifically includes following step
Suddenly：
Step 1：Pixel division is carried out to the valid pixel number of line array CCD
1-1, starting pixels location register PixelStart and end pixel location register PixelEnd is defined, and by upper
Machine is to the two register assignments；
1-2, definition channel_pixel_num registers are divided into channel_pixel_num_min registers and channel_
Pixel_num_max registers；The wherein pixel of the less passage of channel_pixel_num_min registers storage pixel count
Individual numerical value, the value of this register is (PixelEnd-PixelStart)/N；Channel_pixel_num_max registers are deposited
The number of pixels value of the more passage of pixel count is stored up, the value of this register is channel_pixel_num_min+1；
1-3, define the number of pixels that a N-bit register channel_pixel_num_flag is used for representing N number of passage, 0-N
In position, if the numerical value of this is 1, the number of pixels of the passage is register channel_pixel_num_max value, otherwise
The number of pixels of the passage is register channel_pixel_num_min value；
1-4, subtract channel_pixel_num_min*N with register PixelEnd and obtain numerical value of N 1,0<=N1<=N；And will
The 0 of register channel_pixel_num_flag to N1 positions 1, remaining position 0；
Step 2：Single-point color judgement is carried out to each pixel
2-1, M group color threshold registers are defined, every group 3, common 3*M is individual；3 registers in wherein every group are respectively color
R threshold register R_max_min, color G threshold register G_max_min, color B threshold register B_max_min,
It is 16 bit registers；Least-significant byte deposits Low threshold, most-significant byte deposit high threshold；And obtain 3*M color threshold from host computer and post
The value of storage；
2-2, a picture number data for collecting in real time, if its color R value is more than or equal to R_max_min least-significant byte
Value and less than or equal to R_max_min most-significant byte value, and its color G value more than or equal to G_max_min least-significant byte value
And the value of the most-significant byte less than or equal to G_max_min, and the value of least-significant byte of its color B value more than or equal to B_max_min and small
In the value of the most-significant byte equal to B_max_min, then result saves as 1, is otherwise 0；
2-3, the same comparative structure of M groups is replicated, by collect in real time view data and M groups color threshold while carried out
Compare, every group will produce 10 or 1 comparative result, this M comparative result is combined into 1 M place value and is deposited at M position
Single-point comparative result register CMPout；
Step 3：Enter row of channels judgement and determine dithering result
3-1, delimiting period counter PeriodCnt, performance period cycle count, count value is a line of line array CCD collection
Valid pixel numerical value, is counted during valid pixel；
3-2, produce passage commencing signal channel_start；
3-2-1, linage-counter line_cnt is defined, and be initially a value more than 0；It can so avoid counting in the cycle
Calculate when device PeriodCnt is equal to 0 and produce channel_start signals；When cycle rate counter is equal to 1, i.e., a new CCD is adopted
Collect the cycle, make linage-counter line_cnt value be equal to the positional value of starting pixels；As passage commencing signal channel_
Start is that 1 and line_cnt value is less than the positional value of end pixel, makes line_cnt value be equal to line_cnt itself value
Plus the value of the number of pixels of respective channel；Even line_cnt adds channel_pixel_num_min equal to line_cnt
Along with channel_pixel_num_flag lowest order；And channel_pixel_num_flag is moved to right into shifting 1：
3-2-2, when cycle rate counter PeriodCnt value be equal to linage-counter line_cnt value when, make passage starts letter
Number channel_statr is 1, and remaining time is 0；
3-3, accumulator register pixel_accumulate is defined, added up and register accumulate_sum；With according to each picture
The single-point court verdict of vegetarian refreshments determines whether accumulator register is added up：If in single-point comparative result register CMPout
In M positions the value of at least 1 be 1, then accumulator register add 1 otherwise accumulator register keep initial value；When passage commencing signal
When channel_statr is 1, accumulator register pixel_accumulate value is latched into cumulative and register
In accumulate_sum, and accumulator register pixel_accumulate is reset；
3-4, the characteristic due to line array CCD, a period of image data acquisition can be only done the collection of a line valid pixel；Entering
Row of channels needs the cumulative of multirow same channels when adjudicating and added up again, obtains a last accumulation result of passage,
So need to when the cumulative of each passage of row and storing, and to the cumulative of the same channels of multirow and add up；
3-4-1, call macro functional module generate a size as RAM memory on the piece of N*K*M1 positions, address width log2N
Position, data width is K*M1 positions；Wherein K value is equal to log2(channel_pixel_num_max), represent one of single file it is logical
The bit wide of the maximum pixel number in road；M1 value is to need cumulative line number value into row of channels judgement；With different address storages not
With the cumulative and data of passage, it is therefore desirable to which N number of address stores the value of the cumulative sum of N number of passage；Data on each address
For K*M1 positions, a passage cumulative per K positions for a line and, so storing the cumulative of M1 row same channels on each address
With；
3-4-2, channel counter channel_cnt is defined, for realize channel counts；In passage commencing signal channel_
Start is that the value for making channel counter channel_cnt adds 1 for 1；When cycle rate counter PeriodCnt meters arrive its maximum
Channel counter is zeroed out；
3-4-3, realize RAM accesses and passage and accumulation state machine；It is when channel_cnt is more than or equal to 1, i.e., logical from second
Road starts, and using passage commencing signal channel_statr as the enabling signal of this state machine, enters after startup and reads RAM
State, channel counter channel_cnt value is read into data as address from RAM；Subsequently enter and shift and write RAM
State, the data read from RAM are moved to left into K positions, and make the value of low K positions be equal to and add up and register accumulate_sum's
Value, the data newly obtained are stored back to RAM channel_cnt addresses and channel_accumulate registers are given in unloading, with
This realizes the renewal of row；Row accumulation state is subsequently entered, channel_accumulate every K positions are added up, add up knot
Fruit is assigned to register channel_sum；Subsequently enter and compare state, by channel_sum and the passage threshold from host computer reception
Value is compared, and if being 1 more than or equal to result if passage threshold value, otherwise result is 0, is deposited at register comp；Subsequently enter
As a result storage state, N position result register result are defined, result register result is moved to right N-1 positions, and by highest order
Value is assigned to comp；Subsequently enter Idle state and wait next passage commencing signal from new starting state machine；
3-5, result register result is latched to register when cycle rate counter PeriodCnt is remembered to its maximum
ResultChannel；And reset register result, register ResultChannel value is exported to obtain dithering
As a result.
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| CN109146953A (en) * | 2018-09-11 | 2019-01-04 | 杭州电子科技大学 | The index face block upper limit based on FPGA separates shunting method |
| CN109660774A (en) * | 2018-11-29 | 2019-04-19 | 杭州电子科技大学 | Linear array based on FPGA misplaces, and image is compound to remove color Bian Fangfa |
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| CN109102540B (en) * | 2018-08-16 | 2022-01-28 | 杭州电子科技大学 | FPGA-based lower limit separation and lane division method for marked area blocks |
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| CN109146953B (en) * | 2018-09-11 | 2021-12-10 | 杭州电子科技大学 | FPGA-based upper limit separation and lane separation method for marked area blocks |
| CN109660774A (en) * | 2018-11-29 | 2019-04-19 | 杭州电子科技大学 | Linear array based on FPGA misplaces, and image is compound to remove color Bian Fangfa |
| CN109660774B (en) * | 2018-11-29 | 2020-12-01 | 杭州电子科技大学 | Linear array malposed image composite color edge removing method based on FPGA |
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