CN107895342B - Implementation method of high-speed color screening method based on FPGA - Google Patents
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Abstract
The invention discloses a method for realizing a high-speed color screening method based on FPGA, which comprises the steps of firstly carrying out pixel division on effective pixel numbers of a line acquired by a linear array CCD (charge coupled device), namely determining a starting pixel position and an ending pixel position, and dividing pixels positioned between the starting pixel and the ending pixel into N channels; then, single-point color judgment is carried out on each pixel, M groups of color threshold values received from an upper computer are used for carrying out real-time judgment on the collected pixel data, if the collected pixel data fall in the numerical range of at least one of the eight groups of color threshold values, the collected pixel data are stored as 1, and if not, the collected pixel data are 0; finally, channel judgment is carried out according to the comparison result of the accumulated value of each channel and the channel threshold value received from the upper computer to determine a color screening result; the method processes and judges the acquired image data in real time in a hardware mode, greatly improves the speed of color screening, reduces the cost and improves the integration level of the system.
Description
Technical Field
The invention belongs to the field of industrial machine vision, and particularly relates to a method for realizing a high-speed color screening method based on an FPGA (field programmable gate array).
Background
In the field of industrial machine vision, the color screening method for screening out the detected object meeting the color requirement is widely applied; the key to realizing the function of screening the colors of the detected objects is to design and realize a set of high-efficiency color screening algorithm, especially when the detected objects are in a high-speed motion state; in the conventional technology, the collection and processing of image data are usually separated, and the realization of an image processing algorithm is carried out on a DSP or an upper computer, so that the cost is high and the system integration is not facilitated; and the data transmission speed between the image data acquisition system and the processing system can limit the working speed of the whole system.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a method for realizing a high-speed color screening method based on an FPGA (field programmable gate array): firstly, pixel division is carried out on a row of effective pixels acquired by a linear array CCD, namely, the position of a starting pixel and the position of an ending pixel are determined, the pixels positioned between the starting pixel and the ending pixel are divided into N (60< ═ N < ═ 64) channels, then single-point color judgment is carried out on each pixel, and the acquired pixel data is judged in real time by using M (8< ═ M < ═ 16) groups of color threshold values received from an upper computer; if the collected pixel data falls within the numerical range of at least one of the M sets of color thresholds, saving the collected pixel data to be 1, otherwise, to be 0; and finally, channel judgment is carried out according to the comparison result of the accumulated value of each channel and the channel threshold value received from the upper computer, and a color screening result is determined.
The implementation steps of the high-speed color screening algorithm comprise:
the method comprises the following steps: pixel division is carried out on effective pixel number of linear array CCD
1-1, defining a starting pixel position register PixelStart and an ending pixel position register PixelEnd, and assigning values to the two registers by an upper computer;
1-2, defining a channel _ pixel _ num register to be divided into a channel _ pixel _ num _ min register and a channel _ pixel _ num _ max register; wherein, the channel _ pixel _ num _ min register stores the pixel number value of the channel with less pixel number, and the value of the register is (Pixel end-Pixel Start)/N; a channel _ pixel _ num _ max register stores pixel numerical values of channels with a large number of pixels, and the value of the register is channel _ pixel _ num _ min + 1;
1-3, defining an N-bit register channel _ pixel _ num _ flag for indicating the number of pixels of N channels, wherein in the 0-N bits, if the value of the bit is 1, the number of pixels of the channel is the value of the register channel _ pixel _ num _ max, otherwise, the number of pixels of the channel is the value of the register channel _ pixel _ num _ min;
1-4, subtracting channel _ pixel _ num _ min _ N from register pixeend to obtain value N1, 0< ═ N1< ═ N; and registers channel _ pixel _ num _ flag from 0 to N1 position 1, the remaining position 0.
Step two: single point color decision for each pixel
2-1, defining M groups of color threshold registers, wherein each group comprises 3 color threshold registers, and the total number of the color threshold registers is 3M; wherein, the 3 registers in each group are respectively a threshold register R _ max _ min of the color R, a threshold register G _ max _ min of the color G and a threshold register B _ max _ min of the color B, which are all 16-bit registers; the low 8 bits register a low threshold value, and the high 8 bits register a high threshold value; obtaining values of 3 × M color threshold registers from an upper computer;
2-2, for one image data collected in real time, if the value of the color R is greater than or equal to the value of the lower 8 bits of R _ max _ min and less than or equal to the value of the upper 8 bits of R _ max _ min, the value of the color G is greater than or equal to the value of the lower 8 bits of G _ max _ min and less than or equal to the value of the upper 8 bits of G _ max _ min, and the value of the color B is greater than or equal to the value of the lower 8 bits of B _ max _ min and less than or equal to the value of the upper 8 bits of B _ max _ min, the result is saved as 1, otherwise, the result is 0;
2-3, copying the same comparison structure of the M groups, simultaneously comparing one image data acquired in real time with the color threshold values of the M groups, generating a comparison result of 1 bit 0 or 1 in each group, and combining the M comparison results into 1M bit value to be registered in a single-point comparison result register CMPout of the M bit.
Step three: determining color screening results by channel judgment
3-1, defining a period counter PeriodCnt to realize period cycle counting, wherein the counting value is an effective pixel value of one line acquired by the linear array CCD and is counted in the effective pixel period;
3-2, generating a channel start signal channel _ start;
3-2-1, defining a line counter line _ cnt and initializing it to a value greater than 0; this may avoid generating a channel _ start signal when the period calculator PeriodCnt is equal to 0; when the period counter is equal to 1, namely a new CCD acquisition period starts, the value of the line _ cnt of the line counter is equal to the position value of the initial pixel; when the channel start signal channel _ start is 1 and the value of the line _ cnt is smaller than the position value of the end pixel, making the value of the line _ cnt equal to the value of the line _ cnt plus the value of the number of pixels of the corresponding channel; i.e., line _ cnt is equal to line _ cnt plus channel _ pixel _ num _ min plus the least significant bits of channel _ pixel _ num _ flag; and shift channel _ pixel _ num _ flag by 1 bit to the right:
3-2-2, when the value of the period counter PeriodCnt is equal to the value of the line counter line _ cnt, making a channel start signal channel _ stat be 1 and the rest time be 0;
3-3, defining an accumulation register pixel _ accumulation and an accumulation and register accumulation _ sum; and determining whether the accumulation register accumulates according to the single-point judgment result of each pixel point: if the value of at least 1 bit in M bits in the single-point comparison result register CMPout is 1, adding 1 to the accumulation register, otherwise, keeping the original value of the accumulation register; when a channel start signal channel _ stall is 1, latching the value of an accumulation register pixel _ accumulation into an accumulation sum register accumulation _ sum, and clearing the accumulation register pixel _ accumulation;
3-4, due to the characteristics of the linear array CCD, only one row of effective pixels can be acquired in one image data acquisition period; when channel judgment is carried out, accumulation sums of multiple lines of same channels need to be accumulated again to obtain a final accumulation result of one channel, so that the accumulation sums of all the channels in the current line need to be stored, and the accumulation sums of the multiple lines of same channels need to be accumulated;
3-4-1, calling the macro function module to generate an on-chip RAM memory of size N K M1 bits with address width log2N bits, data width K M1 bits; where the value of K is equal to log2(channel _ pixel _ num _ max) indicating a bit width of a maximum number of pixels of one channel of a single row; the value of M1 is the row number that needs to be accumulated to make a channel decision. Different addresses are used to store the accumulated sum data for different channels, so that N addresses are required to store the values of the accumulated sums for N channels. The data at each address is K × M1 bits, and each K bit is the accumulated sum of one channel in one row, so that the accumulated sum of M1 rows of the same channel is stored at each addressAdding;
3-4-2, defining channel counter channel _ cnt for realizing channel counting; when the channel start signal channel _ start is 1, the value of the channel counter channel _ cnt is added with 1; clearing the channel counter when the period counter period counts to the maximum value;
3-4-3, realizing RAM access, channel and accumulation state machine; when the channel _ cnt is greater than or equal to 1, starting from the second channel, taking a channel start signal channel _ stat as a start signal of the state machine, entering a read RAM state after starting, and taking the value of a channel counter channel _ cnt as an address to read data from the RAM; and then entering a shift and write RAM state, shifting the data read from the RAM by K bits to the left, making the value of the low K bit equal to the value of an accumulation sum register (accumulation sum _ sum), storing the newly obtained data back to the channel _ cnt address of the RAM and transferring the data to a channel _ accumulation register so as to realize the updating of the data. Then entering a row accumulation state, accumulating every K bits of the channel _ accumulation, and giving an accumulation result to a register channel _ sum; and then entering a comparison state, comparing the channel _ sum with a channel threshold value received from the upper computer, and if the channel _ sum is greater than or equal to the channel threshold value, the result is 1, otherwise, the result is 0, and the result is registered in a register comp. Then enter the result storage state, define the N bit result register result, shift the result register result N-1 bit to the right, and assign the value of the highest bit to comp. Then entering an idle state to wait for a next channel starting signal to start the state machine from the beginning;
3-5, latching the result register result to the register ResultChannel when the period counter period count records to the maximum value; and resetting the register result, and outputting the value of the register ResultChannel to obtain a color screening result.
Compared with the prior art, the invention has the beneficial effects that: the high-speed color screening algorithm based on the FPGA is realized, the acquired image data is processed and judged in real time in a hardware mode, the color screening speed is greatly improved, the cost is reduced, and the integration level of the system is improved.
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FIG. 1 is a flow chart of a color screening algorithm
Detailed Description
A high-speed color screening algorithm based on FPGA is realized by dividing effective pixels of a line acquired by a linear array CCD into 64(N is 64) channels, performing single-point color judgment on image data acquired in real time, and storing the pixel result falling in at least one group of color threshold value range as 1, otherwise as 0. Accumulating the single-point judgment results in one channel, accumulating the accumulated sum of multiple rows of same channels, comparing the result with a channel threshold value, realizing channel judgment and determining a color screening result.
As shown in fig. 1: the color screening algorithm firstly obtains color threshold parameters, channel threshold parameters and pixel division parameters from an upper computer. And finally, outputting a color screening result after the color screening of N channels is finished, and then waiting for the sensor to start to collect the effective pixels of the next line.
The implementation steps of the high-speed color screening algorithm comprise:
the method comprises the following steps: pixel division is carried out on effective pixel number of linear array CCD
1-1, defining a starting pixel position register PixelStart and an ending pixel position register PixelEnd, and assigning values to the two registers by an upper computer;
1-2, defining a channel _ pixel _ num _ min register to store the pixel number value of the channel with the smaller pixel number, wherein the value of the register is (Pixel end-Pixel Start)/64;
1-3, defining a channel _ pixel _ num _ max register to store pixel numerical values of channels with a large number of pixels, wherein the value of the register is channel _ pixel _ num _ min + 1;
1-4, defining a 64-bit register channel _ pixel _ num _ flag to represent the number of pixels of 64 channels, wherein if the value of the bit is 1, the number of pixels of the channel is the value of the register channel _ pixel _ num _ max if the value of the bit is 0-64, otherwise, the number of pixels of the channel is the value of the register channel _ pixel _ num _ min;
1-5, subtracting channel _ pixel _ num _ min _ 64 from the register PixelEnd to obtain the value N1(0< ═ N1< ═ 64); and registers channel _ pixel _ num _ flag from 0 to N1 position 1, the remaining position 0.
Step two: single point color decision for each pixel
2-1, defining 8 groups of color threshold registers, wherein each group comprises 3 and 24; wherein, the 3 registers in each group are respectively a threshold register R _ max _ min of the color R, a threshold register G _ max _ min of the color G and a threshold register B _ max _ min of the color B, which are all 16-bit registers;
the low 8 bits register a low threshold value, and the high 8 bits register a high threshold value; obtaining values of 24 color threshold registers from an upper computer;
2-2, for one image data collected in real time, if the value of the color R is greater than or equal to the value of the lower 8 bits of R _ max _ min and less than or equal to the value of the upper 8 bits of R _ max _ min, the value of the color G is greater than or equal to the value of the lower 8 bits of G _ max _ min and less than or equal to the value of the upper 8 bits of G _ max _ min, and the value of the color B is greater than or equal to the value of the lower 8 bits of B _ max _ min and less than or equal to the value of the upper 8 bits of B _ max _ min, the result is saved as 1, otherwise, the result is 0;
2-3, copying 8 groups of same comparison structures, simultaneously comparing one image data acquired in real time with 8 groups of color threshold values, generating a comparison result of 1 bit 0 or 1 in each group, and combining the 8 comparison results into 1 single-point comparison result register CMPout with 8 bit values and storing the single-point comparison result register CMPout with 8 bits.
Step three: determining color screening results by channel judgment
3-1, defining a period counter PeriodCnt to realize period cycle counting, wherein the counting value is an effective pixel value of one line acquired by the linear array CCD and is counted in the effective pixel period;
3-2, generating a channel start signal channel _ start;
3-2-1, defining a line counter line _ cnt and initializing it to a value greater than 0; this may avoid generating a channel _ start signal when the period calculator PeriodCnt is equal to 0;
when the cycle counter equals 1, i.e. a new CCD acquisition cycle starts, the line is ordered
The value of the counter line _ cnt is equal to the position value of the start pixel; when the channel start signal channel _ start is 1 and the value of the line _ cnt is smaller than the position value of the end pixel, making the value of the line _ cnt equal to the value of the line _ cnt plus the value of the number of pixels of the corresponding channel; i.e., line _ cnt is equal to line _ cnt plus channel _ pixel _ num _ min plus the least significant bits of channel _ pixel _ num _ flag; and shift channel _ pixel _ num _ flag by 1 bit to the right:
3-2-2, when the value of the period counter PeriodCnt is equal to the value of the line counter line _ cnt, making a channel start signal channel _ stat be 1 and the rest time be 0;
3-3, defining an accumulation register pixel _ accumulation and an accumulation and register accumulation _ sum; and determining whether the accumulation register accumulates according to the single-point judgment result of each pixel point: if the value of at least 1 bit in 8 bits in the single-point comparison result register CMPout is 1, adding 1 to the accumulation register, otherwise, keeping the original value of the accumulation register; when a channel start signal channel _ stall is 1, latching the value of an accumulation register pixel _ accumulation into an accumulation sum register accumulation _ sum, and clearing the accumulation register pixel _ accumulation;
3-4, due to the characteristics of the linear array CCD, only one row of effective pixels can be acquired in one image data acquisition period; when channel judgment is carried out, accumulation sums of multiple lines of same channels need to be accumulated again to obtain a final accumulation result of one channel, so that the accumulation sums of all the channels in the current line need to be stored, and the accumulation sums of the multiple lines of same channels need to be accumulated;
3-4-1, calling the macro function module to generate an on-chip RAM memory with 64 x 6 x 44 bits, wherein the address width is 8 bits, and the data width is 6 x 44 bits; the maximum number of pixels for one lane of a single row is 6 bits wide, so that the accumulated sum of 44 rows of the same lane can be stored at each address;
3-4-2, defining channel counter channel _ cnt for realizing channel counting; when the channel start signal channel _ start is 1, the value of the channel counter channel _ cnt is added with 1; clearing the channel counter when the period counter period counts to the maximum value;
3-4-3, realizing RAM access, channel and accumulation state machine; when the channel _ cnt is greater than or equal to 1, starting from the second channel, taking a channel start signal channel _ stat as a start signal of the state machine, entering a read RAM state after starting, and taking the value of a channel counter channel _ cnt as an address to read data from the RAM; and then entering a shift and write RAM state, shifting the data read from the RAM by 6 bits to the left, making the value of the lower 6 bits equal to the value of an accumulation sum register (accumulation sum _ sum), storing the newly obtained data back to the channel _ cnt address of the RAM and transferring the data to a channel _ accumulation register so as to realize the updating of the data. Then entering a row accumulation state, accumulating every 6 bits of channel _ accumulation, and giving an accumulation result to a register channel _ sum; and then entering a comparison state, comparing the channel _ sum with a channel threshold value received from the upper computer, and if the channel _ sum is greater than or equal to the channel threshold value, the result is 1, otherwise, the result is 0, and the result is registered in a register comp. The result storage state is entered, a 64-bit result register result is defined, the result register result is shifted to the right by 63 bits, and the value of the highest bit is assigned to comp. Then entering an idle state to wait for a next channel starting signal to start the state machine from the beginning;
3-5, latching the result register result to the register ResultChannel when the period counter period count records to the maximum value; and resetting the register result, and outputting the value of the register ResultChannel to obtain a color screening result.
Claims (1)
1. An implementation method of a high-speed color screening method based on FPGA is characterized by comprising the following steps:
the method comprises the following steps: pixel division is carried out on effective pixel number of linear array CCD
1-1, defining a starting pixel position register PixelStart and an ending pixel position register PixelEnd, and assigning values to the two registers by an upper computer;
1-2, defining a channel _ pixel _ num register to be divided into a channel _ pixel _ num _ min register and a channel _ pixel _ num _ max register; wherein the channel _ pixel _ num _ min register stores a value of (PixelEnd-PixelStart)/N; the value stored by the channel _ pixel _ num _ max register is channel _ pixel _ num _ min + 1;
1-3, defining an N-bit register channel _ pixel _ num _ flag for indicating the number of pixels of N channels, wherein in the 0-N bits, if the value of the bit is 1, the number of pixels of the channel is the value of the register channel _ pixel _ num _ max, otherwise, the number of pixels of the channel is the value of the register channel _ pixel _ num _ min;
1-4, subtracting channel _ pixel _ num _ min _ N from register pixeend to obtain value N1, 0< ═ N1< ═ N; and the registers channel _ pixel _ num _ flag are from 0 to N1 position 1, and the rest positions are 0;
step two: single point color decision for each pixel
2-1, defining M groups of color threshold registers, wherein each group comprises 3 color threshold registers, and the total number of the color threshold registers is 3M; wherein, the 3 registers in each group are respectively a threshold register R _ max _ min of the color R, a threshold register G _ max _ min of the color G and a threshold register B _ max _ min of the color B, which are all 16-bit registers; the lower 8 bits register a lower 8 bits threshold value, and the upper 8 bits register an upper 8 bits threshold value; obtaining values of 3 × M color threshold registers from an upper computer;
2-2, for one pixel data collected in real time, if the value of the color R is greater than or equal to the value of the lower 8 bits of R _ max _ min and less than or equal to the value of the upper 8 bits of R _ max _ min, the value of the color G is greater than or equal to the value of the lower 8 bits of G _ max _ min and less than or equal to the value of the upper 8 bits of G _ max _ min, and the value of the color B is greater than or equal to the value of the lower 8 bits of B _ max _ min and less than or equal to the value of the upper 8 bits of B _ max _ min, saving the result as 1, otherwise, saving the result as 0;
2-3, copying the same comparison structure of the M groups, simultaneously comparing one image data acquired in real time with the color threshold values of the M groups, generating a comparison result of 1 bit 0 or 1 in each group, and combining the M comparison results into 1M bit value to be registered in a single-point comparison result register CMPout of the M bit;
step three: determining color screening results by channel judgment
3-1, defining a period counter PeriodCnt to realize period cycle counting, wherein the counting value is an effective pixel value of one line acquired by the linear array CCD and is counted in the effective pixel period;
3-2, generating a channel start signal channel _ start;
3-2-1, defining a line counter line _ cnt and initializing it to a value greater than 0; avoiding generating a channel _ start signal when the period calculator PeriodCnt is equal to 0; when the period counter is equal to 1, namely a new CCD acquisition period starts, the value of the line _ cnt of the line counter is equal to the position value of the initial pixel; when the channel start signal channel _ start is 1 and the value of the line _ cnt is smaller than the position value of the end pixel, making the value of the line _ cnt equal to the value of the line _ cnt plus the value of the number of pixels of the corresponding channel; i.e., line _ cnt is equal to line _ cnt plus channel _ pixel _ num _ min plus the least significant bits of channel _ pixel _ num _ flag; and shift channel _ pixel _ num _ flag by 1 bit to the right:
3-2-2, when the value of the period counter PeriodCnt is equal to the value of the line counter line _ cnt, making the channel start signal channel _ start 1, and the rest time 0;
3-3, defining an accumulation register pixel _ accumulation and an accumulation and register accumulation _ sum; and determining whether the accumulation register accumulates according to the single-point judgment result of each pixel point: if the value of at least 1 bit in M bits in the single-point comparison result register CMPout is 1, adding 1 to the accumulation register, otherwise, keeping the original value of the accumulation register; when the channel start signal channel _ start is 1, latching the value of the accumulation register pixel _ accumulation into the accumulation sum register accumulation _ sum, and clearing the accumulation register pixel _ accumulation;
3-4, due to the characteristics of the linear array CCD, only one row of effective pixels can be acquired in one image data acquisition period; when channel judgment is carried out, accumulation sums of multiple lines of same channels need to be accumulated again to obtain a final accumulation result of one channel, so that the accumulation sums of all the channels in the current line need to be stored, and the accumulation sums of the multiple lines of same channels need to be accumulated;
3-4-1, Call macrosThe function module generates an on-chip RAM memory of size N K M1 bits with address width log2N bits, data width K M1 bits; where the value of K is equal to log2(channel _ pixel _ num _ max) indicating a bit width of a maximum number of pixels of one channel of a single row; the value of M1 is the row number value to be accumulated for channel decision; storing the accumulated sum data of different channels with different addresses, thus requiring N addresses to store the values of the accumulated sums of N channels; the data at each address is K M1 bits, and each K bit is the accumulated sum of one channel in one row, so that the accumulated sum of the same channel in M1 rows is stored at each address;
3-4-2, defining channel counter channel _ cnt for realizing channel counting; when the channel start signal channel _ start is 1, the value of the channel counter channel _ cnt is added with 1; clearing the channel counter when the period counter period counts to the maximum value;
3-4-3, realizing RAM access, channel and accumulation state machine; when the channel _ cnt is larger than or equal to 1, starting from the second channel, taking a channel starting signal channel _ start as a starting signal of the state machine, entering a read RAM state after starting, and taking the value of a channel counter channel _ cnt as an address to read data from the RAM; then entering a state of shifting and writing in the RAM, shifting the data read out from the RAM to the left by K bits, making the value of the low K bit equal to the value of an accumulation sum register (accumulation sum _ sum), storing the newly obtained data back to the channel _ cnt address of the RAM and transferring the newly obtained data to a channel _ accumulation register so as to realize the updating of the data; then entering a row accumulation state, accumulating every K bits of the channel _ accumulation, and giving an accumulation result to a register channel _ sum; then entering a comparison state, comparing channel _ sum with a channel threshold value received from the upper computer, if the channel _ sum is greater than or equal to the channel threshold value, the result is 1, otherwise, the result is 0, and registering in a register comp; then entering a result storage state, defining an N-bit result register result, right-shifting the result register result by N-1 bits, and assigning the value of the highest bit as the value stored by the register comp; then entering an idle state to wait for a next channel starting signal to start the state machine from the beginning;
3-5, latching the result register result to the register ResultChannel when the period counter period count records to the maximum value; and resetting the register result, and outputting the value of the register ResultChannel to obtain a color screening result.
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