CN110996005B - Real-time digital image enhancement method and system - Google Patents
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Abstract
The invention relates to a real-time digital image enhancement method and a real-time digital image enhancement system, which belong to the technical field of digital image processing, when a digital image is processed, a gray level image acquired by an industrial camera is acquired, the gray level image is transmitted to a first data conversion module through a Camera Link input interface for serial-parallel conversion, and then is transmitted to an FPGA chip, the FPGA chip is used as a core processing unit and a main control unit for carrying out logic time sequence control on the whole system, the image is processed, then the image data is transmitted to a second data conversion module for serial-parallel conversion again, and then the enhanced image is output through a Camera Link output interface. The invention is mainly realized by utilizing the internal resources of the FPGA, and adopts a pipeline mode to process data, thereby improving the image processing speed, occupying less resources and reducing the power consumption of the FPGA.
Description
Technical Field
The invention relates to the technical field of digital image processing, in particular to a real-time digital image enhancement method and a real-time digital image enhancement system.
Background
Digital Image Processing (Digital Image Processing) technology, that is, a process of converting Image information into Digital information by a certain means and Processing the Digital information by a computer to obtain a result. With the rapid development of information technology, digital image processing technology is now widely used in various fields, such as remote sensing and aerospace, industrial, agricultural, biomedical, and military police fields. The FPGA is the most integrated in an application-specific integrated circuit, provides rich logic resources, an internal memory and a special DSP, focuses on parallel execution of codes, and has the main significance that the functions of hardware can be modified by programming like software, and the FPGA is generally suitable for engineering projects under high-speed sampling frequency. The image processing is carried out by adopting hardware, the processing speed can be greatly improved, but the problems of large FPGA resource consumption and high energy consumption still exist in the traditional digital image enhancement processing method based on the FPGA.
Disclosure of Invention
Therefore, it is necessary to provide a real-time digital image enhancement method and system for solving the problems of large FPGA resource consumption and high energy consumption of the current digital image enhancement processing method based on the FPGA.
In order to solve the problems, the invention adopts the following technical scheme:
a method of real-time digital image enhancement, the method comprising the steps of:
acquiring a gray level image acquired by an industrial camera through a CameraLink input interface;
performing data format conversion on the gray level image by using a first data conversion module, and sending the converted image into an FPGA chip;
the FPGA chip carries out histogram statistics on the converted image and stores the statistical data in a DPRAM in the chip; the DPRAM comprises an A port data signal, a B port data signal, an A port writing signal, an A port address and a B port address; the FPGA chip comprises a statistic module for performing histogram statistics and a stretching module for performing histogram stretching operation, and the state conversion process of the statistic module in the histogram statistics process comprises the following steps:
(1) an idle state: initializing the address of the port A to-1, entering a DPRAM zero clearing state if the statistical request is effective in an idle state, and otherwise, maintaining the current state;
(2) DPRAM clear state: the A port writing signal is set to 1, and the data of each address of the A port is cleared; when the DPRAM is cleared, if the address of the A port of the DPRAM is the maximum gray value of the pixel, entering a state of waiting for the end of the current frame, and if not, maintaining the current state;
(3) waiting for the current frame to end: performing no related operation, and entering a histogram statistical state after the current frame is finished; when waiting for the end of the current frame, if the frame is invalid, entering a state of waiting for a new frame to come, otherwise, maintaining the current state;
(4) wait for new frame to come state: no relevant operation is carried out; when waiting for a new frame, if the frame is valid, entering a histogram statistical state, otherwise, maintaining the current state;
(5) histogram statistical state: counting all gray values corresponding to the A port address when the image data are effective; when histogram statistics is carried out, if a frame is valid, the current state is maintained, otherwise, a histogram reading initialization state is entered;
(6) histogram readout initialization state: initializing the address of the port B to-1, and directly entering a histogram reading state after initialization;
(7) histogram readout state: reading out the histogram through the ascending order of the B port addresses; when histogram sequential reading is carried out, when the B port address read out from the DPRAM is the maximum pixel gray value, the reading is finished and the DPRAM enters an idle state, otherwise, the current state is maintained;
after the FPGA chip completes histogram statistics, reading data from the DPRAM, performing histogram stretching operation on the read data, and sending enhanced image data obtained after the stretching operation to a second data conversion module;
the second data conversion module performs data format conversion on the enhanced image data and sends the converted image data to a CameraLink output interface;
the CameraLink output interface outputs the enhanced digital image.
Correspondingly, the invention also provides a real-time digital image enhancement system, which comprises:
the camera Link input interface is used for acquiring a gray level image acquired by an industrial camera and sending the gray level image to the first data conversion module;
the first data conversion module is used for performing data format conversion on the gray level image and sending the converted image data into an FPGA chip;
the FPGA chip is used for carrying out histogram statistics on the converted image, storing statistical data in a DPRAM in the chip, reading out the data from the DPRAM after the histogram statistics is finished, carrying out histogram stretching operation on the read-out data, and sending enhanced image data obtained after the stretching operation into a second data conversion module; the DPRAM comprises an A port data signal, a B port data signal, an A port writing signal, an A port address and a B port address; the FPGA chip comprises a statistic module for performing histogram statistics and a stretching module for performing histogram stretching operation, and the state conversion process of the statistic module in the histogram statistics process comprises the following steps:
(1) an idle state: initializing the address of the port A to-1, entering a DPRAM zero clearing state if the statistical request is effective in an idle state, and otherwise, maintaining the current state;
(2) DPRAM clear state: the A port writing signal is set to 1, and the data of each address of the A port is cleared; when the DPRAM is cleared, if the address of the A port of the DPRAM is the maximum gray value of the pixel, entering a state of waiting for the end of the current frame, and if not, maintaining the current state;
(3) waiting for the current frame to end: performing no related operation, and entering a histogram statistical state after the current frame is finished; when waiting for the end of the current frame, if the frame is invalid, entering a state of waiting for a new frame to come, otherwise, maintaining the current state;
(4) wait for new frame to come state: no relevant operation is carried out; when waiting for a new frame, if the frame is valid, entering a histogram statistical state, otherwise, maintaining the current state;
(5) histogram statistical state: counting all gray values corresponding to the A port address when the image data are effective; when histogram statistics is carried out, if a frame is valid, the current state is maintained, otherwise, a histogram reading initialization state is entered;
(6) histogram readout initialization state: initializing the address of the port B to-1, and directly entering a histogram reading state after initialization;
(7) histogram readout state: reading out the histogram through the ascending order of the B port addresses; when histogram sequential reading is carried out, when the B port address read out from the DPRAM is the maximum pixel gray value, the reading is finished and the DPRAM enters an idle state, otherwise, the current state is maintained;
the second data conversion module is used for performing data format conversion on the enhanced image data and sending the converted image data to the CameraLink output interface;
and the CameraLink output interface is used for outputting the enhanced digital image.
Compared with the prior art, the invention has the following beneficial effects:
when the digital image is processed, an industrial camera is used for collecting the image in real time, the image is transmitted to the first data conversion module through the Camera Link input interface to be subjected to serial-parallel conversion, then the image is transmitted to the FPGA chip, the FPGA chip is used as a core processing unit and a main control unit to perform logic time sequence control on the whole system, the image is processed, then the image data is transmitted to the second data conversion module to be subjected to serial-parallel conversion again, and then the enhanced image is output through the Camera Link output interface. The invention provides a real-time digital image enhancement method based on a Camera Link and an FPGA (field programmable gate array), aiming at the hardware implementation characteristics, the algorithm implementation process is optimized, the functions are mainly realized by utilizing the internal resources of the FPGA, the data processing is carried out in a pipeline mode, the image processing speed is improved, the occupied resources are less, the histogram stretching work can be completed under the condition of extremely few occupied resources, the energy consumption is reduced, and the power consumption of the FPGA is reduced. The invention effectively saves a large amount of internal resources of the FPGA, reduces the power consumption and improves the running speed.
Drawings
FIG. 1 is a flow chart of a method for enhancing a real-time digital image according to one embodiment of the present invention;
FIG. 2 is a schematic diagram of a DPRAM module;
FIG. 3 is a schematic diagram of a statistical module;
FIG. 4 is a diagram illustrating a state transition process of a statistic module during histogram statistics;
FIG. 5 is a schematic diagram of a real-time digital image enhancement system according to another embodiment of the present invention;
FIG. 6 is a schematic diagram of a real-time digital image enhancement system according to an embodiment of the present invention.
Detailed Description
The invention provides a real-time digital image enhancement method and a real-time digital image enhancement system based on a CameraLink and an FPGA, which can achieve the purpose of secondary compiling of an algorithm on the basis of not changing a hardware system and greatly improve the flexibility of the system. The technical solution of the present invention will be described in detail with reference to the accompanying drawings and preferred embodiments.
In one embodiment, as shown in fig. 1, the present invention discloses a real-time digital image enhancement method, comprising the following steps:
step S1: acquiring a gray level image acquired by an industrial camera through a CameraLink input interface;
step S2: performing data format conversion on the gray level image by using a first data conversion module, and sending the converted image into an FPGA chip;
step S3: the FPGA chip carries out histogram statistics on the converted image and stores the statistical data in a DPRAM in the chip;
step S4: after finishing histogram statistics, the FPGA chip reads data from the DPRAM, performs histogram stretching operation on the read data, and sends enhanced image data obtained after the stretching operation to a second data conversion module;
step S5: the second data conversion module performs data format conversion on the enhanced image data and sends the converted image data to a CameraLink output interface;
step S6: the CameraLink output interface outputs the enhanced digital image.
Specifically, the real-time digital image enhancement method of the embodiment adopts a histogram correlation algorithm, and realizes the real-time enhancement effect of the digital image through the FPGA. Collecting images by using an industrial CameraLink camera at an input end, and inputting the collected gray level images through a CameraLink input interface; the method comprises the steps that after a gray image is subjected to data format conversion through a first data conversion module (such as a DS90CR288 chip), the converted image is sent to an FPGA chip, the FPGA chip is of a parallel computing structure and can achieve high-speed parallel data processing, the FPGA chip firstly carries out histogram statistics on the converted image by utilizing internal resources, statistical data are stored in a DPRAM (dual port RAM) in the FPGA chip, the data are read out from the DPRAM after the statistics is completed, a divider in the FPGA chip is called to carry out histogram stretching operation, enhanced image data are obtained after the stretching operation, after the histogram stretching is completed, the enhanced image data are subjected to data format conversion through a second data conversion module (such as a DS90CR287 chip), and finally the enhanced digital image is output through a CameraLink output interface.
When the digital image is processed, an industrial camera is used for collecting the image in real time, the image is transmitted to the first data conversion module through the Camera Link input interface to be subjected to serial-parallel conversion, then the image is transmitted to the FPGA chip, the FPGA chip is used as a core processing unit and a main control unit to perform logic time sequence control on the whole system, the image is processed, then the image data is transmitted to the second data conversion module to be subjected to serial-parallel conversion again, and then the enhanced image is output through the Camera Link output interface. The invention provides a real-time digital image enhancement method based on a Camera Link and an FPGA (field programmable gate array), aiming at the hardware implementation characteristics, the algorithm implementation process is optimized, the functions are mainly realized by utilizing the internal resources of the FPGA, the data processing is carried out in a pipeline mode, the image processing speed is improved, the occupied resources are less, the histogram stretching work can be completed under the condition of extremely few occupied resources, the energy consumption is reduced, and the power consumption of the FPGA is reduced. The invention effectively saves a large amount of internal resources of the FPGA, reduces the power consumption and improves the running speed.
In this embodiment, the first data conversion module may adopt a DS90CR288 chip, and the second data conversion module may adopt a DS90CR287 chip. The DS90CR288 chip can convert the high-speed serial differential signal of 4bits into the parallel signal of 28bits and correspondingly input the parallel signal into the FPGA chip.
The FPGA chip in the embodiment comprises a statistic module and a stretching module, wherein the statistic module is used for carrying out histogram statistics on the converted image, and the stretching module is used for carrying out histogram stretching operation on the read data.
When the FPGA is used for histogram statistics, address information is needed to count the number of pixels with different gray values, and meanwhile, a counting module needs to be matched with other time sequences, so that a DPRAM in a chip is used as a cache memory, the DPRAM module is shown in FIG. 2, ADDRA and ADDRB are respectively an A port address and a B port address, DIA is an A port data signal, DOB is a B port data signal, WRA is an A port write-in signal, DAVL represents that data is valid, PIX represents the corresponding gray value of the pixel, DIA and DOB are stored gray value counts, and +1 represents that the number of pixels with a certain gray value is increased by 1.
The statistical block diagram is shown in fig. 3, where HIST _ CALC represents histogram statistics, HIST _ Req represents a statistical request, datadvalid represents valid DATA, HIST _ VAL represents valid statistical DATA, HIST _ DATA represents statistical DATA, a represents an a-port address of the DPRAM block, and B represents a B-port address of the DPRAM block.
Due to the parallel characteristic of the FPGA, when the FPGA is programmed by using a Verilog HDL language, the fact that all modules work simultaneously needs to be considered, a specific task needs to be completed in a plurality of time periods, and a plurality of enabling signals are used for connecting different modules, but the method is quite complex, so that the histogram statistical process of the statistical module adopts the idea of a three-section state machine. The state transition process of the statistical module in the histogram statistical process is shown in fig. 4, and the specific process of each state transition is as follows:
(1) IDLE state (IDLE): initializing an A port address to-1, entering a DPRAM zero clearing state if a counting request (HIST _ Req) is valid in an idle state, and otherwise, maintaining the current state;
(2) DPRAM clear state (CLR _ RAM): the A port writing signal is set to 1, and the data of each address of the A port is cleared; when the DPRAM is cleared, if the address of the A port of the DPRAM is the maximum gray value of the pixel, entering a state of waiting for the end of the current frame, and if not, maintaining the current state;
(3) WAIT for current frame end state (WAIT _ CUR _ FRM _ DONE): performing no related operation, and entering a histogram statistical state after the current frame is finished; when waiting for the end of the current frame, if the frame is invalid, entering a state of waiting for a new frame to come, otherwise, maintaining the current state;
(4) WAIT for NEW frame coming state (WAIT _ NEW _ FRM): no relevant operation is carried out; when waiting for a new frame, if the frame is valid, entering a histogram statistical state, otherwise, maintaining the current state;
(5) histogram statistical state (HIST _ CALC): counting all gray values corresponding to the A port address when the image data are effective; when histogram statistics is carried out, if a frame is valid, the current state is maintained, otherwise, a histogram reading initialization state is entered;
(6) histogram readout initialization state (HIST _ READ _ INIT): initializing the address of the port B to-1, and directly entering a histogram reading state after initialization;
(7) histogram READ state (HIST _ READ): and reading the histogram in the ascending order of the B port addresses, and when the B port addresses read out from the DPRAM are the maximum pixel gray value, ending the reading and entering an idle state, otherwise, maintaining the current state.
The process of performing the histogram stretching operation by the stretching module in the FPGA chip includes the following steps, as shown in fig. 5:
(1) expressing a gray function of an input image by f (x, y), and acquiring a minimum gray level a and a maximum gray level b of the gray image, wherein the minimum gray level a and the maximum gray level b are expressed by a formula respectively as follows:
a＝min[f(x,y)]
b＝max[f(x,y)]
after the minimum gray level a and the maximum gray level b are obtained, a stretching interval b-a can be obtained through calculation;
(2) stretching the minimum gray level a and the maximum gray level b to two ends of a horizontal axis (gray level) of a histogram until the minimum gray level is equal to 0 and the maximum gray level is equal to 255, wherein after stretching operation, the histogram is uniformly distributed in a range of the gray level of 0-255 to obtain enhanced image data, and a gray function g (x, y) of the enhanced image is as follows:
further, before the histogram stretching operation, the stretching module further performs a step of calculating a threshold, where the step specifically includes:
(1) firstly, the work to be carried out is still gray level histogram statistics, and the obtained function is marked as F (i);
(2) then taking the histograms from 0 to k for summation operation, and recording as S (k) as shown in a formula (1);
(3) two suitable thresholds P and Q are set artificially, and when the left end is stretched to a ═ k or the right end is stretched to b ═ k, the histogram sum needs to satisfy the following two conditions, as shown in equations (2) and (3).
As a specific implementation manner, the number of the first data conversion modules, the number of the second data conversion modules, the number of the statistical modules, and the number of the stretching modules are two, the two first data conversion modules are respectively connected with the CameraLink input interface, and the two second data conversion modules are respectively connected with the CameraLink output interface. The two symmetrical data processing links are formed by the two first data conversion modules, the two second data conversion modules, the two statistical modules and the two stretching modules, so that the larger data processing amount, the higher processing speed and the higher efficiency can be realized.
In another embodiment, the present invention provides a real-time digital image enhancement system, as shown in fig. 5, comprising:
the camera Link input interface 1 is used for acquiring a gray image acquired by an industrial camera and sending the gray image to the first data conversion module 2;
the first data conversion module 2 is used for performing data format conversion on the gray level image and sending the converted image data into the FPGA chip 3;
the FPGA chip 3 is used for carrying out histogram statistics on the converted image, storing the statistical data in a DPRAM in the chip, reading out the data from the DPRAM after the histogram statistics is finished, carrying out histogram stretching operation on the read-out data, and sending the enhanced image data obtained after the stretching operation into the second data conversion module 4;
the second data conversion module 4 is configured to perform data format conversion on the enhanced image data, and send the converted image data to the CameraLink output interface 5;
and a CameraLink output interface 5 for outputting the enhanced digital image.
Specifically, the real-time digital image enhancement system of the embodiment adopts a histogram correlation algorithm, and realizes the real-time enhancement effect of the digital image through the FPGA. Collecting images by using an industrial CameraLink camera at an input end, and inputting the collected gray level images through a CameraLink input interface 1; after the gray image is subjected to data format conversion through the first data conversion module 2 (for example, a DS90CR288 chip), the converted image is sent to the FPGA chip 3, the FPGA chip 3 is of a parallel computing structure and can realize high-speed parallel data processing, the FPGA chip 3 firstly performs histogram statistics on the converted image by using internal resources thereof, the counted data is stored in a DPRAM (dual port RAM) in the chip, the data is read out from the DPRAM after the statistics is completed, a divider in the FPGA chip is called to perform histogram stretching operation, the enhanced image data is obtained after the stretching operation, the enhanced image data is subjected to data format conversion through the second data conversion module 4 (for example, the DS90CR287 chip) after the histogram stretching is completed, and finally, the enhanced digital image is output through the CameraLink output interface 5. The Flash module is used for storing configuration files, and programming is carried out on the FPGA chip 3 through the Flash module after each time of power-on.
When the digital image is processed, an industrial camera is used for collecting the image in real time, the image is transmitted to the first data conversion module 2 through the Camera Link input interface 1 for serial-parallel conversion, then the image is transmitted to the FPGA chip 3, the FPGA chip 3 serves as a core processing unit and a main control unit for logic time sequence control of the whole system, the image is processed, then the image data is transmitted to the second data conversion module 4 for serial-parallel conversion again, and then the enhanced image is output through the Camera Link output interface 5. The invention provides a real-time digital image enhancement method based on a Camera Link and an FPGA (field programmable gate array), aiming at the hardware implementation characteristics, the algorithm implementation process is optimized, the functions are mainly realized by utilizing the internal resources of the FPGA, the data processing is carried out in a pipeline mode, the image processing speed is improved, the occupied resources are less, the histogram stretching work can be completed under the condition of extremely few occupied resources, the energy consumption is reduced, and the power consumption of the FPGA is reduced. The invention effectively saves a large amount of internal resources of the FPGA, reduces the power consumption and improves the running speed.
In this embodiment, the first data conversion module 2 may adopt a DS90CR288 chip, and the second data conversion module 4 may adopt a DS90CR287 chip. The DS90CR288 chip can convert the high-speed serial differential signal of 4bits into the parallel signal of 28bits and correspondingly input the parallel signal into the FPGA chip.
The FPGA chip 3 in the embodiment comprises a statistical module 3-1 and a stretching module 3-2, wherein the statistical module 3-1 is used for carrying out histogram statistics on the converted image, and the stretching module 3-2 is used for carrying out histogram stretching operation on the read data.
When the FPGA is used for histogram statistics, address information is needed to count the number of pixels with different gray values, and meanwhile, a statistical module 3-1 needs to be matched with other time sequences, so that an on-chip DPRAM is used as a cache memory, a schematic diagram of the DPRAM module is shown in FIG. 2, ADDRA and ADDRB are respectively an A-port address and a B-port address, DIA is an A-port data signal, DOB is a B-port data signal, WRA is an A-port write signal, DAVL indicates that data is valid, PIX indicates the corresponding pixel gray value, DIA and DOB are stored gray value counts, and +1 indicates that the number of pixels with a certain gray value is increased by 1.
The schematic diagram of the statistic module 3-1 is shown in fig. 3, where HIST _ CALC represents histogram statistics, HIST _ Req represents a statistic request, DATADVAL represents valid DATA, HIST _ VAL represents valid statistic DATA, HIST _ DATA represents statistic DATA, a represents an a-port address of the DPRAM module, and B represents a B-port address of the DPRAM module.
Due to the parallel characteristic of the FPGA, when the FPGA is programmed by using a Verilog HDL language, the fact that all modules work simultaneously needs to be considered, a specific task needs to be completed in a plurality of time periods, and a plurality of enabling signals are used for connecting different modules, but the method is quite complex, so that the histogram statistical process of the statistical module 3-1 adopts the thought of a three-section state machine. The state transition process of the statistical module 3-1 in the histogram statistical process is shown in fig. 4, and the specific process of each state transition is as follows:
(1) IDLE state (IDLE): initializing an A port address to-1, entering a DPRAM zero clearing state if a counting request (HIST _ Req) is valid in an idle state, and otherwise, maintaining the current state;
(2) DPRAM clear state (CLR _ RAM): the A port writing signal is set to 1, and the data of each address of the A port is cleared; when the DPRAM is cleared, if the address of the A port of the DPRAM is the maximum gray value of the pixel, entering a state of waiting for the end of the current frame, and if not, maintaining the current state;
(3) WAIT for current frame end state (WAIT _ CUR _ FRM _ DONE): performing no related operation, and entering a histogram statistical state after the current frame is finished; when waiting for the end of the current frame, if the frame is invalid, entering a state of waiting for a new frame to come, otherwise, maintaining the current state;
(4) WAIT for NEW frame coming state (WAIT _ NEW _ FRM): no relevant operation is carried out; when waiting for a new frame, if the frame is valid, entering a histogram statistical state, otherwise, maintaining the current state;
(5) histogram statistical state (HIST _ CALC): counting all gray values corresponding to the A port address when the image data are effective; when histogram statistics is carried out, if a frame is valid, the current state is maintained, otherwise, a histogram reading initialization state is entered;
(6) histogram readout initialization state (HIST _ READ _ INIT): initializing the address of the port B to-1, and directly entering a histogram reading state after initialization;
(7) histogram READ state (HIST _ READ): and reading the histogram in the ascending order of the B port addresses, and when the B port addresses read out from the DPRAM are the maximum pixel gray value, ending the reading and entering an idle state, otherwise, maintaining the current state.
The stretching module 3-2 in the FPGA chip 3 includes an obtaining submodule and a stretching submodule, as shown in fig. 5:
(1) expressing a gray function of an input image by f (x, y), and acquiring a minimum gray level a and a maximum gray level b of the gray image, wherein the minimum gray level a and the maximum gray level b are expressed by a formula respectively as follows:
a＝min[f(x,y)]
b＝max[f(x,y)]
after the minimum gray level a and the maximum gray level b are obtained, a stretching interval b-a can be obtained through calculation;
(2) stretching the minimum gray level a and the maximum gray level b to two ends of a horizontal axis (gray level) of a histogram until the minimum gray level is equal to 0 and the maximum gray level is equal to 255, wherein after stretching operation, the histogram is uniformly distributed in a range of the gray level of 0-255 to obtain enhanced image data, and a gray function g (x, y) of the enhanced image is as follows:
further, the stretching module further comprises a threshold value solving module, and the threshold value solving module solves the threshold value through the following steps:
(1) firstly, the work to be carried out is still gray level histogram statistics, and the obtained function is marked as F (i);
(2) then taking the histograms from 0 to k for summation operation, and recording as S (k) as shown in a formula (1);
(3) two suitable thresholds P and Q are set artificially, and when the left end is stretched to a ═ k or the right end is stretched to b ═ k, the histogram sum needs to satisfy the following two conditions, as shown in equations (2) and (3).
As a specific implementation manner, as shown in fig. 6, two first data conversion modules 2, two second data conversion modules 3, two statistical modules 3-1, and two stretching modules 3-2 are provided, the two first data conversion modules 2 are respectively connected to the CameraLink input interface 1, and the two second data conversion modules 4 are respectively connected to the CameraLink output interface 5. In the embodiment, two symmetrical data processing links are formed by the two first data conversion modules 2, the two second data conversion modules 4, the two statistical modules 3-1 and the two stretching modules 3-2, so that the data processing quantity is larger, the processing speed is higher and the efficiency is higher.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (6)
1. A real-time digital image enhancement method is characterized in that,
acquiring a gray level image acquired by an industrial camera through a CameraLink input interface;
performing data format conversion on the gray level image by using a first data conversion module, and sending the converted image into an FPGA chip;
the FPGA chip carries out histogram statistics on the converted image and stores the statistical data in a DPRAM in the chip; the DPRAM comprises an A port data signal, a B port data signal, an A port writing signal, an A port address and a B port address; the FPGA chip comprises a statistic module for performing histogram statistics and a stretching module for performing histogram stretching operation, and the state conversion process of the statistic module in the histogram statistics process comprises the following steps:
(1) an idle state: initializing the address of the port A to-1, entering a DPRAM zero clearing state if the statistical request is effective in an idle state, and otherwise, maintaining the current state;
(2) DPRAM clear state: the A port writing signal is set to 1, and the data of each address of the A port is cleared; when the DPRAM is cleared, if the address of the A port of the DPRAM is the maximum gray value of the pixel, entering a state of waiting for the end of the current frame, and if not, maintaining the current state;
(3) waiting for the current frame to end: performing no related operation, and entering a histogram statistical state after the current frame is finished; when waiting for the end of the current frame, if the frame is invalid, entering a state of waiting for a new frame to come, otherwise, maintaining the current state;
(4) wait for new frame to come state: no relevant operation is carried out; when waiting for a new frame, if the frame is valid, entering a histogram statistical state, otherwise, maintaining the current state;
(5) histogram statistical state: counting all gray values corresponding to the A port address when the image data are effective; when histogram statistics is carried out, if a frame is valid, the current state is maintained, otherwise, a histogram reading initialization state is entered;
(6) histogram readout initialization state: initializing the address of the port B to-1, and directly entering a histogram reading state after initialization;
(7) histogram readout state: reading out the histogram through the ascending order of the B port addresses; when histogram sequential reading is carried out, when the B port address read out from the DPRAM is the maximum pixel gray value, the reading is finished and the DPRAM enters an idle state, otherwise, the current state is maintained;
after the FPGA chip completes histogram statistics, reading data from the DPRAM, performing histogram stretching operation on the read data, and sending enhanced image data obtained after the stretching operation to a second data conversion module;
the second data conversion module performs data format conversion on the enhanced image data and sends the converted image data to a CameraLink output interface;
the CameraLink output interface outputs the enhanced digital image.
2. The method for enhancing a real-time digital image according to claim 1, wherein the process of the histogram stretching operation by the stretching module comprises the following steps:
acquiring the minimum gray level and the maximum gray level of the gray image;
and stretching the minimum gray level and the maximum gray level to two ends of a horizontal axis of the histogram until the minimum gray level is equal to 0 and the maximum gray level is equal to 255, so that the histogram is uniformly distributed in the range of 0-255 gray level to obtain enhanced image data.
3. The real-time digital image enhancement method of claim 1 or 2,
the number of the first data conversion module, the number of the second data conversion module, the number of the statistic module and the number of the stretching module are two.
4. A real-time digital image enhancement system, comprising:
the camera Link input interface is used for acquiring a gray level image acquired by an industrial camera and sending the gray level image to the first data conversion module;
the first data conversion module is used for performing data format conversion on the gray level image and sending the converted image data into an FPGA chip;
the FPGA chip is used for carrying out histogram statistics on the converted image, storing statistical data in a DPRAM in the chip, reading out the data from the DPRAM after the histogram statistics is finished, carrying out histogram stretching operation on the read-out data, and sending enhanced image data obtained after the stretching operation into a second data conversion module; the DPRAM comprises an A port data signal, a B port data signal, an A port writing signal, an A port address and a B port address; the FPGA chip comprises a statistic module for performing histogram statistics and a stretching module for performing histogram stretching operation, and the state conversion process of the statistic module in the histogram statistics process comprises the following steps:
(1) an idle state: initializing the address of the port A to-1, entering a DPRAM zero clearing state if the statistical request is effective in an idle state, and otherwise, maintaining the current state;
(2) DPRAM clear state: the A port writing signal is set to 1, and the data of each address of the A port is cleared; when the DPRAM is cleared, if the address of the A port of the DPRAM is the maximum gray value of the pixel, entering a state of waiting for the end of the current frame, and if not, maintaining the current state;
(3) waiting for the current frame to end: performing no related operation, and entering a histogram statistical state after the current frame is finished; when waiting for the end of the current frame, if the frame is invalid, entering a state of waiting for a new frame to come, otherwise, maintaining the current state;
(4) wait for new frame to come state: no relevant operation is carried out; when waiting for a new frame, if the frame is valid, entering a histogram statistical state, otherwise, maintaining the current state;
(5) histogram statistical state: counting all gray values corresponding to the A port address when the image data are effective; when histogram statistics is carried out, if a frame is valid, the current state is maintained, otherwise, a histogram reading initialization state is entered;
(6) histogram readout initialization state: initializing the address of the port B to-1, and directly entering a histogram reading state after initialization;
(7) histogram readout state: reading out the histogram through the ascending order of the B port addresses; when histogram sequential reading is carried out, when the B port address read out from the DPRAM is the maximum pixel gray value, the reading is finished and the DPRAM enters an idle state, otherwise, the current state is maintained;
the second data conversion module is used for performing data format conversion on the enhanced image data and sending the converted image data to the CameraLink output interface;
and the CameraLink output interface is used for outputting the enhanced digital image.
5. The real-time digital image enhancement system of claim 4, wherein the stretching module comprises:
the acquisition submodule is used for acquiring the minimum gray level and the maximum gray level of the gray level image;
and the stretching submodule is used for stretching the minimum gray level and the maximum gray level to two ends of a horizontal axis of the histogram until the minimum gray level is equal to 0 and the maximum gray level is equal to 255, so that the histogram is uniformly distributed in the range of 0-255 gray level, and the enhanced image data is obtained.
6. The real-time digital image enhancement system of claim 4 or 5,
the number of the first data conversion module, the number of the second data conversion module, the number of the statistic module and the number of the stretching module are two.
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