CN106851085B - A kind of signal processing system of the variable spectral coverage multispectral camera based on area array CCD - Google Patents
A kind of signal processing system of the variable spectral coverage multispectral camera based on area array CCD Download PDFInfo
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- CN106851085B CN106851085B CN201611045929.1A CN201611045929A CN106851085B CN 106851085 B CN106851085 B CN 106851085B CN 201611045929 A CN201611045929 A CN 201611045929A CN 106851085 B CN106851085 B CN 106851085B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/60—Control of cameras or camera modules
- H04N23/66—Remote control of cameras or camera parts, e.g. by remote control devices
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/80—Camera processing pipelines; Components thereof
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
Abstract
The signal processing system of the invention discloses a kind of variable spectral coverage multispectral camera based on area array CCD, including variable spectral coverage sequence controller, driving circuit, band come down in torrents the frame transfer area array CCD of charge function, analog to digital conversion circuit and video processor.Variable spectral coverage sequence controller generates the clock signal for driving area array CCD to work according to specified spectral coverage；Clock signal is converted into the driving signal of respective magnitudes by driving circuit；Band come down in torrents charge function frame transfer area array CCD under the action of driving signal output spectra segment information；The CCD analog signal exported is converted to digital signal by analog to digital conversion circuit；Video processor receives data image signal, and handles according to input parameter request image information.Compared with the signal processing system of the multi-thread battle array multispectral camera of tradition, the present invention has the characteristics that more spectral coverage quantity, spectral coverage spectral region real-time, tunable, spectral coverage width adjustment precision are high.
Description
Technical field
The signal processing system of the present invention relates to a kind of variable spectral coverage multispectral camera based on area array CCD, can be used as
The video signal processing system of multispectral camera uses, and belongs to the technology neck of space flight or the design of aerial remote sensing camera video electronics
Domain.
Background technique
The multispectral camera of the existing country generally selects line array CCD as detector.For realize camera multispectral imaging,
It needs using multi-disc uniline line array CCD, a spectral coverage is imaged in every CCD or CCD manufacturer is by multi-disc uniline linear array
CCD is encapsulated in a piece of CCD, to realize the multispectral imaging to target.Use line array CCD as the multispectral phase of detector
Machine is limited by device technology, can only detect to several spectral coverages of target, cannot achieve tens even several hundred a spectral coverages
It obtains.Meanwhile the spectral region of several spectral coverages is fixed, once it is determined that, it cannot achieve the change of in-orbit spectral coverage width.
Summary of the invention
Technology of the invention solves the problems, such as: having overcome the deficiencies of the prior art and provide a kind of variable based on area array CCD
The signal processing system of spectral coverage multispectral camera, realizes the growth of 1 to 2 orders of magnitude of spectral coverage number, while realizing each
The accurate real-time adjustment of spectral coverage spectral region.
The technical solution of the invention is as follows: a kind of signal processing of the variable spectral coverage multispectral camera based on area array CCD
System, comprising: variable spectral coverage sequence controller, driving circuit, band come down in torrents area array CCD, analog to digital conversion circuit, the letter of charge function
Number processor；
Variable spectral coverage sequence controller, clock signal needed for generating driving area array CCD work, including vertical transfer timing
Signal and horizontal transfer clock signal, are supplied to driving circuit；The vertical transfer timing signal and horizontal transfer clock signal
For LVCMOS level standard signal；
The LVCMOS level standard signal that variable spectral coverage sequence controller generates is converted to CCD high voltage by driving circuit
Driving signal send to band the frame transfer area array CCD for charge function of coming down in torrents；
Band comes down in torrents the frame transfer area array CCD of charge function, in the effect for the CCD high voltage drive signal that driving circuit provides
Under, analog signal of the output with specified spectral coverage information is supplied to analog to digital conversion circuit；
Analog to digital conversion circuit, by band come down in torrents charge function the transmission of frame transfer area array CCD come with specified spectral coverage information
Analog signal carry out analog-to-digital conversion generate data image signal, be transferred to signal processor；
Signal processor receives the data image signal from analog to digital conversion circuit, output format logarithm as requested
Word picture signal is arranged and is exported.
The variable spectral coverage sequence controller is made of vertical transfer timing module and horizontal transfer tfi module；Vertically
Transfer timing module generates vertical transfer timing signal, and horizontal transfer tfi module generates horizontal transfer clock signal.
Vertical transfer timing module in variable spectral coverage sequence controller includes: pulse counter 1, pulse counter 2, arteries and veins
Rush counter 3, pulse counter 4, comparator 1, comparator 2, comparator 3, comparator 4, selector 1, selector 2, selector
3, RAM1, d type flip flop 1, d type flip flop 2, d type flip flop 3, d type flip flop 4, d type flip flop 5, d type flip flop 6, d type flip flop 7, phase inverter
1, phase inverter 2, phase inverter 3 and door 1 and door 2 and door 3 and door 4 and door 5 or door 1 and/or door 2；
High active homing end R, the height of pulse counter 2 of externally input frame signal connection pulse counter 1 are effectively multiple
The reset terminal R of position end R, the reset terminal R of d type flip flop 1, the reset terminal R of d type flip flop 2 and d type flip flop 6；Externally input vertical turn
Move the connection of pulse periodic signal and an input terminal of door 1, with an input terminal of door 2, with an input terminal of door 3, with
Door 5 an input terminal, the enable end EN of pulse counter 4, the enable end EN of d type flip flop 1, d type flip flop 2 enable end EN, D
The enable end EN of the enable end EN of trigger 4, d type flip flop 6；The clock of externally input local clock connection pulse counter 1
Hold clock end C1, the D triggering of C1, the clock end C1 of pulse counter 2, the clock end C1 of pulse counter 3, pulse counter 4
Clock end C1, the D triggering of the clock end C1 of device 1, the clock end C1 of d type flip flop 2, the clock end C1 of d type flip flop 3, d type flip flop 4
The clock end C1 of device 5, the clock end C1 of d type flip flop 6, d type flip flop 7 clock end C1；Externally input vertical transfer continuities week
Phase signal connects the input terminal D0 of selector 1 and the input terminal D0 of selector 2, and the input terminal D1 connection of selector 1 is preset
Fixed logic level, the preset fixed logic level of input terminal D1 connection of selector 2；
The output end of enable end the EN connection and door 1 of pulse counter 1 connect phase inverter 1 with another input terminal of door 1
Output end, the input terminal A of the output end connection comparator 1 of pulse counter, the input terminal B connection of comparator 1 presets
Band come down in torrents charge function frame transfer area array CCD line number m, the input terminal and D of the output end Y connection phase inverter 1 of comparator 1
The input terminal D of trigger 1, the input terminal D of the output end connection d type flip flop 2 of d type flip flop 1, the output end of d type flip flop 2 connect choosing
Select the address end A0 of device 1, the address end A0 of selector 2, second input terminal with door 2；
The output end of the enable end connection and door 3 of pulse counter 2, connect defeated with door 4 with second input terminal of door 3
Outlet, the address input end of the output end connection RAM1 of pulse counter 2；
The output end of the enable end connection and door 2 of pulse counter 3, connect phase inverter 2 with the third input terminal of door 2
The output end of output end, the high active homing end R connection of pulse counter 3 or the output end of door 2, pulse counter 3 connects ratio
Output end compared with the input terminal A of device 3, the output end of the input terminal B connection RAM1 of comparator 3, comparator 3 connects phase inverter 2
The input terminal D of input terminal and d type flip flop 4, the output end connection of d type flip flop 4 or the input terminal and pulse counter of door 1
Low active homing end R；
The output end of the input terminal A connection RAM1 of comparator 2, the preset ending mark of the input terminal B connection of comparator 2
The output end connection of second input terminal or door 1 of character learning symbol, the output connection of comparator 2 or an input of door 2 or door 1
The output end of second input terminal connection and door 4 of the address end A1 or door 2 of selector 2；
The output end of the input terminal A connection pulse counter 4 of comparator 4, the input terminal B connection selector 3 of comparator 4
Output end, the input terminal D of the output end Y connection d type flip flop 6 of comparator 4 and an input terminal with door 4, d type flip flop 6 it is defeated
Counter another input terminal being connected back to door 4 of outlet；
The output end of the input terminal D connection phase inverter 3 of d type flip flop 7, the input terminal connection d type flip flop 7 of phase inverter 3
Output end, the output end of enable end the EN connection and door 5 of d type flip flop are connect and the output of door 4 with second input terminal of door 5
End；The output end of the address end A0 connection d type flip flop 7 of selector 3, the preset fixation of input terminal D0 connection of selector 3
Value N1, the preset fixed value N2 of input terminal D1 connection of selector 3；
The output of the input terminal D connection selector 1 of d type flip flop 3, the output end of d type flip flop 3 are vertical transfer timing letter
The vertical transfer timing signal of exposure region in number；The output of the input terminal D connection selector 2 of d type flip flop 5, d type flip flop 5 it is defeated
Outlet is the vertical transfer timing signal in memory block in vertical transfer timing signal.
The pulse counter 1, pulse counter 2, pulse counter 3, pulse counter 4 are the same of edging trigger
Walk decade counter；The trigger 1, trigger 2, trigger 3, trigger 4, trigger 5, trigger 6, trigger 7
Initialization value be logical zero；When externally input frame signal is logic 1, pulse count device 1 carries out reset operation, resets
Pulse counter 1 is in vertically transfer pulse periodic signal, i.e., vertical to turn on the basis of externally input local clock after the completion
Shifting pulse periodic signal is that high level is believing with the period of vertical transfer timing signal same frequency for a local clock cycles
Number, make carried out under can control plus 1 count, while comparator 1 by the count value of pulse counter 1 and preset face battle array
The line number m of CCD is compared, and when the count value of pulse counter 1 is less than m, comparator 1 exports logical zero, by d type flip flop 1
With the address end A0 for being transferred to selector 1 after d type flip flop 2, the gating of control selections device 1 exports vertical transfer continuities periodic signal,
I.e. with vertical transfer timing signal with the periodic signal of duty ratio, output is to d type flip flop 3, and d type flip flop 3 is in local clock frequently
Under the action of, as exposure region vertical transfer timing signal output, while the output of comparator 1 after phase inverter 1 by logic 1
The input terminal with door 1 is assigned, continues to count in the enabled lower pulse counter 1 with door 1；When the count value etc. of pulse counter 1
When the line number m of preset area array CCD, comparator 1 exports logic 1, is transferred to after d type flip flop 1 and d type flip flop 2
The address end A0 of selector 1, control selections device 1 export the silent of preset vertical transfer timing signal in the gating of comparator 1
Recognize logic level, by d type flip flop 3, as the vertical transfer timing signal output of exposure region, while the output of comparator 1 is passed through
Logical zero is assigned to the input terminal with door 1 after phase inverter, exports logical zero with door at this time, and pulse counter 1 stops counting, comparator
1, the output of d type flip flop 1 and d type flip flop 2 remains logic 1, and selector 1 gates D1 input terminal always, and d type flip flop 3 is always
The default logic level for exporting vertical transfer signal is maintained to the arrival of next external input frame signal；
Address pointer of the output of pulse counter 2 as RAM1, RAM1 successively stores outer from small to large according to address
The spectral coverage 1 of portion's input originates line number, spectral coverage 1 includes line number, spectral coverage 2 originates line number and spectral coverage 1 originates line number and spectral coverage 1 includes row
The difference of the sum of number, spectral coverage 2 include line number, and so on, until spectral coverage x starting line number and spectral coverage x-1 starting line number and spectrum
Difference of the section x-1 comprising the sum of line number, spectral coverage x include line number, the remaining line number of area array CCD, preset ending identifier word
Symbol, numerically not equal to any value possible inside RAM1；2 initial value of pulse counter is that the initial value of 0, RAM1 output is spectrum
Section 1 originates line number, and whether the output that comparator 2 compares RAM1 is equal to preset ending mark character, due to signal system
Spectral coverage number is at least 1, therefore comparator 2 exports logical zero level；Pulse counter 3 comparator 1 output be logic 1 after, with
On the basis of local clock, vertically transfer pulse periodic signal make can control under carry out plus 1 count, while comparator 3 will
Pulse counter 3 is compared with the numerical value in the address 0 of RAM1, and spectral coverage 1 originates line number, when the output valve of pulse counter 3
Less than internal RAM 1 output valve when, comparator 3 export logical zero, after level-one d type flip flop 4 and/or door 1, selector 2 gate
Vertical transfer continuities periodic signal is exported, the output of selector 2 is after level-one d type flip flop 5, when vertically shifting as memory block
Sequential signal output；After pulse counter 3 count down to the numerical value of 0 address of RAM1, spectral coverage 1 originates line number, and the output of comparator 3 is patrolled
1 is collected, by phase inverter 2 and with after door 2, no longer enabling pulse counter 3, pulse counter keep current count value；Selector 2
Gating exports the default logic level of vertical transfer signal at this time, when vertically shifting after level-one d type flip flop 5 as memory block
Sequential signal output；
Comparator 3 remains logic 1, and pulse counter 4 is in system clock and vertical transfer under the effect of frequency periodic signal
It carries out plus 1 counts, selector 3 exports preset fixed value 1 under the control of d type flip flop 7, and comparator 4 is by step-by-step counting
Device 4 and fixed value 1 are compared, and when the value of pulse counter 4 is less than 1, pulse counter 4 continues plus 1 counts；Work as step-by-step counting
The value of device 4 is equal to 1, and comparator 4 exports logic 1, and the output of comparator 4 carries out after d type flip flop 6 with the output of comparator 4
With operation, obtain a width be a vertical transfer signal period high level pulse, the pulse and it is externally input vertically
By acting on d type flip flop 7 with enable signal is used as after door 5, selector exports transfer pulse periodic signal in d type flip flop 7
Control under, gating n output, the occupied vertical migration period number of n, that is, horizontal transfer a line pixel, at the same the high impulse use
Reset its count value in reset pulse counter 3, and by carrying out adding 1 operation with enabling pulse counter 2 after door 3, it is internal
The output of RAM1 is the content of address 1, and spectral coverage 1 includes line number, and comparator 3 compares the output of pulse counter 3 and internal RAM 1
Value, comparator 3 export logical zero, and pulse counter 4, which is in, resets cleared condition；
After vertical transfer timing module has carried out the vertical transfer timing signal output of x spectral coverage as procedure described above, arteries and veins
Rush counter 2 count down to be stored with ending mark character the address RAM1, comparator 2 compare RAM1 output with it is preset
Ending mark character it is whether equal, when equal, comparator 2 export logic 1, by or door 2 after reset pulse counter 3, together
When selector 2 gate vertical transfer signal default logic state, after d type flip flop 2 as the vertical transfer signal in memory block it is defeated
Out.
Horizontal transfer tfi module in variable spectral coverage sequence controller includes pulse counter 5, comparator 5, selector
3, with door 6 and with door 7；One input terminal of externally input continuous cycles horizontal transfer R signal connection and door 6, external input
An input terminal of the horizontal transfer enable signal connection with second input terminal of door 6 and with door 7, the output end with door 6 is
For horizontal transfer R clock signal；Second input terminal of externally input continuous cycles RST signal connection and door 7, with door 7
The enable end EN of output end connection pulse counter 5；Externally input 4 frequency doubling clock of pixel frequency connection pulse counter 5
Clock end, the input terminal A of the output end connection comparator 5 of pulse counter, the input terminal B connection of comparator 5 are externally input
Horizontal pixel merges number；The output end of the address end A0 connection comparator 5 of selector 3, the input terminal D0 connection water of selector 3
Flat turn moves the default logic level of RST clock signal, the externally input continuous cycles RST letter of the input terminal D1 connection of selector 3
Number.
The pulse counter 5 is on the basis of externally input 4 frequency doubling clock of pixel frequency, when horizontal transfer signal is enabled
It is carried out for logic 1 and when continuous cycles RST signal is logic 1 plus 1 counts, while comparator 5 compares the output of pulse counter 5
Value and horizontal pixel merge number, and when the value of pulse counter 5, which is less than horizontal pixel, merges number, comparator 5 exports logic
0, the gating default RST logic level of selector 3 is exported as horizontal transfer RST clock signal；When the value of pulse counter 5 is equal to
When horizontal pixel merges number, comparator 5 exports logic 1, and selector 3 gates continuous cycles RST signal as horizontal transfer RST
Clock signal output；
Horizontal transfer enable signal and continuous cycles horizontal transfer R signal carry out and are used as horizontal transfer R timing after operation
Signal output.
The driving circuit is by first resistor R1, second resistance R2,3rd resistor R3, the 4th resistance R4, first capacitor
C1, the second capacitor C2, first diode D1 and driver (201) composition；Input signal connects first resistor R1, second resistance R2
With the IN input terminal of driving 201；The other end of first resistor R1 connects driving signal amplitude level Vamp, second resistance it is another
With being connected to circuit；The VH power supply of driver (201) is connected to Vamp, and VL power supply is with being connected to circuit；Driver (201)
OUT output end connects 3rd resistor R3, and the other end of R3 connects one end and the capacitance C2 of waveform first capacitor C1 simultaneously
One end, with being connected to circuit, the other end of C2 is connected to first diode D1, the 4th resistance R4 to the other end of first capacitor C1
And output signal；The another of D1 is connected to clamping level Vclp, and the another of R4 is connected to initialize level Vinit.
The first resistor R1, second resistance R2 value range are as follows:3rd resistor R3 value needs
The impedance of driving signal cabling on match circuit plate；4th resistance R4 value 100K Ω；First capacitor C1 and 3rd resistor R3 group
At low-pass filtering, increase the rise time of driving signal；Capacitance C2 value 1uF.
The band come down in torrents charge function area array CCD include exposure region and memory block, memory block does not expose and pixel knot
Structure is identical as exposure region, can be by exposure region signal charge fast transfer to memory block by continuous vertical transfer；Band comes down in torrents electricity
The area array CCD of lotus function has the function of rapid dump horizontal register signal charge, can be by nontarget area signal charge
Quickly remove.
The A/D chip that the analog to digital conversion circuit includes has the function of correlated-double-sampling, and has change pixel frequency in real time
The ability directly to work according to new parameter after rate without configuration；The input parameter includes: the spectrum of spectral coverage number, single spectral coverage
Range.
The invention has the following advantages over the prior art:
(1) present invention uses detector of the area array CCD as multispectral camera, and comparing line array CCD can obtain more more
Fine spectral coverage information；
(2) present invention using programmable logic device generate area array CCD driving signal, can real-time response external command, lead to
Cross the in-orbit accurate adjustment that change CCD driving signal realizes multispectral camera spectral coverage number and spectral coverage range；
(3) synthesis of spectral coverage information of the present invention is realized by the merging of ccd signal charge, is compared Digital image synthesis, is subtracted
The small reading noise of CCD, improves the signal-to-noise ratio of multispectral camera；
(4) present invention can remove rapidly non-interested spectrum letter by the charge function of coming down in torrents of control area array CCD
Breath, improves the frame frequency of the multispectral camera based on area array CCD；
(5) present invention can respective external instruction, by change horizontal drive RST signal period realize it is adjacent in a line
The merging of pixel signal charge is the merging after digital signal compared to individual signals charge quantization, improves multispectral phase
The signal-to-noise ratio of machine；
(6) present invention realizes variable spectral coverage timing control using a small amount of combinational logic gate circuit and sequential logic gate circuit
Device processed further saves device resource by being multiplexed these gate circuits；
(7) drive signal circuit of the invention has used single level power supply and signal clamp technology, compared to basic pair
Level powered drive circuit reduces the power type of driving circuit, reduces the circuit scale of signal processing system.
Detailed description of the invention
Fig. 1 is signal processing system structural block diagram of the present invention；
Fig. 2 is the spectral coverage schematic diagram that the present invention generates multiple adjustable spectral regions；
Fig. 3 is the variable vertical transfer timing modular structure block diagram of spectral coverage sequence controller of the present invention；
Fig. 4 is the variable vertical transfer timing module timing diagram of spectral coverage sequence controller of the present invention；
Fig. 5 is that the vertical transfer timing module timing diagram of the variable spectral coverage sequence controller of the present invention illustrates；
Fig. 6 is the variable spectral coverage sequence controller horizontal transfer tfi module structural block diagram of the present invention；
Fig. 7 is the variable spectral coverage sequence controller horizontal transfer tfi module timing diagram of the present invention；
Fig. 8 is present invention driver circuit schematic diagram.
Specific embodiment
Basic ideas of the invention are as follows: at the signal for proposing a kind of variable spectral coverage multispectral camera based on area array CCD
Reason system, including variable spectral coverage sequence controller, driving circuit, band come down in torrents the frame transfer area array CCD of charge function, analog-to-digital conversion
Circuit and video processor.Variable spectral coverage sequence controller generates the timing for driving area array CCD to work according to specified spectral coverage
Signal；Clock signal is converted into the driving signal of respective magnitudes by driving circuit；Band comes down in torrents the frame transfer area array CCD of charge function
Output spectra segment information under the action of driving signal；The CCD analog signal exported is converted to digital signal by analog to digital conversion circuit；
Video processor receives data image signal, and handles according to input parameter request image information.With the multi-thread battle array of tradition
The signal processing system of multispectral camera is compared, and the present invention has more spectral coverage quantity, spectral coverage spectral region real-time, tunable, spectral coverage wide
Spend the features such as Adjustment precision is high.
Structure composition and working principle of the invention are further illustrated with reference to the accompanying drawing.
As shown in Figure 1, a kind of signal processing system of variable spectral coverage multispectral camera based on area array CCD proposed by the present invention
System, including variable spectral coverage sequence controller, driving circuit, band come down in torrents the area array CCD of charge function, analog to digital conversion circuit and video
Processor；Variable spectral coverage sequence controller generates the clock signal for driving area array CCD to work according to specified spectral coverage；Driving electricity
Clock signal is converted into the driving signal of respective magnitudes by road；Band come down in torrents charge function area array CCD driving signal effect
Lower output spectra segment information；The CCD analog signal exported is converted to digital signal by analog to digital conversion circuit；Video processor receives number
Word picture signal, and image information is handled according to input parameter request；
A kind of signal processing system of the variable spectral coverage multispectral camera based on area array CCD of the present invention includes: variable spectral coverage
Sequence controller, driving circuit, band come down in torrents area array CCD, analog to digital conversion circuit, the signal processor of charge function；
Variable spectral coverage sequence controller, using programmable logic device, when for generating needed for driving area array CCD work
Sequential signal；Merge number according to the spectral coverage number of input, the width range of single spectral coverage, horizontal pixel, changes internal counter
With comparator and judgment criteria, corresponding vertical transfer timing signal and horizontal transfer clock signal are exported, driving electricity is supplied to
Road, and then drive area array CCD according to specified spectral coverage number and spectral coverage width range output spectra segment information；
Driving circuit realizes the LVCMOS level standard signal for generating variable spectral coverage sequence controller using driving chip
Be converted to CCD high voltage drive signal；Driving circuit includes vertical transfer drive module and horizontal transfer drive module；It is vertical to turn
It moves drive module and vertically shifts driving signal for generating Microsecond grade, horizontal transfer drive module turns for generating nanosecond level
Move driving signal；
The come down in torrents area array CCD of charge function of band is joined under the action of the driving signal that driving circuit provides according to input
Number, analog signal of the output with specified spectral coverage information, is supplied to analog to digital conversion circuit；
Analog to digital conversion circuit, the analog signal that area array CCD transmission is come carry out analog-to-digital conversion and generate data image signal, pass
It is defeated by signal processor；
Signal processor is realized using programmable logic device, receives the digital image information from analog to digital conversion circuit,
The parameters such as the Spectral beam combining according to input integrate digital spectral information.
As shown in Fig. 2, the present invention uses area array CCD (effective pixel m row n column) as detector, every a line of area array CCD
A corresponding band, the band represent the signal processing system of the variable spectral coverage multispectral camera based on area array CCD
Spectral coverage range Adjustment precision；By the way that several rows of area array CCD are merged the merging realized to target special spectrum band, formed
One spectral coverage；The acquisition for the spectral coverage information that the present invention supports multiple spectral coverages, each spectral coverage spectral region independently adjustable；
As shown in Figure 3 and Figure 4, the pulse counter 1, pulse counter 2, pulse counter 3, pulse counter 4
It is the synchronization decade counter of edging trigger；The trigger 1, trigger 2, trigger 3, trigger 4, trigger 5,
Trigger 6, trigger 7 initialization value be logical zero；When (high level is a local clock week to externally input frame signal
Phase) pulse count device 1 carries out reset operation when being logic 1, after the completion of reset pulse counter 1 with it is externally input local when
On the basis of clock, vertically transfer pulse periodic signal (vertical transfer pulse periodic signal is high level be a local when
The clock period with the periodic signal of vertical transfer timing signal same frequency) make to carry out under can control plus 1 counts, while comparator
1 is compared the line number m of the count value of pulse counter 1 and preset area array CCD, when the counting of pulse counter 1
When value is less than m, comparator 1 exports logical zero, and the address end A0 of selector 1 is transferred to after d type flip flop 1 and d type flip flop 2, controls
The gating of selector 1 processed exports vertical transfer continuities periodic signal (to be believed with frequency with the period of duty ratio with vertical transfer timing signal
Number) to d type flip flop 3, d type flip flop 3 is exported under the action of local clock as the vertical transfer timing signal of exposure region for output,
The output of comparator 1 assigns logic 1 to the input terminal with door 1 after phase inverter 1 simultaneously, in the enabled lower pulsimeter with door 1
Number device 1 continues to count；When the count value of pulse counter 1 is equal to the line number m of preset area array CCD, comparator 1 is exported
Logic 1, is transferred to the address end A0 of selector 1 after d type flip flop 1 and d type flip flop 2, and control selections device 1 is selected in comparator 1
The default logic level of the logical preset vertical transfer timing signal of output vertically turns by d type flip flop 3 as exposure region
Move clock signal output, at the same the output of comparator 1 after phase inverter by logical zero assign with the input terminal of door 1, at this time with door
Logical zero is exported, pulse counter 1 stops counting, and the output of comparator 1, d type flip flop 1 and d type flip flop 2 remains logic 1,
Selector 1 gates D1 input terminal always, and d type flip flop 3 exports the default logic level of vertical transfer signal always, is maintained to
The arrival of next external input frame signal；
Address pointer of the output of pulse counter 2 as RAM1, RAM1 successively stores outer from small to large according to address
The spectral coverage 1 of portion's input originates line number, spectral coverage 1 includes line number, spectral coverage 2 originates line number and spectral coverage 1 originates line number and spectral coverage 1 includes row
The difference of the sum of number, spectral coverage 2 include line number, and so on, until spectral coverage x starting line number and spectral coverage x-1 starting line number and spectrum
Difference of the section x-1 comprising the sum of line number, spectral coverage x include line number, the remaining line number of area array CCD, preset ending identifier word
Symbol (numerically not equal to any value possible inside RAM1)；2 initial value of pulse counter is that the initial value of 0, RAM1 output is
Spectral coverage 1 originates line number, and whether the output that comparator 2 compares RAM1 is equal to preset ending mark character, due to signal system
System spectral coverage number is at least 1, therefore comparator 2 exports logical zero level；Pulse counter 3 comparator 1 output be logic 1 after,
On the basis of local clock, vertically transfer pulse periodic signal make can control under carry out plus 1 counts, while comparator 3
Numerical value (spectral coverage 1 originates line number) in the address 0 of pulse counter 3 and RAM1 is compared, when the output of pulse counter 3
When value is less than the output valve of internal RAM 1, comparator 3 exports logical zero, and after level-one d type flip flop 4 and/or door 1, selector 2 is selected
Logical to export vertical transfer continuities periodic signal, the output of selector 2 is vertically shifted after level-one d type flip flop 5, as memory block
Clock signal output；After pulse counter 3 count down to numerical value (spectral coverage 1 originates line number) of 0 address of RAM1, comparator 3 is defeated
Logic 1 out, by phase inverter 2 and with after door 2, no longer enabling pulse counter 3, pulse counter keep current count value；Choosing
It selects device 2 and gates the default logic level for exporting vertical transfer signal at this time, it is vertical as memory block after level-one d type flip flop 5
The output of transfer timing signal.
Comparator 3 remains logic 1, and pulse counter 4 is in system clock and vertical transfer under the effect of frequency periodic signal
It carries out plus 1 counts, selector 3 exports preset fixed value 1 under the control of d type flip flop 7, and comparator 4 is by step-by-step counting
Device 4 and fixed value 1 are compared, and when the value of pulse counter 4 is less than 1, pulse counter 4 continues plus 1 counts；Work as step-by-step counting
The value of device 4 is equal to 1, and comparator 4 exports logic 1, and the output of comparator 4 carries out after d type flip flop 6 with the output of comparator 4
With operation, obtain a width be a vertical transfer signal period high level pulse, the pulse and it is externally input vertically
By acting on d type flip flop 7 with enable signal is used as after door 5, selector exports transfer pulse periodic signal in d type flip flop 7
Control under, gating n (the occupied vertical migration period number of horizontal transfer a line pixel) output, while the high impulse is used for
Reset pulse counter 3 resets its count value, and by carrying out adding 1 operation with enabling pulse counter 2 after door 3, internal
The output of RAM1 is the content (spectral coverage 1 includes line number) of address 1, and comparator 3 compares the output of pulse counter 3 and internal RAM 1
Value, comparator 3 export logical zero, and pulse counter 4, which is in, resets cleared condition；
After vertical transfer timing module has carried out the vertical transfer timing signal output of x spectral coverage as procedure described above, arteries and veins
Rush counter 2 count down to be stored with ending mark character the address RAM1, comparator 2 compare RAM1 output with it is preset
Ending mark character it is whether equal, when equal, comparator 2 export logic 1, by or door 2 after reset pulse counter 3, together
When selector 2 gate vertical transfer signal default logic state, after d type flip flop 2 as the vertical transfer signal in memory block it is defeated
Out；
Such as: the frame transfer area array CCD of charge function if the band for having 20 rows 10 to arrange comes down in torrents, corresponding 20 bands of 20 rows.
It is required that 2 spectral coverages of output, spectral coverage 1 includes band 6 to band 9, and spectral coverage 2 includes band 12 to band 18.Then RAM1
Numerical value is 4 in middle address 0, and numerical value is 3 in address 1, and numerical value is 1 in address 2, and numerical value is 6 in address 3, and numerical value is 1 in address 4,
Numerical value is preset as 10 in address 5, while ending up and identifying character and be set as 10.
As shown in figure 5, when frame signal (high level is a local clock cycles) is logic 1, pulse counter 1, pulse
Counter 2 is reset to 0, and d type flip flop 1, d type flip flop 2 and d type flip flop 7 are reset to 0.After frame signal becomes logical zero, step-by-step counting
The reset terminal R of device 1 fails, and pulse counter 1 starts to carry out on the basis of local clock and vertical transfer pulse periodic signal
Add 1 counting.Before pulse counter 1 count down to 14, comparator 1 exports always logical zero, triggers by level-one trigger D
After device 1, selector 1 gates vertical transfer continuities periodic signal (and vertical transfer timing signal is with the same duty ratio of frequency) output, warp
Output is the vertical transfer timing signal of exposure region after crossing level-one d type flip flop 3；Simultaneous selection device 2 gates the vertical transfer continuities in the end D0
Periodic signal output, output is the vertical transfer timing signal in memory block after level-one d type flip flop 5.When pulse counter 1 counts
When to 14, comparator 1 exports logic 1, by phase inverter 1 and with after door 1, not enabling pulse counter 1, pulse counter 1
Output remains 14, and for the logic 1 that comparator 1 exports after level-one d type flip flop 1, selector 1 gates vertical transfer timing signal
The output of 0 level of default logic, and it is always maintained at 0 level, until next frame signal arrives；Selector 2 gates vertical transfer
The output of continuous cycles signal, output is the vertical transfer timing signal in memory block after level-one d type flip flop 5.
When the output of d type flip flop 2 is logic 1, pulse counter 3 starts in local clock and vertical transfer pulse period
It is carried out under signal function plus 1 counts, the output of pulse counter 2 at this time is 0, is directed toward the address 0 of RAM1, and the output of RAM1 is number
Value 4；The output of pulse counter 3 and 4 are compared by comparator 3, and when the former is less than 4, the output of comparator 30 is touched by D
After sending out device 4 and/or door 1, selector 2 gates vertical transfer continuities periodic signal as output, and output is to deposit after d type flip flop 5
The vertical transfer timing signal of storage area.After pulse counter 3 count down to 4, the output of comparator 31, by d type flip flop 4 and/or door 1
Afterwards, selector 2 gates the 0 level output of vertical transfer default, after d type flip flop 5, exports as the vertical transfer timing in 0 memory block
Signal thereby realizes the coming down in torrents to 5 signal charge of band of band 1.The 1 of the output of d type flip flop 4 at this time no longer resets arteries and veins
Counter 4 is rushed, pulse counter 4 starts to carry out under local clock and vertical transfer pulse periodic signal effect plus 1 counts；
D type flip flop 7 is currently 0, and selector 3 gates preset numerical value 1 and exports；When the value of pulse counter 4 is less than 1, compare
Device 4 export logical zero, when the value of pulse counter 4 be equal to 1 when, comparator 4 export logic 1, by d type flip flop 6 and with after door 4,
The high level signal for generating a vertical transfer signal period, under high level signal effect, the overturning output of d type flip flop 7 is patrolled
1 is collected, selector 3 gates fixed value n (n vertical transfer timing signal periods, be greater than a line pixel horizontal transfer required time)；
Meanwhile the high level reset pulse counter 3 exported with door 4, pulse counter 3 restarts plus 1 counts；It is exported with door 4
Enabling pulse counter 2 carries out high level simultaneously plus 1 counts, the numerical value 3 in RAM1 output address 1.The value of pulse counter 3 and
Numerical value 3 is compared, and when the value of pulse counter 3 is less than 3, comparator 3 exports logical zero, by d type flip flop 4 and/or door 1
Afterwards, the end D0 of selector is selected, the vertical transfer timing signal in memory block exports vertical transfer continuities periodic signal；Work as step-by-step counting
When the value of device 3 is equal to 3, comparator 3 exports logic 1 and selects the end D1 of selector, memory block after d type flip flop 4 and/or door 1
0 level of vertical transfer timing signal output default.Pulse counter 4 restarts plus 1 counts, and comparator 4 compares pulsimeter
The value of number device 4 and fixed value n, when the former is less than n, comparator 4 exports logical zero；When the former is equal to n, comparator output is patrolled
Volume 1, in d type flip flop 6 and under the action of with door 4, a high level is generated, the high level reset pulse counter 3, and enabled arteries and veins
Rushing the value that counter 2 add 1 operation, while overturning d type flip flop 7 is 0.The conjunction of band 6 to band 9 is thus carried out
And.
And so on, then band 10 may be implemented to the coming down in torrents of band 11, the synthesis of band 12 to band 18
With the coming down in torrents to band 20 of band 19.Specific timing diagram is as shown in Figure 5.
As shown in Figure 6 and Figure 7, the horizontal transfer tfi module in adjustable spectral coverage sequence controller is by pulse counter 5, ratio
It is formed compared with device 5, selector 3 and 2 and logic gate；Pulse counter 5 is on the basis of 4 frequency doubling clock of pixel frequency, when level turns
Shifting signal enables to carry out for logic 1 and when continuous cycles RST signal is logic 1 plus 1 counts, while comparator 5 compares pulsimeter
The output valve of number device 5 and horizontal pixel merge number, when the value of pulse counter 5, which is less than horizontal pixel, merges number, compare
Device 5 exports logical zero, and the gating default RST logic level of selector 3 is exported as horizontal transfer RST clock signal；Work as step-by-step counting
When the value of device 5 is equal to horizontal pixel merging number, comparator 5 exports logic 1, and selector 3 gates the conduct of continuous cycles RST signal
The output of horizontal transfer RST clock signal；
Horizontal transfer enable signal and continuous cycles horizontal transfer R signal carry out and are used as horizontal transfer R timing after operation
Signal output；
As shown in figure 8, the driving circuit is by first resistor R1, second resistance R2,3rd resistor R3, the 4th resistance
R4, first capacitor C1, the second capacitor C2, first switch diode D1 and driver (201) composition；The first electricity of input signal connection
Hinder the IN input terminal of R1, second resistance R2 and driving 201；The other end of first resistor R1 connects driving signal amplitude level
Vamp, second resistance it is another with being connected to circuit；The VH power supply of driver (201) is connected to Vamp, and VL power supply is connected to electricity
Lu Di；The OUT output end of driver (201) connects 3rd resistor R3, and the other end of R3 connects waveform first capacitor C1 simultaneously
One end and capacitance C2 one end, with being connected to circuit, the other end of C2 is connected to first to the other end of first capacitor C1
Diode D1, the 4th resistance R4 and output signal；The another of D1 is connected to clamping level Vclp, and the another of R4 is connected to initialization
Level Vinit；
First resistor R1, the requirement of second resistance R2 value range:Reduce the static function of driving circuit
Consumption；3rd resistor R3 value needs the impedance of driving signal cabling on match circuit plate；4th resistance R4 value is about 100K Ω；
First capacitor C1 and 3rd resistor R3 forms low-pass filtering, removes high-frequency noise, increases the rise time t of driving signalRise, by
In jump function RC low-pass filter response formula be uC(t)=v (1-e-t/T), wherein v is driving signal amplitude level Vamp, T
For circuit time constant RC, therefore rise time tRise=ln9 × RC, i.e., about tRise≈2.2RC；Capacitance C2 value is about
The value of 1uF, the more C2 can change the high pass cut off frequency of circuit；
The come down in torrents area array CCD of charge function of the band includes exposure region and memory block, memory block shading and pixel structure
It is identical as exposure region, it can be by exposure region signal charge fast transfer to memory block by continuous vertical transfer；Band comes down in torrents charge
The area array CCD of function has the function of rapid dump horizontal register signal charge, can be fast by nontarget area signal charge
Speed is removed；
The A/D chip that the analog to digital conversion circuit includes has the function of correlated-double-sampling, and has change pixel frequency in real time
The ability directly to work according to new parameter after rate without configuration；
Compared with the signal processing system of the multi-thread battle array multispectral camera of tradition, the present invention more, spectral coverage light with spectral coverage quantity
The features such as spectral limit real-time, tunable, high spectral coverage width adjustment precision.
The content that description in the present invention is not described in detail belongs to the well-known technique of those skilled in the art.
Claims (9)
1. a kind of signal processing system of the variable spectral coverage multispectral camera based on area array CCD, characterized by comprising: variable spectrum
Section sequence controller, driving circuit, band come down in torrents area array CCD, analog to digital conversion circuit, the signal processor of charge function；
Variable spectral coverage sequence controller, clock signal needed for generating driving area array CCD work, including vertical transfer timing signal
With horizontal transfer clock signal, it is supplied to driving circuit；The vertical transfer timing signal and horizontal transfer clock signal are
LVCMOS level standard signal；
The LVCMOS level standard signal that variable spectral coverage sequence controller generates is converted to CCD high voltage drive by driving circuit
Signal send to band the area array CCD for charge function of coming down in torrents；
The come down in torrents area array CCD of charge function of band exports band under the action of the CCD high voltage drive signal that driving circuit provides
There is the analog signal of specified spectral coverage information, is supplied to analog to digital conversion circuit；
Analog to digital conversion circuit comes down in torrents band the analog signal with specified spectral coverage information that the area array CCD transmission of charge function comes
It carries out analog-to-digital conversion and generates data image signal, be transferred to signal processor；
Signal processor receives the data image signal from analog to digital conversion circuit, and output format as requested is to digitized map
As signal is arranged and is exported；
The driving circuit is by first resistor R1, second resistance R2,3rd resistor R3, the 4th resistance R4, first capacitor C1,
Two capacitor C2, first diode D1 and driver (201) composition；Input signal connects first resistor R1, second resistance R2 and drive
Dynamic 201 IN input terminal；The other end of first resistor R1 connects driving signal amplitude level Vamp, another termination of second resistance
To circuit；The VH power supply of driver (201) is connected to Vamp, and VL power supply is with being connected to circuit；The OUT of driver (201) is defeated
Outlet connects 3rd resistor R3, the other end of R3 connect simultaneously waveform first capacitor C1 one end and capacitance C2 one
End, with being connected to circuit, the other end of C2 is connected to first diode D1, the 4th resistance R4 and defeated to the other end of first capacitor C1
Signal out；The another of D1 is connected to clamping level Vclp, and the another of R4 is connected to initialize level Vinit.
2. a kind of signal processing system of variable spectral coverage multispectral camera based on area array CCD according to claim 1,
Be characterized in that: the variable spectral coverage sequence controller is made of vertical transfer timing module and horizontal transfer tfi module；It hangs down
Straight transfer timing module generates vertical transfer timing signal, and horizontal transfer tfi module generates horizontal transfer clock signal.
3. a kind of signal processing system of variable spectral coverage multispectral camera based on area array CCD according to claim 2,
Be characterized in that: the vertical transfer timing module in variable spectral coverage sequence controller include: pulse counter 1, pulse counter 2,
Pulse counter 3, pulse counter 4, comparator 1, comparator 2, comparator 3, comparator 4, selector 1, selector 2, selection
Device 3, RAM1, d type flip flop 1, d type flip flop 2, d type flip flop 3, d type flip flop 4, d type flip flop 5, d type flip flop 6, d type flip flop 7, reverse phase
Device 1, phase inverter 2, phase inverter 3 and door 1 and door 2 and door 3 and door 4 and door 5 or door 1 and/or door 2；
Externally input frame signal connects the high active homing end of the high active homing end R of pulse counter 1, pulse counter 2
R, the reset terminal R of the reset terminal R of d type flip flop 1, the reset terminal R of d type flip flop 2 and d type flip flop 6；Externally input vertical transfer is single
Pulse-period signal connection and an input terminal and door 5 for an input terminal of door 1 and an input terminal of door 2 and door 3
Enable end EN, D triggering of one input terminal, the enable end EN of pulse counter 4, the enable end EN of d type flip flop 1, d type flip flop 2
The enable end EN of the enable end EN of device 4, d type flip flop 6；The clock end C1 of externally input local clock connection pulse counter 1,
The clock end C1 of pulse counter 2, the clock end C1 of pulse counter 3, the clock end C1 of pulse counter 4, d type flip flop 1
Clock end C1, the clock end C1 of d type flip flop 2, the clock end C1 of d type flip flop 3, the clock end C1 of d type flip flop 4, d type flip flop 5
Clock end C1, the clock end C1 of d type flip flop 6, d type flip flop 7 clock end C1；Externally input vertical transfer continuities periodic signal
Connect the input terminal D0 of selector 1 and the input terminal D0 of selector 2, the preset fixation of input terminal D1 connection of selector 1
Logic level, the preset fixed logic level of input terminal D1 connection of selector 2；
The output end of enable end the EN connection and door 1 of pulse counter 1 connect the defeated of phase inverter 1 with another input terminal of door 1
Outlet, the input terminal A of the output end connection comparator 1 of pulse counter, the preset band of input terminal B connection of comparator 1
The line number m of the area array CCD for charge function of coming down in torrents, the input terminal of the output end Y connection phase inverter 1 of comparator 1 and d type flip flop 1
Input terminal D, the input terminal D of the output end connection d type flip flop 2 of d type flip flop 1, the ground of the output end connection selector 1 of d type flip flop 2
Location end A0, the address end A0 of selector 2, second input terminal with door 2；
The output end of the enable end connection and door 3 of pulse counter 2, connect and the output of door 4 with second input terminal of door 3
End, the address input end of the output end connection RAM1 of pulse counter 2；
The output end of the enable end connection and door 2 of pulse counter 3, the output of phase inverter 2 is connect with the third input terminal of door 2
The output end of end, the high active homing end R connection of pulse counter 3 or the output end of door 2, pulse counter 3 connects comparator 3
Input terminal A, the output end of the input terminal B connection RAM1 of comparator 3, comparator 3 output end connection phase inverter 2 input terminal
With the input terminal D of d type flip flop 4, d type flip flop 4 output end connection or door 1 an input terminal and pulse counter it is low effectively
Reset terminal R；
The output end of the input terminal A connection RAM1 of comparator 2, the preset ending identifier word of input terminal B connection of comparator 2
Symbol, the output connection of comparator 2 or an input of door 2 or second input terminal of door 1 or the output end of door 1 connect selection
The output end of second input terminal connection and door 4 of the address end A1 or door 2 of device 2；
The output end of the input terminal A connection pulse counter 4 of comparator 4, the output of the input terminal B connection selector 3 of comparator 4
End, the input terminal D of the output end Y connection d type flip flop 6 of comparator 4 and an input terminal with door 4, the output end of d type flip flop 6
Counter another input terminal being connected back to door 4；
The output end of the input terminal D connection phase inverter 3 of d type flip flop 7, the output of the input terminal connection d type flip flop 7 of phase inverter 3
End, the output end of enable end the EN connection and door 5 of d type flip flop are connect and the output end of door 4 with second input terminal of door 5；Choosing
Select the output end of the address end A0 connection d type flip flop 7 of device 3, the input terminal preset fixed value N1 of D0 connection of selector 3,
The preset fixed value N2 of input terminal D1 connection of selector 3；
The output of the input terminal D connection selector 1 of d type flip flop 3, the output end of d type flip flop 3 is in vertical transfer timing signal
The vertical transfer timing signal of exposure region；The output of the input terminal D connection selector 2 of d type flip flop 5, the output end of d type flip flop 5
The vertical transfer timing signal in memory block in as vertical transfer timing signal.
4. a kind of signal processing system of variable spectral coverage multispectral camera based on area array CCD according to claim 3,
Be characterized in that: the pulse counter 1, pulse counter 2, pulse counter 3, pulse counter 4 are edging trigger
Synchronous decade counter；The trigger 1, trigger 2, trigger 3, trigger 4, trigger 5, trigger 6, trigger
7 initialization value is logical zero；When externally input frame signal is logic 1, pulse count device 1 carries out reset operation, multiple
Pulse counter 1 is on the basis of externally input local clock after the completion of position, in vertically transfer pulse periodic signal, i.e., vertically
Transfer pulse periodic signal be high level be a local clock cycles with the period of vertical transfer timing signal same frequency
Signal, make carried out under can control plus 1 count, while comparator 1 by the count value of pulse counter 1 and preset face battle array
The line number m of CCD is compared, and when the count value of pulse counter 1 is less than m, comparator 1 exports logical zero, by d type flip flop 1
With the address end A0 for being transferred to selector 1 after d type flip flop 2, the gating of control selections device 1 exports vertical transfer continuities periodic signal,
I.e. with vertical transfer timing signal with the periodic signal of duty ratio, output is to d type flip flop 3, and d type flip flop 3 is in local clock frequently
Under the action of, as exposure region vertical transfer timing signal output, while the output of comparator 1 after phase inverter 1 by logic 1
The input terminal with door 1 is assigned, continues to count in the enabled lower pulse counter 1 with door 1；When the count value etc. of pulse counter 1
When the line number m of preset area array CCD, comparator 1 exports logic 1, is transferred to after d type flip flop 1 and d type flip flop 2
The address end A0 of selector 1, control selections device 1 export the silent of preset vertical transfer timing signal in the gating of comparator 1
Recognize logic level, by d type flip flop 3, as the vertical transfer timing signal output of exposure region, while the output of comparator 1 is passed through
Logical zero is assigned to the input terminal with door 1 after phase inverter, exports logical zero with door at this time, and pulse counter 1 stops counting, comparator
1, the output of d type flip flop 1 and d type flip flop 2 remains logic 1, and selector 1 gates D1 input terminal always, and d type flip flop 3 is always
The default logic level for exporting vertical transfer signal is maintained to the arrival of next external input frame signal；
Address pointer of the output of pulse counter 2 as RAM1, RAM1 successively store external defeated from small to large according to address
The spectral coverage 1 that enters originates line number, spectral coverage 1 include line number, spectral coverage 2 originate line number and spectral coverage 1 originate line number and spectral coverage 1 comprising line number it
The difference of sum, spectral coverage 2 include line number, and so on, until spectral coverage x starting line number and spectral coverage x-1 starting line number and spectral coverage x-1
Difference comprising the sum of line number, spectral coverage x include line number, the remaining line number of area array CCD, preset ending mark character, number
Not equal to any value possible inside RAM1 in value；2 initial value of pulse counter is that the initial value of 0, RAM1 output is that spectral coverage 1 rises
Begin number, and whether the output that comparator 2 compares RAM1 is equal to preset ending mark character, due to signal system spectral coverage
Number is at least 1, therefore comparator 2 exports logical zero level；Pulse counter 3 comparator 1 output be logic 1 after, with it is local when
On the basis of clock, vertically transfer pulse periodic signal make can control under carry out plus 1 counts, while comparator 3 is by pulsimeter
Number device 3 is compared with the numerical value in the address 0 of RAM1, and spectral coverage 1 originates line number, within the output valve of pulse counter 3 is less than
When the output valve of portion RAM1, comparator 3 exports logical zero, and after level-one d type flip flop 4 and/or door 1, the gating output of selector 2 is hung down
Straight transfer continuities periodic signal, the output of selector 2 is after level-one d type flip flop 5, as the vertical transfer timing signal in memory block
Output；After pulse counter 3 count down to the numerical value of 0 address of RAM1, spectral coverage 1 originates line number, and comparator 3 exports logic 1, warp
It crosses phase inverter 2 and with after door 2, no longer enabling pulse counter 3, pulse counter keeps current count value；Selector 2 selects at this time
The logical default logic level for exporting vertical transfer signal, is used as the vertical transfer timing signal in memory block after level-one d type flip flop 5
Output；
Comparator 3 remains logic 1, and pulse counter 4 is carried out in the case where system clock and vertical transfer are with the effect of frequency periodic signal
Add 1 counting, selector 3 exports preset fixed value 1 under the control of d type flip flop 7, and comparator 4 is by 4 He of pulse counter
Fixed value 1 is compared, and when the value of pulse counter 4 is less than 1, pulse counter 4 continues plus 1 counts；When pulse counter 4
Value is equal to 1, and comparator 4 exports logic 1, and the output of comparator 4 carries out after d type flip flop 6 with the output of comparator 4 and behaviour
Make, obtains the high level pulse that a width is a vertical transfer signal period, the pulse and externally input vertical transfer
Pulse periodic signal with after door 5 by being used as enable signal to act on d type flip flop 7, the control that selector is exported in d type flip flop 7
Under system, gating n output, the occupied vertical migration period number of n, that is, horizontal transfer a line pixel, while the high impulse is for multiple
Digit pulse counter 3 resets its count value, and by carrying out adding 1 operation, internal RAM 1 with enabling pulse counter 2 after door 3
Output be address 1 content, spectral coverage 1 include line number, comparator 3 compare pulse counter 3 and internal RAM 1 output valve, than
Logical zero is exported compared with device 3, pulse counter 4, which is in, resets cleared condition；
After vertical transfer timing module has carried out the vertical transfer timing signal output of x spectral coverage as procedure described above, pulsimeter
Number device 2 count down to the address RAM1 for being stored with ending mark character, and comparator 2 compares the output and preset ending of RAM1
Identify character it is whether equal, when equal, comparator 2 export logic 1, by or door 2 after reset pulse counter 3, select simultaneously
It selects device 2 and gates vertical transfer signal default logic state, as the vertical transfer signal output in memory block after d type flip flop 2.
5. a kind of signal processing system of variable spectral coverage multispectral camera based on area array CCD according to claim 2,
Be characterized in that: the horizontal transfer tfi module in variable spectral coverage sequence controller includes pulse counter 5, comparator 5, selector
3, with door 6 and with door 7；One input terminal of externally input continuous cycles horizontal transfer R signal connection and door 6, external input
An input terminal of the horizontal transfer enable signal connection with second input terminal of door 6 and with door 7, the output end with door 6 is
For horizontal transfer R clock signal；Second input terminal of externally input continuous cycles RST signal connection and door 7, with door 7
The enable end EN of output end connection pulse counter 5；Externally input 4 frequency doubling clock of pixel frequency connection pulse counter 5
Clock end, the input terminal A of the output end connection comparator 5 of pulse counter, the input terminal B connection of comparator 5 are externally input
Horizontal pixel merges number；The output end of the address end A0 connection comparator 5 of selector 3, the input terminal D0 connection water of selector 3
Flat turn moves the default logic level of RST clock signal, the externally input continuous cycles RST letter of the input terminal D1 connection of selector 3
Number.
6. a kind of signal processing system of variable spectral coverage multispectral camera based on area array CCD according to claim 5,
Be characterized in that: the pulse counter 5 is on the basis of externally input 4 frequency doubling clock of pixel frequency, when horizontal transfer signal makes
It is carried out when energy be logic 1 and continuous cycles RST signal is logic 1 plus 1 counts, while comparator 5 compares the defeated of pulse counter 5
Value and horizontal pixel merge number out, and when the value of pulse counter 5, which is less than horizontal pixel, merges number, the output of comparator 5 is patrolled
0 is collected, the gating default RST logic level of selector 3 is exported as horizontal transfer RST clock signal；When the value etc. of pulse counter 5
When horizontal pixel merges number, comparator 5 exports logic 1, and selector 3 gates continuous cycles RST signal as horizontal transfer
The output of RST clock signal；
Horizontal transfer enable signal and continuous cycles horizontal transfer R signal carry out and are used as horizontal transfer R clock signal after operation
Output.
7. a kind of signal processing system of variable spectral coverage multispectral camera based on area array CCD according to claim 1,
It is characterized in that: the first resistor R1, second resistance R2 value range are as follows:3rd resistor R3 value needs
The impedance of driving signal cabling on match circuit plate；4th resistance R4 value 100K Ω；First capacitor C1 and 3rd resistor R3 group
At low-pass filtering, increase the rise time of driving signal；Capacitance C2 value 1uF.
8. a kind of signal processing system of variable spectral coverage multispectral camera based on area array CCD according to claim 1,
Be characterized in that: the band come down in torrents charge function area array CCD include exposure region and memory block, memory block does not expose and pixel knot
Structure is identical as exposure region, can be by exposure region signal charge fast transfer to memory block by continuous vertical transfer；Band comes down in torrents electricity
The area array CCD of lotus function has the function of rapid dump horizontal register signal charge, can be by nontarget area signal charge
Quickly remove.
9. a kind of signal processing system of variable spectral coverage multispectral camera based on area array CCD according to claim 1,
Be characterized in that: the A/D chip that the analog to digital conversion circuit includes has the function of correlated-double-sampling, and has change pixel in real time
The ability directly to work according to new parameter after frequency without configuration；The input parameter includes: the light of spectral coverage number, single spectral coverage
Spectral limit.
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| CN108495065B (en) * | 2018-02-01 | 2020-11-06 | 中国科学院国家空间科学中心 | Driving time sequence control method of frame transfer type area array CCD |
| CN109688314B (en) * | 2019-02-19 | 2021-03-09 | 福州视驰科技有限公司 | Camera system and method with low delay, less cache and controllable data output mode |
| CN111510647B (en) * | 2020-04-27 | 2021-08-31 | 中国科学院长春光学精密机械与物理研究所 | Uniform charge transfer control method for multi-spectral-segment TDICMOS |
| CN111830816B (en) * | 2020-06-28 | 2023-05-12 | 南京天朗防务科技有限公司 | Self-adaptive timing method and device |
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