JPH11275469A - Sensor array device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a sensor array device high in S/N, small in scale and high in operating speed. SOLUTION: An M series generator 3 generates an M series signal based on a clock and a timing signal generated by a control circuit 2, a shift register 4 generates pluralities of delayed M series patterns to control an analog switch 5. The analog switch 5 connects pluralities of sensor elements of a sensor array 1 simultaneously to a current amplifier 6 in a way depending on a pattern of the M series. A correlation device 7 consisting only of adders and subtractors applies demultiplexing arithmetic operation to an output of the current amplifier 6 to demultiplex outputs of each element of the sensor array 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a one-dimensional or two-dimensional
The present invention relates to a one-dimensional or two-dimensional sensor array device in which sensor elements are arranged dimensionally and a certain physical quantity is sensed in parallel.

[0002]

2. Description of the Related Art A sequential scanning method is well known as a scanning method for a sensing device having an array structure. FIG. 20 is a general configuration diagram of a conventional sensor array device, where 101 is a sensor array, 102 is a control circuit, 103
Is a start pulse generator, 104 is a shift register, 1
05 is an analog switch, and 106 is an amplifier.

[0003] The sensor array 101 is composed of n sensor elements, and outputs a sensed signal as a current output ai when a bias Vb is applied. The control circuit 102 generates a clock and supplies the clock to the start pulse generator 103 and the clock terminal of the shift register 104.

[0004] The start pulse generator 103 generates a pulse by dividing the input clock by n and supplies the pulse to the data input terminal of the shift register 104. The Q output terminal of each stage of the shift register 104 is connected to the analog switch 105
Is connected to the control terminal. The analog switch 105
As shown in FIG. 20, the voltage supplied from the Q output terminal of the shift register 104 controls whether each output terminal of the sensor array 101 is connected to the a terminal side or the b terminal side.

FIG. 21 is a timing chart showing a sequential read operation of the sensor array device shown in FIG.
In FIG. 21, when a start pulse is supplied and only one clock is supplied to the clock terminal of the shift register,
The output of the shift register is "1", "0", "0", ...
, "0", "1" is applied to the control terminal of the analog switch SW0, and the other analog switches SW1
ＳＷSWn−1 is in a state where “0” is applied.

Subsequently, when a clock is supplied to the shift register 104, the analog switches SWi are sequentially connected to the terminal a. Therefore, the amplifier 106 obtains detection signals a0, a1, a2,..., An-1 in synchronization with the clock.

Further, as disclosed in Japanese Patent Application Laid-Open No. 57-118740, there is a sensor array device which controls ON / OFF by a bias voltage using a diode instead of the analog switch 105.

Another sensing device having an array structure is disclosed in Transactions of the Society of Instrument and Control Engineers, Vol. 23, no. 5
As disclosed in “One Method of Scanning Sensor Array”, there is an ultrasonic sensor array device using an M-sequence.
In this device, ultrasonic waves emitted from an ultrasonic source placed at a distant position are received by a plurality of microphones arranged on a straight line, and the microphones to be received are selected and amplified in the M series, and the same M series is received. Performs correlation detection. In this scanning method, the signal energy increases because the outputs from a plurality of microphones are collected at the same time. As a result, when the ratio with the energy of the noise generated by the adder or the A / D converter is increased, the signal is restored. S / N is increased.

Further, as disclosed in Japanese Patent Application Laid-Open No. H8-261751, there is a star scanner device using an optical mask of an M-sequence code pattern. The optical mask of the M-sequence code pattern of this device modulates the light projected on the light receiving element, and collects the ultrasonic energy in one place by a plurality of transmission delay elements and a plurality of transducers. In this method, the reflected ultrasonic waves are received by a plurality of wave receiving means, and the resolution and S / N are increased by a plurality of reception delay elements.

[0010]

However, FIG.
In the conventional technique shown in FIG. 21, the time during which one sensor element is selected is short, and the scanning time n clocks must be secured sufficiently because of thermal noise generated by the amplifier 106 and the feedback resistor at the subsequent stage. There is a problem that S / N cannot be secured. Further, since the sensors are arranged on the array, there is a problem that a delay occurs due to a stray capacitance between the lines of the analog switches, and the detection signal further decreases.

Further, in the above-mentioned Japanese Patent Application Laid-Open No. 57-118740, when the number of sensor elements is N, the leakage current of a sensor element other than the sensor element to be detected is multiplied by (N-1). If the leak characteristic at the time of OFF is not sufficiently ensured, the S / N ratio of the system cannot be ensured. That is, assuming that the detection signal of the sensor element alone at the time of ON bias is s and the leak current at the time of OFF bias is In, the S / N ratio of the system is s: (N-1) In, and when the number N of sensor elements is increased, , S / N deteriorates.

Also, the Transactions of the Society of Instrument and Control Engineers Vo
The two-dimensional sensor array device as described in 1.23, No. 5, has the following problems. +1 and-
Since the same M-sequence is used for both modulation and demodulation using an M-sequence having a binary value of 1, the defect that the average value r of the output of the sensor array enters the demodulated data as an error. there were. This is due to the fact that the matrix M * M has the property of pseudo-orthogonal rather than perfect orthogonal.

Furthermore, in the above-mentioned Japanese Patent Application Laid-Open No. Hei 8-261751, since the optical mask member is used as an M-sequence modulation element, it is necessary to perform scanning mechanically. However, there is a problem that the size becomes large when applied to small products such as information devices.

[0014]

In order to achieve the above object, a sensor array device according to a first aspect of the present invention comprises:
Timing generating means for generating a timing signal, M-sequence generating means for generating an M-sequence by the above timing, delay means for delaying the M-sequence signal output from the M-sequence generating means, and output from the delay means A switch means to be controlled, a sensor array connected to the switch means, a current amplifying means connected to the switch means, and an adder / subtracter connected to the output side of the current amplifying means and having a coefficient of 1 And correlation means configured.

According to the above arrangement, the M-sequence signal generated by the M-sequence generation means specifies a method for electrically selecting the sensor elements of the sensor array, and simultaneously obtains detection signals from a plurality of sensor elements. Since the noise of the amplifier input stage and the noise of the quantizer are added to the detection signal having high energy, the noise energy at the time of restoration is diffused, and relatively S
/ N is obtained.

According to a second aspect of the present invention, in addition to the configuration of the first aspect, the correlation means includes an A / D converter, a shift register group, and a plurality of adders. And one subtractor.

According to the above configuration, the detection signal from the amplifier is converted into digital data by the A / D converter, a delay signal is generated by the shift register group, and addition and subtraction are performed in parallel. Thus, it is possible to perform the restoration operation at high speed.

According to a third aspect of the present invention, in addition to the configuration of the first or second aspect, the correlation means includes an A / D converter, a memory device, and a program. An arithmetic unit that can be described in is used.

According to the above configuration, the detection signal from the amplifier is converted into digital data by the A / D converter and is taken into the memory device. Further, the CPU performs an addition / subtraction operation based on a program stored in the memory device, and performs an inverse operation of the scanning. Since it can be realized by a program and can be executed only by addition / subtraction operation, it is possible to restore read data flexibly and relatively quickly.

If the CPU stores an application program for processing and editing the read data in a memory device, the CPU has a sophisticated processing function that can be shared with the memory device and the CPU in addition to the restoration arithmetic processing. An array device can be configured.

According to a fourth aspect of the present invention, in addition to the configuration of the first aspect of the present invention, the correlation means includes a sample and hold circuit, a buffer circuit, an analog switch group, and an analog adder. And a differential amplifier.

According to the above configuration, an analog delay circuit is formed by arranging a sample-and-hold circuit, a buffer circuit, and an analog switch group in series with the detection signal from the amplifier being an analog signal. The output of each buffer circuit of the analog delay circuit is synthesized by two systems of analog adders, and the outputs of the two systems of analog adders are input to a differential amplifier to perform subtraction. A restoration operation can be performed.

According to a fifth aspect of the present invention, there is provided a sensor array device, comprising: a timing generating means for generating a timing signal; a first M-sequence generating means for generating a first M-sequence signal based on the timing signal; A second M-sequence generating means for generating a second M-sequence signal in response to a timing signal, a first delay means for delaying the first M-sequence signal output from the first M-sequence generation means, and an output of the first delay means First switch means controlled by
A second delay means for delaying a second M-sequence signal output from the M-sequence generation means, a second switch means controlled by an output of the second delay means, and one of the first switch means arranged in parallel Connected to the plurality of electrodes of the second
A two-dimensional sensor array connected to the other plurality of electrodes, the switch means being arranged orthogonally and parallel to the one electrode, a current amplifying means connected to the second switch means, A first correlating means connected to the output side of the amplifying means and comprising only an adder / subtractor having a coefficient of 1, a frame memory means for storing an output result of the first correlating means, The second correlation means is constituted only by an adder / subtracter for performing a correlation operation from the data obtained.

According to the above arrangement, the first M-sequence generation means, the first delay means, and the first switch means
Selection of ON or OFF of a plurality of sensor rows of the first coordinate axis (column electrode) of the sensor array is performed simultaneously, and the second M
A second coordinate axis (row electrode) is formed by the sequence generation means, the second delay means, the second switch means, and the current amplification means.
By simultaneously synthesizing and amplifying the sensor outputs output from the amplifiers, it is possible to collect sufficient detection energy before amplification, so that a larger S than the thermal noise, clock noise, and quantization noise generated after the amplifier. / N can be obtained. With the first correlating means, the frame memory means, and the second correlating means, it is possible to accurately recover the detection output corresponding to the position of the sensor array from the detection signal having a high S / N coded by the above-described scanning method. Become.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a sensor array device according to the present invention will be described with reference to the drawings.

[Embodiment 1] A one-dimensional sensor array device according to an embodiment of the sensor array device of the present invention comprises a sensor array 1, a control circuit 2, an M-sequence generator 3, as shown in FIG. It comprises a shift register 4, an analog switch 5, an amplifier 6, and a correlator 7.

The control circuit 2 generates a clock and supplies it to the clock terminal of the shift register 4 and the input terminal of the M-sequence generator 3. The M-sequence generator 3 generates an M-sequence signal consisting of "0" or "1" according to the input clock. The generated M-sequence signal is stored in a shift register 4
, And the shift register 4 sequentially inputs the M-sequence signal delayed from the left to the right for each clock unit to the control terminal of the analog switch 5. The analog switch 5 has a configuration as shown in FIG. 5, and according to “0” or “1” of the M-sequence signal,
The connected sensor element is connected to the b terminal or the a terminal. The terminal a is input to the current amplifier 6 and “
Current output ai of sensor element corresponding to 1 "(not shown)
Are added and amplified.

FIG. 2 is a detailed block diagram of the M-sequence generator shown in FIG. The M-sequence generator 3 in FIG. 2 is a circuit that generates an eighth-order M-sequence, and generates an M-sequence having a period = 2 ⁸ −1 = 255 clocks. Flip-flops 32, 33, 34
And 38 have their output terminals Q connected to the input terminals of XOR circuits (exclusive OR) 51, 52, 53, respectively.
The output of the OR circuit 51 is connected to the data input terminal D of the first flip-flop 31 and the M-sequence generator 3
To generate an M-sequence signal M (i).

FIG. 3 is a timing chart showing the operation of the M-sequence generator of the one-dimensional sensor array device shown in FIGS.

The outputs Q of the eight cascade-connected flip-flops 31 to 38 are all initially set to "1" by the reset pulse rm from the control circuit 2, and are initialized. Subsequently, the clock ck is continuously supplied, and every time the rising edge of the clock ck is input, the output terminal Xk of the M-sequence generator 3 outputs the clock signal Mk in chronological order.
(0), M (1), M (2)... M (n−1) · M (K−1) M-sequence signal m is output. The M-sequence signal m is input to the shift register 4 and shifts the data to the right each time the clock ck is input.

Since the sensor element Si corresponding to each output "1" of the shift register 4 is turned on and is simultaneously output to the amplifier 6, the reset pulse rm is supplied, and when n clocks elapse, the analog switch SW0 is turned on. Corresponds to the M-sequence signal M (n-1), and the analog switch SWn-1 corresponds to the M-sequence signal M (0). This state will be described with reference to FIG.

FIG. 4 is a diagram showing a spatial positional relationship and a temporal change in sensor array selection.

Assuming that the number of sensor elements is n, the repetition period of the M series is K clock, and the thermal noise generated at the input part of the amplifier 6 and the feedback resistor is ni, the output fi of the amplifier 6 at the i-th clock is 4 is expressed by the following equation.

[0034]

(Equation 1)

Here, M is a K × K symmetric matrix composed of M sequences having values of 0 or 1.

[0036]

(Equation 2)

When Expression 1 is simplified and expressed in a vector, the following expression is obtained.

F = Ma + n (1) Mr is defined as a matrix in which elements 0 and 1 of M are exchanged, and M− Write Mr = B, and write B on both sides of equation (1) from the left.
* 2 / (K + 1) multiplied by 2 / (K + 1) B * M =
Since I, (I is a unit matrix of K × K) 2Bf / (K + 1) = a + 2Bn / (K + 1) (2) where f is the output of the amplifier 6 and 2 * B / (K + 1) is Correlator 7
And the output of the correlator 7 is represented by the equation (2). The first term on the right side of the equation (2) is a restored sensor element signal, and the second term is a noise term. B element is ± 1
Therefore, for example, looking at the noise related to an-1, the following equation is obtained.

[0039]

(Equation 3)

Ni are independent of each other and their effective values are σn0 = σn1 =... = ΣnK-1 = σn.

[0041]

(Equation 4)

In the case of K >> 1, the noise is reduced to 1 / SQRT [K] as compared with the conventional sequential scanning method.

Next, the configuration of the correlator 7 for performing the above operation will be described. Basically, the operation of the coefficient ± 1 is addition / subtraction, and in the case of the M series, since K + 1 is 2 ^m (m is an integer), 2 / (K
+1) is realized by a bit shift.

FIG. 6 is a block diagram of a one-dimensional sensor array device according to an embodiment of the present invention.
FIG. 7 is a configuration diagram using a D / D converter, a line memory, and an adder, and FIG. 7 is a configuration diagram similarly using a sample-hold circuit and an operational amplifier as a correlator.

In FIG. 6, the output terminal of the amplifier 6 is connected to the input terminal Ain of the A / D converter 39.
The / D converter 39 converts the analog signal into a c-bit digital signal. The converted digital signal is supplied to D terminals of flip-flops 30 to 3n-1, and a delay signal is generated by n * c flip-flops. Corresponding to the element ± 1 of the matrix B, when the element is +1, the operation proceeds to the adder 40. When the element is -1, the other adder 41 is operated.
And the subtractor 42 obtains the final calculation result.
Each time the clock signal ck is input, the matrix B and the vector f
Is output from the subtractor 42 in time series. The configuration as shown in FIG. 6 has an advantage that a restoration signal can be obtained in real time in synchronization with the clock ck.

In FIG. 7, a sample-and-hold circuit group A
The output terminals of the amplifier 6 are connected to the first stage inputs of 0 to An−1, and the sample and hold circuit groups A0 to An−1
Are connected in cascade, and every time the clock ck is input, analog data is transferred to the subsequent sample and hold circuit. That is, the sample hold groups A0 to A0
An-1 performs the function of an analog delay. The output terminal of each sample and hold circuit is connected to the addition operational amplifier 43 or the addition operational amplifier 4 depending on the sign of the coefficient of the matrix B.
4, the output of the addition operational amplifier 43 is input to the + input terminal of the operational amplifier 45, and the output of the addition operational amplifier 44 is input to the − input terminal of the operational amplifier 45. The operation result of the matrix B, which is 1, and the output f of the amplifier 6 is output to the output terminal of the operational amplifier 45. When an analog configuration is used, it is possible to perform a high-speed restoration operation with low power consumption.

With respect to the configuration of the correlator 7, various configurations other than those described above are conceivable. For example, there are methods of using a line memory instead of the flip-flop, using a CPU or DSP instead of an adder / subtractor, using a CCD instead of a sample and hold circuit group, and using a surface acoustic wave as a correlator. . When a CPU or DSP is used, a correlation operation can be performed by software, and since the product-sum calculation coefficient is ± 1, the configuration can be easily performed at high speed.

In any case, any method of calculating the product of the matrix B and f using only addition and subtraction can be regarded as an embodiment based on the same idea.

[Embodiment 2] A case where a diode and a pin photodiode as shown in FIG. 8 are used as the sensor elements of the sensor array 1 of the one-dimensional sensor array device described in the embodiment will be described.

The basic operation is the same as in the above embodiment. As shown in FIG. 1, the control circuit 2 generates a clock and supplies the clock to the clock terminal of the shift register 4 and the input terminal of the M-sequence generator 3. In the M-sequence generator 3, M consisting of "0" or "1" is set in accordance with the input clock.
Generate a sequence signal. The generated M-sequence signal is supplied to the data input terminal of the shift register 4, and the shift register 4 controls the analog switch 5 by sequentially delaying the M-sequence signal from left to right for each clock unit. Input to the terminal.

The analog switch 5 has a configuration as shown in FIG. 5, and changes the connected sensor element to the a terminal or the b terminal in accordance with “0” or “1” of the M-sequence signal. Connecting. The terminal a is connected to the voltage Va,
The terminal b is connected to the voltage Vb. The output terminal of the analog switch 5 is connected to one of the column electrodes 12 of the sensor element groups S0 to Sn-1 in FIG.
The other terminals of .about.Sn-1 are commonly connected to a row electrode 11, and the row electrode 11 is connected to the input side of the amplifier 6.

FIG. 9A shows a cross-sectional structure of the sensor element, and FIG. 9B shows a detailed structure of a main part thereof.

As the sensor element, a metal electrode 12 is deposited on a glass substrate 11, and a pin structure for converting light into electricity and an a-Si layer 13 for forming a diode for preventing backflow are formed on the metal electrode 12. Is formed by a CVD method, and a transparent electrode ITO14 is deposited thereon to form a target device as the other electrode.

FIG. 10 shows typical IV characteristics when light is applied to the sensor element having the structure shown in FIG.

When the applied voltage V is +0.5 V, the current output is almost 0 and -Ileak. When the applied voltage V is -0.5 V, the output current is Ion. 8, when a row electrode 11 is a metal electrode and a column electrode 12 is an ITO transparent electrode, a photodetection current can be extracted from the sensor element when a negative voltage is applied to the column electrode 12 side.

In FIG. 5, +0.5 V is applied to the terminal a of the analog switch 5 and -0.5 V is applied to the terminal b. Now, as shown in FIG. 5, the control terminal of the analog switch 5 has "1" for SW0, "0" for SW1,.
When a voltage such as "0" is applied to SWn-1, "-0.5 V" is applied to the sensor element S0, "+0.5 V" is applied to S1, and so on.
"+0.5 V" is applied to Sn-1. The row electrode 11, which is the opposite electrode of the sensor element, is connected to the minus input terminal of the amplifier 6, and the plus input terminal of the amplifier 6 is connected to the ground. At the same time, the output current from the sensor element to which a voltage of -0.5 V is applied flows, and the current is amplified through the feedback resistor of the amplifier 6. The output of the amplifier 6 is output to the correlator 7.

When the sensor element has a structure as shown in FIG. 9, a small amount of light that enters the sensor reaches not only the photodiode part of the pin but also the backflow prevention diode of pn, and the leakage current -It is a factor of Ileak. Therefore, the leak current -Ileak also changes in proportion to the incident light intensity. Under a certain illuminance, the output current when the sensor element Si is turned on (−0.5 V) is expressed as Ion =
Assuming ai, the leak current Ileak at the time of off-bias (+0.5 V) is expressed by the following equation.

Ion = ai (3) Ileak = k * ai (3) (4) where 0 <k << 1 From the above equation, the output f of the current amplifier 6 is f = M * a-Mr * k * a・ ・ (5)

When (M−Mr) / 128 is multiplied from the left side of both sides, assuming that the number of sensor elements is 160, Bf / 128 = BMa / 128−BMka / 128 = (1 + k) a−k * 160/128 * a ... (6) As described above, using the sensor element having the IV characteristic as shown in FIG.
When the restoration processing is performed, the effect of the leak current is as follows with respect to the original detection signal a as shown in the second term of the equation (8).
(1 + k) times detection signals are obtained, and k * 160/128
* A leak is mixed.

This is because a simple pulse scan method as disclosed in Japanese Patent Application Laid-Open No.
1) Compared to the case where the number is doubled, 2 *
N / (K + 1) <2 times or less.

Third Embodiment FIG. 11 is a block diagram of a two-dimensional sensor array device according to another embodiment of the sensor array device of the present invention.

For the sake of simplicity, the number of sensor elements is set to 160 × 160 and the order of the M series is set to 8 (repetition period K
= 255) using two M-sequence generators.

In FIG. 11, 15 is a timing generator, 16 is a first M-sequence generator, 17 is a first shift register, 18 is a first analog switch, 19 is a two-dimensional sensor array, 20 is a second M-sequence generator, 21 is a second shift register, 22 is a second analog switch, 23 is a differential current amplifier, 24 is an A / D converter, 25 is a first correlator, 26
Is a frame memory, and 27 is a second correlator.

The timing generator 15 divides the reference clock to generate various control signals for controlling the entire system. The first M-sequence generator 1 receives the clock ck1 and the reset pulse rm1 output from the timing generator 15, generates a first M-sequence signal synchronized with the clock ck1, and generates the generated first M-sequence signal. Is supplied to one input terminal of the first shift register 17. At the same time, the clock ck1 generated by the timing generator 15 is supplied to the other input terminal of the first shift register 17. The first shift register 17 includes, as shown in FIG.
In this configuration, the flip-flops are connected in series, the data is shifted from left to right of the first shift register 17 in FIG. 11, and the output terminal of each flip-flop 1Dn is connected to the first analog switch 18D. Are supplied to the corresponding control terminals.

The first analog switch 18 is composed of 2 channels × 160 analog switches.
The common terminal side is connected to each column electrode of the two-dimensional sensor array 19, one terminal of two channels is connected to the terminal a in common with other analog switches, and the other terminal is connected to the b terminal.
Connected to terminal. +0.5 V is applied to the a terminal and -0.5 V is applied to the b terminal. The analog switch 18 sets +0.5 V according to the logic level of the control terminal.
V or -0.5 V is applied to the column electrodes of the two-dimensional sensor array 19.

As shown in FIG. 18, the detailed configuration of the two-dimensional sensor array 19 is such that a backflow prevention diode is connected to the row electrode group 191 and a pin diode for converting light into current is connected to the column electrode group 192. The structure is as shown in FIG.

On the other hand, the second M-sequence generator 20 receives the clock ck1 and the enable signal EN and the reset pulse rm2 output from the timing generator 15, and receives the clock signal ck2 and the second M-sequence synchronized with the enable signal EN and the clock ck1. And generating a second M-sequence signal.
It is supplied to one input terminal of the shift register 21. At the same time, the clock ck1 generated by the timing generator is supplied to the other input terminal of the second shift register 21. The second shift register 21, as shown in FIG.
The configuration is such that 160 flip-flops are connected in series, the data shifts from the top to the bottom of the row electrodes of the two-dimensional sensor array 19 in FIG. 11, and the output terminal of each flip-flop 2Dn is 2 analog switch 22
Are supplied to the corresponding control terminals.

The second analog switch 22 is composed of 2 channels × 160 analog switches.
The common terminal side is connected to each row electrode of the two-dimensional sensor array 19, one terminal of two channels is connected to the a 'terminal in common with the other analog switches, and the other terminal is connected to the b' terminal. Have been. The amplifier 232 is connected to the terminal a '.
Of the amplifier 231 is connected to the b 'terminal.
The input terminal is connected, and the second analog switch 22 selects a row electrode to which the sensor element of the two-dimensional sensor array 19 is connected according to the logic level of the control terminal.

That is, if the logic level is "0", the corresponding row electrode is connected to the amplifier 232 and "1"
If so, the corresponding row electrode is connected to amplifier 231. At this time, since the + input terminals of the amplifier 231 and the amplifier 232 are connected to the ground, the amplifier 231 and the amplifier 232 amplify the current, and
A 0 V bias potential is applied to the row electrodes 9. That is, the row electrode side of one terminal of each sensor element is fixed to 0V potential, and the other terminal is + 0.5V or -0.5V.
Since the voltage of 0.5 V is applied, the detected current is supplied to the amplifier 231 or 232 through the second analog switch 22 in accordance with the IV characteristic as shown in FIG.
Amplified by The amplifier 233 calculates the difference between the outputs of the amplifiers 231 and 232 and outputs the difference to the A / D converter 24.

The details of the above scanning method will be described with reference to the timing chart of FIG.

As shown in FIG. 11, the timing generator 1
5, the clock ck1 and the reset pulse rm1 are
The clock M1 is supplied to the first M-sequence generator 16 and the first shift register 17, and receives the clock ck1, the reset pulse rm2,
The enable signal EN is supplied to the second M-sequence generator 20 and the second shift register 21. First, the reset pulses rm1 and rm2 are supplied, the first M-sequence generator 16 and the second M-sequence generator 20 are initialized, and the M-sequence signal M (0) is output as the output signals Xk1 and Xk2. Is done. The first M-sequence generator 16 synchronizes with the successively input clock ck1 and successively outputs M-sequence signals M (1), M (2),.
(159) is generated.

On the other hand, as shown in FIG. 17, the second M-sequence generator 20 has an input terminal EN for the enable signal EN, and changes the time series of the M-sequence only while the enable signal EN is "1". Therefore, in FIG. 14, an M sequence is generated for 160 clocks during a period when the enable signal EN is "1". That is, for the first 160 clocks, the M-sequence signals M (0), M (1),..., As the output signal Xm2, like the output signal Xm1 of the first M-sequence generator.
.. M (159) is generated.

The input terminal of the first shift register 17 has
The output signal Xk1 and the clock ck1 are supplied, and the input output signals Xk1,.
That is, the M-sequence signal is shifted to the right. When the input of the first 160 clocks is completed, m is applied to the column electrode C0.
(159), a bias voltage of +0.5 V or -0.5 V corresponding to M (0) is applied to M1 (158),. At the same time, the output signal Xk2, the clock ck1, and the enable signal EN are supplied to the input terminals of the second shift register 21. Since EN is "1", the input is enabled and also input in synchronization with the clock ck1. The output signal Xk2, that is, the M-sequence signal, is shifted to the right. When the input of the first 160 clocks is completed, m (159) is applied to the row electrode R0, M (158),.
Is connected to an amplifier 231 or 232 corresponding to M (0), and a detection output f0 appears at an output terminal of the amplifier 233 as a differential output. This 160 clock period is defined as a prescan period.

The operation after the 161 clock is the main scan period, and the first M-sequence generator 16 continuously outputs the M-sequence signal M to the output signal Xk1 in synchronization with the clock ck1.
(160), M (161),..., M (254), and further repeatedly outputs M-sequence signals M (0),. 2M
The enable signal EN of the sequence generator 20 becomes "1" for only one of the 255 clocks, and the state changes when the clock ck1 is input only at this time. That is, during the present clock period, the first M-sequence generator 16, the first shift register 17, and the first analog switch 18 scan at high speed in synchronization with the clock ck1, and the second M-sequence generator 20 and the second shift register 21 The second analog switch 22 performs a low-speed scan in which the state changes only one clock per 255 clocks.

Here, the current output of the sensor elements Si, i is turned on.
Assuming ai, i at the time of bias and 0 at the time of OFF bias, the amplifier output fi, i is expressed by the following equation.

F0,0 f1,0 ・ f254,0 a159,159 a158,159 ・ a0,159 0 ・ 0 f0,1 f1,1 ・ f254,1 = M a159,158 a158,158 ・ a0,158 0 ・0 B + N ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ f0,254 f1,254 ・ f254., 254 a159,0 a158,0 ・ a0 , 0 0 ・ 0 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ (7) In a simplified notation of equation (7), F = MAB + N ・ ・ ・ ・ ・ ・ ・ ・ ・... (8)

Next, the operation of restoring the original sensor current output ai, i from the detected signal F will be described.

The detection signal F is converted into a p-bit digital signal by the A / D converter 24 and input to the first correlator 25. The first correlator 25 has, for example, the configuration shown in FIG. I have.

In the period of the first 255 clocks of the main scan at the timing shown in FIG.
The data of f0,254 are flip-flops 3D0 to 3D25.
4 is stored. At the 255th clock of the main scan, the enable signal EN becomes “1” and the selectors 1SE0 to 1SE1
SE254 selects the output from flip-flops 3D0 to 3D254, and outputs the flip-flops 4D0 to 4D25.
4. Transfer the data. The enable signal EN becomes “0” from the next clock ck, and the selectors SE0 to SE2
54 selects the flip-flops 4D0 to 4D254 so as to form a cyclic shift register.

The output Q of the flip-flops 4D0 to 4D254 is input to the input of the adder 251 corresponding to "1" of the M-sequence signal and to the adder 252 corresponding to the M-sequence signal "0".
Is mechanically connected to the input terminal. The output Sm1 of the adder 251 and the output Sm2 of the adder 252 are obtained by subtracting
And subtraction is performed, and the operation result is finally output as a correlator output RCX. 25 of the main scan
From the sixth clock to the 509th clock, the flip-flops 4D0 to 4D254 cyclically shift data, so that the input data f0,0 to f0,254 and the matrix B
Appears in the output of the subtractor. When the lower 7 bits of the output S are omitted and output, the first correlator 25 of p bits is output.
As the correlator output RCX. Correlator output RCX
Is represented by the following equation.

BF / 128 = BM / 128AB + BN / 128 = AB + BN / 128 (9) The obtained correlator output RCX is input to the frame memory 26. The timing generation circuit 15 sets the R / W of the frame memory 26 to "0" for 255 * 255 clocks from the 256th clock of the main scan, sets the frame memory 26 to the write mode, and outputs the correlator output R
CXs are sequentially stored. Note that R in the frame memory 26
When / W is "0", the horizontal address XADR and the vertical address YADR of the frame memory 26 are counted up in synchronization with the clock ck1 as shown in FIG. Is counted up by 255, the vertical address YADR is counted up by one.

When the R / W of the frame memory 26 becomes "1", the frame memory 26 enters the reading mode,
The data of the equation (11) is read. In read mode,
When the vertical address YADR counts up in synchronization with the clock ck1 and the vertical address YADR counts up by 255, the horizontal address XADR counts up by one. In this way, the data of the equation (11) written in the frame memory 26 can be read by transposing the matrix.

FIG. 13 shows the configuration of the second correlator. The read data Di of the frame memory 26 is stored in the shift register D0.
Is supplied to the D terminal of
The read data Di input for 5 clocks shifts the shift registers 5D0 to 5D254 to the right, and shifts the shift registers 6D0 to 6D254 by the T pulse of the 255th clock.
Transfer to The output terminals of the shift registers 6D0 to 6D254 correspond to the M-sequence signal m (i), and
Connected to the input. The adder 271 outputs the addition result to the Sm3 terminal. By omitting the lower 7 bits, the division by 128 is performed simultaneously, and the correlator output RCY 'is output.
Output as The correlator output RCY 'is expressed by the following equation.

BFM / 128/128 = ABM / 128 + BNM / 128/128 = A + BNM / 128/128 (10) However, the correlator output RCY ′ is output in the order of the row direction and the column direction.

The first term of the equation (10) represents the current output ai, i of the sensor element, and the second term is a noise term. Since the matrix of B is a matrix composed of ± 1 elements, and M is a matrix composed of 1 or 0, each element ni, j of the noise N is independent, and assuming that the effective value is σn, by the statistical property,
The effective value σm of the second term of the expression (10) is σm = Sqrt [ΣΣ (± 1) ² * m (i) ² * σn ² ] / 128/128 = Sqrt [255 * 128] / 128/128 * σn ... (11), showing a noise improvement effect of 39.15 dB.

In the description, the sensor element Si, i is turned off.
Although the sensor output current at this time is set to 0, the above-mentioned scanning method can be applied to the case where k * ai, i (k is a constant and 0 <k <1) by expanding the discussion in Embodiment 2 to two dimensions. It can be seen that the influence of the error is significantly reduced.

In the embodiment, the M-sequence signal is used. However, as a binary signal other than the M-sequence signal, there are a Gold sequence, a Barker code, a Frank code, a complementary sequence code, and the like, and these may be used. These code sequences are suitable for a shift register structure and have a large noise suppression effect because the coefficient becomes ± 1.

As described above, the sensor array device according to the present embodiment comprises a timing generating means, an M-sequence generating means, a delay means for delaying an M-sequence signal output from the M-sequence generating means, , A sensor array connected to the switch means, a current amplifying means connected to the switch means, and a correlating means comprising only an adder / subtractor having a coefficient of 1. , And a sensor array device with a high S / N ratio can be realized.

[0089]

The sensor array device according to the present invention generates an M-sequence signal and outputs "0" or "1" of the generated M-sequence signal.
The sensor to be read is selected in accordance with the above, the detection signals of the plurality of sensors are combined and coded in the dimension of current to save a large amount of energy, and thermal noise generated by the amplifier, noise from the system, A / D converter By lowering the energy ratio of the quantization noise generated in step (a) and restoring the energy using a correlator consisting of only an adder / subtractor, a sensor array device that has a high S / N and operates at high speed on a small scale is provided.

[Brief description of the drawings]

FIG. 1 is a block diagram according to an embodiment of a sensor array device of the present invention.

FIG. 2 is a detailed configuration diagram of an M-sequence generator shown in FIG.

FIG. 3 is a timing chart showing a sequential read operation of an M-sequence generator of the one-dimensional sensor array device shown in FIGS. 1 and 2;

FIG. 4 is a diagram showing a spatial positional relationship and a temporal change in selection of a sensor array according to the sensor array device of the present invention.

FIG. 5 is a configuration diagram of an analog switch according to the sensor array device of the present invention.

FIG. 6 is a configuration diagram of a digital correlator according to an embodiment of the sensor array device of the present invention.

FIG. 7 is another configuration diagram of the analog correlator according to the embodiment of the sensor array device of the present invention.

FIG. 8 is a configuration diagram of a sensor array using a photodiode and a blocking diode according to an embodiment of the sensor array device of the present invention.

FIG. 9 is a cross-sectional view of a principal part showing a structure of a photodiode and a blocking diode according to the sensor array device of the present invention.

10 is an IV characteristic diagram of the sensor element shown in FIG.

FIG. 11 is a block diagram showing a configuration of a two-dimensional sensor array device according to another embodiment of the sensor array device of the present invention.

FIG. 12 is a configuration diagram of a first correlator shown in FIG. 11;

FIG. 13 is a configuration diagram of a second correlator shown in FIG. 11;

FIG. 14 is a timing chart showing a scanning method of the two-dimensional sensor array device shown in FIG.

FIG. 15 is a configuration diagram of a first shift register shown in FIG. 11;

FIG. 16 is a configuration diagram of a second shift register shown in FIG. 11;

17 is a configuration diagram of a second M-sequence signal generator shown in FIG.

18 is a configuration diagram of a two-dimensional sensor array using the photodiode and the blocking diode shown in FIG.

FIG. 19 is a timing chart showing a restoration calculation operation of the two-dimensional sensor array device shown in FIG.

FIG. 20 is a general configuration diagram of a conventional sensor array device.

21 is a timing chart showing the operation of the sensor array device of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Sensor array 2 Control circuit 3 M series generator 4 Shift register 5 Analog switch 6 Amplifier 7 Correlator 15 Timing generator 16 1st M series generator 17 1st shift register 18 1st analog switch 19 2D sensor array 20 2M Sequence generator 21 Second shift register 22 Second analog switch 23 Differential current amplifier 24 A / D converter 25 First correlator 26 Frame memory 27 Second correlator

Claims (5)

[Claims] 1. A timing generating means for generating a timing signal, an M-sequence generating means for generating an M-sequence signal based on the timing signal, and a delay means for delaying an M-sequence signal output from the M-sequence generating means A switch unit controlled by an output from the delay unit; a sensor array connected to the switch unit; a current amplifying unit connected to the switch unit; a coefficient connected to an output side of the current amplifying unit; And a correlation means comprising only an adder / subtracter having a value of 1. 2. The sensor array according to claim 1, wherein said correlation means comprises an A / D converter, a shift register group, a plurality of adders, and one subtractor. apparatus. 3. The sensor array device according to claim 1, wherein the correlating means uses an A / D converter, a memory device, and an arithmetic device that can be described by a program. 4. The sensor array device according to claim 1, wherein said correlation means comprises a sample hold circuit, a buffer circuit, an analog switch, an analog adder, and a differential amplifier. 5. A timing generating means for generating a timing signal, a first M-sequence generating means for generating a first M-sequence signal based on the timing signal, and a second M-sequence signal based on the timing signal A second M-sequence generating means; a first delay means for delaying a first M-sequence signal output from the first M-sequence generating means; a first switch means controlled by an output of the first delay means; A second delay means for delaying a second M-sequence signal output from the sequence generation means, a second switch means controlled by an output of the second delay means, and one of the first switch means arranged in parallel. Two-dimensional sensor connected to a plurality of electrodes, and wherein the second switch means is connected to another one of the plurality of electrodes arranged in parallel to and perpendicular to the one electrode. A current amplifying means connected to the second switch means; a first correlating means connected to an output side of the current amplifying means, the adder-subtractor having a coefficient of 1; A frame memory for storing an output result of the means, and a second correlator comprising only an adder / subtractor for performing a correlation operation from the data stored in the frame memory. Sensor array device.