JP3141832B2 - A / D converter and A / D converter using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter and an A / D converter using the same, and more particularly , to an A / D converter with high resolution, high speed , and simplified circuit, and an A / D converter. The present invention relates to an A / D converter used.

[0002]

2. Description of the Related Art Generally, an A / D converter converts an input analog signal into digital data. A conventional A / D converter will be described with reference to FIGS. 8, 9, and 10. FIG. Conventionally, this type of A / D converter is, for example,
"Camera on" by Bryan Ackland et al.
Chip "(ISSCC96 DIGEST OFT
ECNICAL PAPERS TA1.2 1996
As shown in FIG. 1, an A / D converter for converting a general analog signal into a digital signal is used for the purpose of high resolution, high speed, and simplification of a circuit.

FIG. 8 is a block diagram of a conventional single slope type A / D converter. In the figure, A / D applied when pixel signals for each row are simultaneously output from the sensor unit 230 having the pixels 231 arranged two-dimensionally.
4 shows a converter. Area 201 indicated by broken line
a, 201b,... have the same configuration, and are formed for each pixel column.

The basic circuit of the A / D converter is a counter circuit 205 for counting the number of clocks from the clock circuit.
, A D / A converter 206 that receives the output digital data as input, and outputs analog data of which the amplitude of the negative polarity monotonically increases, and an area 201a indicated by a broken line. A region 201a is a sample-and-hold circuit (hereinafter abbreviated as "S / H circuit") 207a for sampling and holding an analog input signal.
And a comparator 208a for comparing the magnitude of the output of this S / H circuit with the output of the D / A converter 206, and using the output of this comparator as a latch control signal to output digital data from the counter circuit 205. And a latch circuit 209a for input data.

Next, the operation of the A / D converter having the above configuration will be described. Note that the area 201 indicated by a broken line
a, 201b... perform the same operation, so that
Only the operation of 01a will be described.

The negative signal output from the pixel 231 formed in the sensor section 230 becomes an analog input signal of the A / D converter in the area 201a. This analog input signal is generated by the S / H pulse generated in a predetermined cycle,
Sampled and held in the H circuit 207a. After being sampled and held, the counter circuit 205 starts outputting digital data.

D / A using this digital data as input
The magnitude of the output of the converter 206 and the output of the S / H circuit 207a are compared by a comparator 208a. And D / A
When the amplitude of the output of converter 206 becomes larger than the output of S / H circuit 207a, the output signal of comparator 208a changes from H level to L level (hereinafter abbreviated as “H → L”). A latch circuit 209a using the output of the comparator as a latch control signal latches and holds digital data output from the counter circuit 205 when the output of the comparator becomes L level.

By the above operation, the digital data latched and output from the latch circuit 209a is output to the pixel 23
It becomes digital data after A / D conversion of the analog input signal output from 1.

FIG. 9 is a schematic diagram showing the operation of a conventional A / D converter. Here, for the sake of simplicity, an example of a 3-bit A / D converter will be described. FIG. 7 shows a case where an analog input signal input to the A / D converter is sampled and held, and the output of the S / H circuit 207a has an amplitude of V0.

When the digital data of the counter circuit 205 is 100, D / D is output from the output V0 of the S / H circuit 207a.
The amplitude of the output of the A converter 206 increases (decreases as a voltage), the output of the comparator 208a changes from H to L (not shown), the latch circuit 209a performs a latch operation, and the result of the A / D conversion is performed. As a result, digital data 100 is obtained. At this time, the result of the A / D conversion has the amplitude V3 as analog data. Voltage ΔV = V3−V
0 is a quantization error due to A / D conversion.

FIG. 10 is a configuration diagram for making the A / D converter have a high resolution. An A / D converter of this type is disclosed in, for example, Japanese Patent Application Laid-Open No. 1-253319.

The circuit shown in FIG. 1 includes an A / D converter 301 for roughly A / D converting an analog input, a D / A converter 302 for D / A converting the conversion result, and input analog data. , An A / D converter 305 for A / D converting the difference data, and an A / D converter 305 for amplifying the obtained difference.
A multiplier 306 that performs bit shifting to make the result of the / D conversion into a fine A / D conversion result, and an A / D converter 30
1 and an adder 307 that combines the coarse A / D conversion result and the fine A / D conversion result.

The operation of the circuit having such a configuration is as follows. That is, the A / D converter 301
D / A conversion is performed, and the coarse A / D conversion result is D / A converted by the D / A converter 302. Then, the difference between the D / A conversion result and the analog input is obtained by the subtractor 303, and the difference result is amplified by the amplifier 304. After this amplification, A / D
The converter 305 performs a fine A / D conversion, and a multiplier 306
To shift the bit. Finally, the adder 307 performs bit synthesis. By doing so, high resolution A / D
Conversion can be realized.

[0014]

In the prior art described above, for example, when performing A / D conversion of N (N is an integer of 2 or more, the same applies hereinafter) bits, all N bits are A / D converted in the same manner. To perform D conversion, 2 ^N counts are required. For this reason, in a single-slope A / D converter, the higher the resolution, the longer the conversion time. Therefore,
There is a drawback that it cannot be applied to applications with high resolution and short conversion time.

Conventionally, for example, when performing N-bit A / D conversion, it is necessary to increase the clock frequency in order to generate 2 ^N counts in a short time. For this reason, in order to shorten the conversion time in the single-slope A / D converter, it is necessary to increase the clock frequency, and in an analog circuit or the like, it may not be applicable due to the limitation of the clock frequency of the circuit. There is.

Furthermore, conventionally, in order to perform fine A / D conversion, it is necessary to obtain difference data, and coarse A / D conversion is required.
At the same time as D conversion, D / A conversion cannot be performed to obtain difference data. For this reason, in order to increase the resolution, it is necessary to perform coarse A / D conversion first, then perform D / A conversion with the same number of bits or more to obtain difference data, and then perform finer A / D conversion. is there. For this reason, D
/ A conversion requires time, and high resolution A
There is a disadvantage that the conversion time for performing the / D conversion becomes long.

Further, when performing A / D conversion on a plurality of data, each A / D converter formed for each column has:
Coarse A / D converter, D / A converter for higher resolution,
It is necessary to provide a fine A / D converter and the like, and the circuit scale cannot be reduced, for example, the circuit cannot be shared. For this reason, when a plurality of data are simultaneously output from a sensor or the like, forming a high-resolution A / D converter for each column has a disadvantage in that the circuit scale becomes large. Therefore, when the area is limited, such as on-chip,
Either the resolution must be lowered to reduce the circuit scale, or A /
There is a drawback that the conversion time becomes longer due to the D conversion.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks of the prior art, and an object of the present invention is to provide an A / D converter which operates at a high speed at a low clock frequency and has a high resolution, and uses the A / D converter. An object of the present invention is to provide an A / D converter.
It is another object of the present invention to provide an A / D converter which has a small circuit scale and is suitable for on-chip implementation, and an A / D converter using the same.

[0019]

An A / D converter according to the present invention first compares an input analog signal to be converted into digital data with an analog signal corresponding to reference digital data whose value sequentially changes. Comparing means, and first latch means for latching the reference digital data at the time when the content of the comparison result of the first comparing means changes, and outputs the latched data as a conversion result A first A / D converter, and a difference detecting means for constantly outputting a difference between the input analog signal and an analog signal corresponding to the reference digital data, wherein an output of the difference detecting means at the time of the change is digitally output. A second A / D converter that converts the data into data and outputs the data, and combines the output of the first A / D converter and the output of the second A / D converter before combining them. And a synthesizing means for outputting as the digital data after conversion obtained by converting the input analog signal,
The second A / D converter is configured to perform the conversion at the time of the change.
Holding means for holding the output of the difference detecting means;
An analog signal equivalent to digital data
Is the minimum resolution of the first A / D converter.
Attenuator that attenuates the output to equal the size of
A step, a holding content of the holding means, and an output of the damping means.
Second comparing means for sequentially comparing
The reference at the time when the content of the comparison result changes
Second latch means for latching digital data.
And outputs the latched data as a conversion result.
It is characterized by doing.

[0020]

Further, another A / D converter according to the present invention includes:
A first switch for selectively outputting the input analog signal and the content held by the holding unit; and a second switch for selectively outputting an analog signal corresponding to the reference digital data and an output of the attenuating unit. 2 switch means, a first comparing operation for comparing the input analog signal with an analog signal corresponding to the reference digital data according to an output from the first and second switch means, and holding of the holding means. A second comparing the content with the output of said damping means;
And a shared latch circuit that latches the reference digital data at the time when the content of the comparison result of the shared comparison circuit changes, the shared comparison circuit comprising: The shared latch circuit is used as the first latch means and the second latch means, and the shared latch circuit is used as the first latch means and the second latch means.

The A / D converter according to the present invention has N rows (N
Is a positive integer, the same applies hereinafter) and M columns (M is an integer of 2 or more,
An A / D converter for converting an output signal of a two-dimensional sensor comprising a group of sensor elements arranged and arranged in the same manner into digital data.
The sensor elements are provided in a one-to-one correspondence with the sensor element groups in a row.

Another A / D converter according to the present invention is an A / D converter for converting an output signal of a two-dimensional sensor comprising sensor elements arranged in N rows and M columns into digital data. Wherein the A / D converter according to any one of claims 1 to 6 is provided in common for a plurality of rows of the M rows of sensor element groups, and the commonly provided A / D converter is provided.
The D converter is connected to the plurality of rows of sensor element groups in a time-division manner.

[0024]

[0025]

In short, the present converter is an N-bit single-slope A / D converter, in which A / D conversion for upper bits (bit number P) for coarse A / D conversion and fine A / D conversion are performed.
A / D conversion (bit number Q) for lower bits to be converted is performed. For this reason, the number of counts conventionally required for A / D conversion, which is 2 ^N, can be reduced to (2 ^P +2 ^Q ). Therefore, a high-speed and high-resolution A / D converter can be realized. Note that P and Q are both positive integers, and P + Q =
N.

When the same resolution is realized in the same conversion time, the clock frequency can be reduced.

Further, in the present invention, the upper bits A
At the same time as the / D conversion operation, difference data of the A / D conversion for lower bits is detected. That is, since the detected difference data is directly subjected to the A / D conversion of the lower bits, the A / D conversion data for the upper bits is D / A-converted after the A / D conversion processing for the upper bits is completed. There is no need to detect the difference between the analog input signal and the A / D conversion data for upper bits. Therefore, the A / D conversion processing for the lower bits can be performed a predetermined time after the A / D conversion processing for the upper bits is completed, and the processing time required for the A / D conversion can be reduced.

[0029]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a first embodiment of the present invention.
It is a block diagram which shows the example of a structure of a / D converter. Referring to FIG. 1, an A / D converter according to a first embodiment of the present invention includes:
This is an N-bit single-slope A / D converter. The converter includes an S / H circuit 7 for sampling and holding the analog input signal, a counter circuit 5 for counting the number of clocks from the clock circuit, and an output digital data of the counter circuit 5 which receives the digital data as an input. The magnitude of the output of the S / H circuit 7 and the magnitude of the output of the D / A converter 6 are compared with the D / A converter 6 that outputs analog data whose signal amplitude of the negative polarity monotonically increases according to the change. In order to obtain the upper bits of digital data, a coarse A / D
A / D converter 2 for upper bits for conversion (number of bits P)
And A / D conversion of the difference between the conversion result and the input signal to obtain a small A / D
A / D converter 3 for lower bits for performing D conversion (number of bits Q) and a bit combining circuit 4 for combining upper bits and lower bits after conversion to generate N-bit digital data Have been.

The upper bit A / D converter 2 (number of bits P) compares the magnitude of the output of the S / H circuit 7 with the magnitude of the output of the D / A converter 6, and compares the comparison result with the L level or The comparator 8 outputs at the H level, the inverter 15 inverts the output of the comparator 8, an OR gate 16 having the inverted output as one of its inputs, and a control signal S7 output from the gate 16. It comprises a latch circuit 9 for upper bits that performs a latch operation and uses digital data from the counter 5 as input data.

On the other hand, the lower bit A / D converter 3 (the number of bits Q) outputs the output signal of the D / A converter 6 and the S / H circuit 7
, An S / H circuit 11 that samples and holds the difference output, and that the maximum value of the output of its own circuit is the minimum resolution (LSB) of the D / A converter 6. ; Least Significant
Predetermined gain K such that it is equal to the magnitude of
And an amplifier circuit 12 that attenuates the output of the D / A converter 6, compares the magnitude of the output of the amplifier circuit 12 with the output of the S / H circuit 11, and compares the comparison result with the L level or the H level. , An inverter 17 for inverting the output of the comparator 13, an OR gate 18 having the inverted output as one of its inputs, and a latch operation in response to a control signal S12 output from the gate 18. And a lower-bit latch circuit 14 that receives digital data from the counter 5 as input data.

The comparators 8 and 13 can be configured using a well-known comparator or the like. Further, the difference detection circuit 10 can be configured using a known operational amplifier or the like.

The bit synthesizing circuit 4 is composed of two latch circuits that synthesize digital data of N bits by latching digital data of the latch circuits 9 and 14 as upper bits and lower bits, respectively.

In this converter, the inverters 21 and 22 and the OR gate 20 are used to generate the latch control signals S7 and S12 to the latch circuits 9 and 4 and the latch control signal to the latch circuit in the bit synthesizing circuit 4. And 21 are used.

As will be described later, when a plurality of analog signals such as sensors are output simultaneously and an A / D converter is provided for each sensor column, the S / H in the area 1 indicated by the broken line is provided. A circuit 7, an upper bit A / D converter 2, a lower bit A / D converter 3, and a bit synthesizing circuit 4 are formed for each column. On the other hand, only one set of the counter circuit 5 and the D / A converter 6 is required for the entire chip.

In such a configuration, the A / D for the upper bit
Simultaneously with the operation of the converter 2, the differential data for the lower bit A / D converter 3 is detected, and the lower bit A / D converter is processed after a fixed time after the completion of the upper bit A / D conversion. . At this time, after the upper-bit A / D conversion processing, the upper-bit A / D-converted digital data is D / A-converted and the difference from the input analog signal is not detected.

That is, the A / D conversion method by this converter is as follows.
Performing a first A / D conversion step for coarsely A / D conversion and a second A / D conversion step for fine A / D conversion;
A / D for converting input analog signal to digital data
This is a conversion method in which a difference signal between a conversion result at the end of conversion in the first A / D conversion step and an input analog signal is set as a conversion target in the second A / D conversion step. That is, since the detected difference data is directly subjected to A / D conversion of the lower bits, the A / D conversion for the upper bits is completed after the A / D conversion processing for the upper bits is completed.
The D / A conversion is performed on the D conversion data, and the difference between the analog input signal and the A / D conversion data for upper bits is not detected. Therefore, the A / D conversion processing for the lower bits can be performed a predetermined time after the A / D conversion processing for the upper bits is completed, and the processing time required for the A / D conversion can be reduced.

A more specific A / D conversion method is as follows. That is, an input analog signal to be converted to digital data is sequentially compared with an analog signal corresponding to reference digital data whose value sequentially changes, and the difference data between the input analog signal and the analog signal corresponding to the reference digital data is calculated. Then, the difference data at the time when the content of the comparison result changes is converted into digital data, and the reference digital data at the time of the change and the result of the conversion are combined.

The present A / D converter has an A
The / D converter 2 and the A / D converter 3 for lower bits have a circuit configuration that shares at least a counter and a D / A converter. As described above, an A / D converter capable of high speed, high resolution, and downsizing can be realized. As will be described later, a comparator for A / D conversion, a latch control circuit, and a latch circuit for digital data can be shared.

The operation of the A / D converter having such a configuration will be described with reference to FIGS. FIG.
FIG. 6 is a waveform chart showing the operation of the D converter. FIG. 3 shows A /
It is a schematic diagram which shows operation | movement of a D converter. 2 and 3, there is no limitation on the number of bits for A / D conversion, but for simplicity of description here, A / D
Each of the D conversion unit 2 and the A / D conversion unit 3 for lower bits has a bit number of 3 bits and a total of 6 bits is shown. Further, the analog input signal is sent to the S / H circuit 11
The / H signal is shown as the amplitude V0 of the negative polarity.

The signal S1 is supplied to the A / D converter 2 for the upper bit.
And a signal for switching the operation of the A / D converter 3 for lower bits. If the count number of the counter 5 is 8 (binary "11
1 "), the level is switched between the H level and the L level, and is at the H level when the A / D converter 2 for the upper bit operates and at the L level when the A / D converter 3 for the lower bit operates. .

The signal S2 is a control signal φS / H for sampling and holding the analog input signal. When the control signal φS / H is at the L level, the analog input signal is sampled and held, and after changing to the H level, the counter 5 starts counting.

The signal S3 is the clock signal CLK in FIG.
It is.

The signal S4 is digital data output from the counter circuit 5. The counter circuit 5 counts up eight clocks from "000" to "111", and outputs the count result as digital data. Further, in this example, after “111”, the counting operation is stopped for three clock periods, and thereafter, from “000” to “11” again.
The 8 clocks up to "1" are counted up. Thereafter, the same operation is repeated. Here, “000” to “1”
After up-counting eight clocks up to "11", the counter circuit 5 stops counting for three clock periods. However, this suspension period is not limited to three clocks, but may be any number of clocks.

The signal S5 is an analog signal output from the S / H circuit 7, and is sampled and held at the timing of the signal S2. Here, the analog signal output from the S / H circuit 7 has a negative polarity and an amplitude of V0.

The signal S6 is the output of the comparator 8. FIG.
At time t5 (see FIG. 2) when the signal S4 from the counter 5 becomes "100",
The output amplitude of the A converter 6 becomes larger than the signal S5, and the output signal S6 of the comparator 8 changes from the H level to the L level (hereinafter, abbreviated as “H → L”). The control signal T
The period when G1 is at the L level has no effect on the operation and can be ignored.

The signal S7 is a latch control signal for the upper-bit latch circuit 9. When the signal S7 is at the L level, the upper bit latch circuit 9 performs a latch operation, and holds and outputs the input data when the signal changes from H to L. On the other hand, in the state where the data is fixed at the H level, the data does not change.
The signal S7 is processed by the control signals TG1, the clock CLK (signal S3) and the signal S6 by the inverters 15, 21 and the gates 16, 19, so that the signal S6 becomes low.
When the level becomes (the amplitude of the D / A converter output becomes larger than the signal S5), the level does not become L level. Therefore, the digital data “011” one clock before that is latched by the upper-bit latch circuit 9.

The signal S8 is digital data output from the upper-bit latch circuit 9. By the signal S7, the signal S
Digital data “011” one clock before the signal 6 becomes L level is latched by the latch circuit 9. The digital data "011" is the data of the upper bits of the A / D converter, and corresponds to the analog voltage V1 shown in FIG.

The signal S9 is analog data output from the difference detector 10. This signal S9 indicates the difference between the output signal S5 of the S / H circuit 7 and the output signal of the D / A converter 6. Note that the operation of the difference detector 10 is based on A
This is performed simultaneously during the operation of the / D conversion unit 2.

The signal S10 is an output signal of the S / H circuit 11. Since the control signal of the S / H circuit 11 is the signal S7, after the time t5 (see FIG. 2), the input analog voltage V
An analog voltage V2 which is a difference between 0 and an analog voltage V1 which is a result of the A / D conversion for the upper bits is continuously output.

The signal S11 is the output of the comparator 13.
As shown in FIG. 3, the signal S4 from the counter 5
At time t15 (see FIG. 2) at which the signal becomes "011", the output amplitude of the D / A converter 6 attenuated by the amplifier circuit 12 becomes larger than the signal S10, and the output signal S11 of the comparator 13 becomes H → Changes to L. The control signal T
The period when G1 is at the H level has no effect on the operation and can be ignored.

The signal S12 is the low-order bit latch circuit 1
4 is a latch control signal. When the signal S12 is at L level, the lower bit latch circuit 14 performs a latch operation,
Holds and outputs input data when H → L changes. On the other hand, in the state where the data is fixed at the H level, the data does not change. The signal S12 is obtained by processing the control signal TG1, the clock CLK (signal S3) and the signal S10 by the inverter 17 and the gates 18 and 20, thereby obtaining the signal S12.
When 11 goes low, it does not go low. Therefore, the digital data “01” one clock before that,
"0" is latched by the lower bit latch circuit 14.

The signal S13 is the lower bit latch circuit 1
4 is the output digital data. By the signal S12,
Digital data “010” one clock before the signal S 11 becomes L level is latched by the latch circuit 14. This digital data "010" is the lower bit data of the A / D converter, and corresponds to the analog voltage V2 shown in FIG.

The digital output signal S14 is digital data output from the bit synthesizing circuit 4.

In this configuration, at time t20 when the latch control data obtained by inverting the control signal TG1 by the inverter 22 becomes L level, the signal S8, which is the output data of the upper bit latch circuit 9, and the lower bit latch circuit 14
The signal S13 which is the output data of the bit synthesizing circuit 4
Latched. In addition, without using the bit synthesis circuit 4,
If the output data of the upper bit latch circuit 9 and the lower bit latch circuit 14 are used during the period from time t15 to time t20, the same result as the output data of the bit synthesis circuit 4 can be obtained. In addition, inverters 15 and 1
Each of the logic circuits using the gates 7, 21, and 22 and the gates 16, 18, 19, and 20 is not limited to the configuration shown in FIG. 1, but the signal S7 and the signal S7 shown in FIG.
As long as 12 is obtained, a logic circuit having another configuration may be used.

As shown in FIG. 3, while "011" is latched as an upper bit and "010" is latched as a lower bit, a time corresponding to the number of clocks from "000" to "111" is obtained. The time required for resetting the circuit, etc.
Again, the time obtained by adding the time corresponding to the number of clocks from “000” to “111” is the time required for one A / D conversion. Specifically, time T1, time T2, time T3
Is the total time. Therefore, the number of clocks 2
It takes ³ + 3 + 2 ³ time corresponding to.

Here, the timing at which data is output from the bit synthesizing circuit 4 in FIG. 1 will be described with reference to FIG. FIG. 4 shows the signals TG1, S7, S8,
In addition to S12, S13, and S14, the contents (upper bits and lower bits) of the bit combining circuit 4 in FIG. 1 are shown. In the figure, during a period A in which the signal TG1 is at the H level, the upper bit data is
Can be latched. In the period B in which the signal TG1 is at the L level, the lower bit data can be latched by the lower bit latch circuit 14.

The signal S8 is in a transient state at the beginning, and at time t4
"011" is latched in the upper-bit latch circuit 9 at the falling timing of. The signal S13 is also in a transient state at first, but “010” is latched by the lower-bit latch circuit 14 at the falling timing at the time t14. Therefore, in the period C, the upper bit data is output as the signal S8 and the lower bit data is output as the signal S13.

At time t20, "011" of the upper-bit latch circuit 9 and "010" of the lower-bit latch circuit 14 are latched by the bit synthesizing circuit 4. Therefore, the bit synthesizing circuit 4 outputs “011010”
Is output.

Since the signal TG1 repeats the H-level period A and the L-level period B alternately thereafter, A / D conversion is continuously performed by the same operation as described above.

Returning to FIG. 1, the present A / D converter shares at least the counter and the D / A converter in the A / D conversion for the upper bits and the A / D conversion for the lower bits, so that the circuit scale is large. Can be reduced, and the on-chip implementation becomes easy.

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a block diagram showing a configuration of the A / D converter according to the second embodiment of the present invention.
In the figure, the same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description of those parts will be omitted.

In the figure, the A / D converter according to the present embodiment includes an S / H circuit 7 for sampling and holding an analog input signal, a counter circuit 5 for counting the number of clocks from a clock circuit, A digital-to-analog (D / A) converter 6 that receives digital data output from the circuit 5 and outputs analog data whose signal amplitude monotonically increases in accordance with a change in the value, and a switch 124 whose connection state is switched by a control signal TG1. An A / D converter 102 for sequentially converting upper bits and lower bits of target digital data, a difference detection circuit 10, an S / H
The circuit includes a circuit 11 and a bit combining circuit 4 that combines upper bits and lower bits to generate N-bit digital data.

The A / D converter 102 includes a comparator 8, an inverter 15 receiving the output of the comparator 8, and an OR gate 16 receiving the output and the control signal TG1.
In response to this output, a latch operation is performed, and latch circuit 109 using digital data from counter 5 as input data.
Consists of As will be described later, similarly, when a plurality of analog signals from the sensors and the like are simultaneously output and an A / D converter is provided for each column of the sensor, an area 101 indicated by a broken line is formed for each column. Shall be performed. on the other hand,
The counter circuit 5 and the D / A converter 6 have 1
Only a pair need be formed.

In such a configuration, first, the switch 124 is connected to the terminal A, and the output of the S / H circuit 7 and the D /
By comparing the magnitude with the output of the A converter 6, the A / D
The conversion unit 102 operates as an A / D conversion unit for upper bits in FIG. 1 and performs coarse A / D conversion. At the same time, difference detection is performed by the difference detection circuit 10 and the S / H circuit 11.
Next, the switch 124 is connected to the terminal B, and compares the magnitude of the output of the difference detection circuit 10 with the magnitude of the output of the amplifier circuit 12 in which the output of the D / A converter 6 is attenuated.
Operate as an A / D conversion unit for lower bits of. Finally, the bit synthesizing circuit 4 latches the A / D conversion result in the upper bit latch at the end of the upper bit A / D conversion by the control signal TG1. Similarly, at the end of the lower bit A / D conversion, the A / D conversion is performed. Latch the D conversion result. With the above operation, N-bit digital data is generated and held.

This A / D converter is characterized in that the comparator 13, the inverter 17, and the O / D converter of the A / D converter 3 for lower bits in FIG.
The R gate 18 and the lower bit latch 14 are connected to the switch 1
24 is shared with the A / D converter 2 for the upper bits. For this reason, the circuit scale of the A / D converter can be reduced.

Here, the timing at which data is output from bit combination circuit 4 in FIG. 5 will be described with reference to FIG. FIG. 6 shows, in addition to the signal TG1 in FIG. 5, the output of the latch circuit 109, the contents (upper bits and lower bits) of the bit synthesizing circuit 4 in FIG. In the figure, during the period A in which the signal TG1 is at the H level, the upper bit data
9 can be latched. In the period B in which the signal TG1 is at the L level, the lower bit data is
9 can be latched.

The output of the latch circuit 109 is initially in a transient state, and after "011" is latched as in the case of FIG. 4, it is latched by the bit synthesizing circuit 4 as an upper bit at the falling timing of the signal TG1. Thereafter, the output of the latch circuit 109 is again in a transient state, and "010" is latched in the same manner as in FIG. 4, and then latched by the bit synthesizing circuit 4 as a lower bit at the rising timing of the signal TG1.

Therefore, during the period from the rising timing of signal TG1 at which "010" is latched to the next falling timing, correct data "011010" is output from bit synthesizing circuit 4.

In this embodiment, since the comparator, the latch control circuit and the latch circuit for digital data are also used in common, the circuit can be made smaller than in the case of FIG. 1 and more suitable for on-chip implementation. An A / D converter can be realized.

Next, a third embodiment of the present invention will be described with reference to the drawings. FIG. 7 is a block diagram showing a configuration of an A / D converter according to the third embodiment of the present invention. In the figure, the same parts as those in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description of those parts will be omitted.

FIG. 7 shows a sensor unit 30 having pixels 31-11 to 31 -NM arranged two-dimensionally (N rows × M columns).
1 shows a configuration example of an A / D converter connected to a sensor unit from which pixel signals for each row are simultaneously output. The areas 1a, 1b,..., 1n indicated by broken lines in the figure correspond to the area 1 of the A / D converter in FIG. 1 according to the first embodiment described above. Each of these areas has A / A
.. And a lower bit A / D converter 3
, and bit combination circuits 4a, 4b,..., respectively, and each pixel column (31-11-31-N1,.
-1M to 31-NM). Note that only one set of the counter circuit 5 and the D / A converter 6 is formed.

As shown in the figure, only one set of the counter circuit 5 and the D / A converter 6 is formed, and the A / D converter for the upper bit and the A / D for the lower bit are provided for each pixel column. By forming a circuit including only the conversion unit and the bit synthesizing circuit, it is not necessary to incorporate many counter circuits and D / A converters as in the conventional example, and the circuit scale can be reduced. Therefore, a high-resolution A / D converter can be realized without increasing the circuit scale, and it can be implemented on-chip. Further, although not shown in FIG.
In 1b, if the A / D converter shown in FIG. 5 of the second embodiment described above is used, the circuit scale can be further reduced, which is more suitable for on-chip implementation.

Here, when the signal outputs of the sensors and the like are output simultaneously for one row and A / D conversion is required for each signal, an A / D converter is formed for each column. General. Even in such a case, in this embodiment, it is only necessary to provide only one set of counters and D / A converters for all A / D converters. Therefore, the circuit scale can be reduced, and the on-chip integration of the sensor unit 30 and the regions 1a, 1b,. further,
The comparator, the latch control circuit, and the latch circuit for digital data can be shared, and the circuit scale can be reduced and the on-chip implementation can be facilitated.

The above is a description of a CCD (Charge Couple).
ed Device) and the like, the case of a sensor having a plurality of pixels has been described. However, the present invention is not limited to this, and the present invention can be widely applied to other two-dimensional sensors including sensor elements arranged and arranged in N rows and M columns. Is clear.

In the case of a two-dimensional sensor, one A / D converter is provided in common for a plurality of arbitrary sensor element rows, and output signals from each sensor element are time-divided by a switch or the like. A / D conversion may be performed by switching and connecting to the A / D converter. With such a configuration, the number of circuits of the A / D converter can be reduced, so that the circuit size can be reduced and the power consumption can be reduced. When one A / D converter is connected to one sensor element row, the outputs of the sensor elements included in the sensor element row are sequentially connected to the A / D converter. Are sequentially A / D converted. The order of the A / D conversion may be random or every other row (for example, odd-numbered rows and even-numbered rows are alternately performed for a plurality of rows).

Further, different from the above-described direct A / D conversion of a pixel signal, a readout circuit formed at a rate of one for each pixel column or a plurality of predetermined pixel columns to which a pixel signal is input. The above-described A / D conversion can be performed on an output signal of a circuit having a function such as a bias component removal circuit, a filter circuit, an integration circuit, or an amplification circuit.
With such a configuration, unnecessary components (bias components, noise, and the like) included in the pixel signal can be removed, and only effective components can be A / D converted. For example, CCD
By subtracting the reset level voltage from the output signal of the sensor, only the effective level can be extracted.
Further, processing after the A / D converter becomes easy.

As described above, A / D conversion for upper bits (bit number P) for coarse A / D conversion and A / D conversion for lower bits (bit number Q) for fine A / D conversion are performed. As a result, the number of counts required for A / D conversion can be reduced. More specifically, what was conventionally 2 ^N pieces can be reduced to (2 ^P +2 ^Q ) pieces.

Further, since the differential data for the lower bit A / D converter is detected simultaneously with the operation of the upper bit A / D converter, the conventional data is processed after the upper bit A / D converter processing is completed. Without performing D / A conversion on the A / D conversion data for the upper bits of the data. Further, since the number of bits of the A / D conversion for the upper bit and the A / D conversion for the lower bit is determined so that the count number required for the A / D conversion is minimized, the conversion required for the A / D conversion is performed. Time is minimized. From the above, a high-speed and high-resolution A / D converter with a low clock frequency can be realized.

Furthermore, since the A / D converter for the upper bits and the A / D converter for the lower bits share at least a counter and a D / A converter, pixels are formed in parallel for each column. A /
Even when performing D conversion, it is possible to realize an A / D converter suitable for downsizing the circuit scale and on-chip. In addition, a comparator,
The latch control circuit and the digital data latch circuit can be shared, and an A / D converter suitable for further downsizing of the circuit scale and on-chip implementation can be realized.

The present invention can take the following aspects in connection with the description of the claims.

(1) The A / D converter according to claim 2, wherein said holding means is a sample and hold circuit which samples and holds the output of said difference detecting means at the time of said change.

(2) The A / D converter according to claim 5, wherein the counter performs a counting operation in accordance with an externally input clock and outputs the count value as the reference digital data. .

[0085]

As described above, the present invention performs A / D conversion for upper bits for coarse A / D conversion and A / D conversion for lower bits for fine A / D conversion. By synthesizing the conversion results, the number of counts required for A / D conversion can be reduced, the conversion time required for A / D conversion is minimized, and a low clock frequency, high speed and high resolution A / D converter is used. There is an effect that can be realized. Also, an A / D converter for upper bits and an A / D converter for lower bits
Since the conversion unit shares at least the counter and the D / A converter, the circuit scale is also used when performing A / D conversion after signal output from a sensor or the like in which pixels are formed in parallel for each column. A / suitable for miniaturization and on-chip
There is an effect that a D converter can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an A / D converter according to a first embodiment of the present invention.

FIG. 2 is a waveform chart showing the operation of each part of the A / D converter of FIG.

FIG. 3 is a schematic diagram showing an operation of the A / D converter of FIG. 1;

FIG. 4 is a diagram showing a timing at which data is output from the bit synthesizing circuit in FIG. 1;

FIG. 5 is a diagram illustrating a configuration of an A / D converter according to a second embodiment of the present invention.

6 is a diagram showing a timing at which data is output from the bit synthesizing circuit in FIG. 5;

FIG. 7 is a diagram illustrating a configuration of an A / D converter according to a third embodiment of the present invention.

FIG. 8 is a diagram showing a configuration of a conventional example of a single slope type A / D converter.

FIG. 9 is a schematic diagram showing an operation of a conventional example.

FIG. 10 is a configuration diagram of a conventional high-resolution A / D converter.

[Explanation of symbols]

 2, 2a, 2b ... A / D converters for upper bits 3, 3a, 3b ... A / D converters for lower bits 4, 4a, 4b ... Bit synthesis circuit 5 Counter circuit 6 D / A converter 7, 11 S / H circuit 8, 13 Comparator 9 Upper bit latch circuit 10 Difference detection circuit 12 Amplifier circuit 14 Lower bit latch circuit

Claims (9)

(57) [Claims] A first comparing means for sequentially comparing an input analog signal to be converted into digital data with an analog signal corresponding to reference digital data whose value sequentially changes, and a comparison result of the first comparing means. A first A / D converter for latching the reference digital data at the time when the content has changed, a first A / D converter for outputting the latched data as a conversion result, and the input analog signal A second analog-to-digital (A / D) converter for constantly outputting a difference between the analog signal corresponding to the reference digital data and an analog signal corresponding to the reference digital data. And a converted digital signal obtained by combining the output of the first A / D converter and the output of the second A / D converter and converting the input analog signal. Including a combining means for outputting as Rudeta
Only, the second A / D conversion unit performs the conversion at the time of the change.
Holding means for holding the output of the difference detecting means;
An analog signal equivalent to digital data
Is the minimum resolution of the first A / D converter.
Attenuator that attenuates the output to equal the size of
A step, a holding content of the holding means, and an output of the damping means.
Second comparing means for sequentially comparing
The reference at the time when the content of the comparison result changes
Second latch means for latching digital data.
And outputs the latched data as a conversion result.
An A / D converter. 2. The input / output converter according to claim 1, wherein
The log signal is converted to P-bit (P is a positive integer) digital data.
And the second A / D converter is connected to the holding unit.
The held contents are Q-bit (Q is a positive integer) digital data.
And the synthesizing means converts the data into N bits (N = P + Q).
2. The digital data output device according to claim 1, wherein the digital data is output.
The A / D converter according to claim. 3. The first A / D converter according to claim 1 , wherein
The output of the second A / D converter is set as the upper bit of the output of the second A / D converter.
The power is combined as lower bits.
The A / D converter according to any one of claims 1 to 2 . 4. A power supply for generating the reference digital data.
And counter, the reference digital de which is the output of the counter
D / A conversion means for converting the data into an analog signal.
And conversion by the input analog signal and D / A conversion means.
The difference from the converted analog signal is always determined from the difference detection means.
The A / D converter according to claim 1, wherein the A / D converter outputs the signal. 5. An apparatus according to claim 1, wherein said input analog signal and said holding means are connected to each other.
First switch means for selectively outputting the held content;
An analog signal corresponding to the reference digital data and
A second switch for selectively outputting the output of the attenuation means
Means and an output from said first and second switch means.
Corresponding to the input analog signal and the reference digital data.
Comparison operation for comparing an analog signal corresponding to the
And the holding content of the holding means and the output of the damping means
Perform one of the second comparison operations for comparing
The content of the comparison result of the shared comparison circuit and the shared comparison circuit is
The reference digital data at the time of the change
A shared latch circuit for latching, and the shared comparison circuit
Are used as the first comparing means and the second comparing means.
The shared latch circuit is connected to the first latch means and the first latch means.
5. The A / D converter according to claim 2 , wherein the A / D converter is used as a second latch means . 6. N rows (N is a positive integer, the same applies hereinafter) and M rows
Arranged and arranged in columns (M is an integer of 2 or more, the same applies hereinafter)
The output signal of the two-dimensional sensor consisting of
A / D converter for converting digital data into digital data
Item 6. The A / D converter according to any one of Items 1 to 5,
To the sensor element group is one-to-one correspondence with A / D converter, characterized in that provided. 7. Sensors arranged and arranged in N rows and M columns.
Digital output signal of a two-dimensional sensor consisting of
An A / D converter for converting data into data, wherein:
5. The A / D converter according to claim 5,
Provided in common for a plurality of columns in the
A / D converter provided for the plurality of rows of sensor element groups
A / D characterized by connecting in a time-sharing manner
Conversion device. 8. A one-line converter provided for the A / D converter.
The N sensor elements constituting the sensor element group are referred to as A /
JP that it has to be connected to the time division with respect to D converter
The A / D converter according to claim 6 or 7, wherein 9. The A / D according to claim 1,
The converter is integrated into one chip together with the two-dimensional sensor.
A / D converter characterized by the above-mentioned .