CN107799503B - 具有mim电容器的半导体器件 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 91
- 239000003990 capacitor Substances 0.000 title claims abstract description 58
- 229910052751 metal Inorganic materials 0.000 claims abstract description 46
- 239000002184 metal Substances 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 239000010931 gold Substances 0.000 claims description 18
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 9
- 229910052737 gold Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 238000005530 etching Methods 0.000 abstract description 16
- 230000015572 biosynthetic process Effects 0.000 abstract description 6
- 230000008021 deposition Effects 0.000 abstract description 2
- 239000000463 material Substances 0.000 description 12
- 238000000034 method Methods 0.000 description 12
- 239000010936 titanium Substances 0.000 description 12
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 229910052719 titanium Inorganic materials 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 5
- 229910002601 GaN Inorganic materials 0.000 description 4
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 2
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- 229910010272 inorganic material Inorganic materials 0.000 description 2
- 239000011147 inorganic material Substances 0.000 description 2
- 238000001883 metal evaporation Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- AJGDITRVXRPLBY-UHFFFAOYSA-N aluminum indium Chemical compound [Al].[In] AJGDITRVXRPLBY-UHFFFAOYSA-N 0.000 description 1
- NWAIGJYBQQYSPW-UHFFFAOYSA-N azanylidyneindigane Chemical compound [In]#N NWAIGJYBQQYSPW-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000012777 electrically insulating material Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- JMOHEPRYPIIZQU-UHFFFAOYSA-N oxygen(2-);tantalum(2+) Chemical compound [O-2].[Ta+2] JMOHEPRYPIIZQU-UHFFFAOYSA-N 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 239000007779 soft material Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
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Abstract
本申请公开了具有MIM电容器的半导体器件。一种半导体器件,其设置有电连接至金属层的焊盘和连接至焊盘的电容器。半导体器件在电容器的下电极与焊盘之间设置有绝缘膜。由于绝缘膜保护并隔离下电极而免受衬底过孔的蚀刻和过孔金属的沉积的影响,因此在形成过孔和过孔金属期间下电极不会引起空隙或间隙。
Description
相关申请的交叉引用
本申请要求于2016年8月30日提交的日本专利申请NO.2016-168569的优先权的权益,其通过引用合并于此。
技术领域
本发明涉及一种半导体器件,具体地,本发明涉及金属绝缘体金属(MIM)型电容器与衬底过孔之间的位置关系。
背景技术
金属绝缘体金属(MIM)型电容器可内置于单片微波集成电路(MMIC)中,在该单片微波集成电路中,MIM电容器包括下电极、绝缘膜和上电极。日本专利特开NO.2008-078547A公开了如下技术:将扩散保护层堆叠在介电层上的内置电容器埋置于衬底内并且通过过孔电连接至互连部。
当半导体衬底设置有填充有金属的过孔和在衬底的顶表面上的电极并且电极电连接至过孔时,在电容器和过孔并排布置的情况下衬底的尺寸不可避免地会扩大。另一方面,当电容器与过孔重叠时,电容器中的电介质可能随着过孔的变形而变形,这降低了电容器的击穿电压。
发明内容
本发明的一方面涉及一种半导体器件,其设置有衬底、半导体层、焊盘、第一绝缘膜和电容器。半导体层设置在衬底上。衬底和半导体层设置有穿过衬底和半导体层的过孔。过孔中设置有过孔金属。设置在半导体层上的焊盘完全覆盖过孔并且与过孔金属连接。第一绝缘膜覆盖焊盘。从第一绝缘膜的一侧起按顺序包括下电极、第二绝缘膜和上电极的电容器设置在第一绝缘膜上。本半导体器件的特征是第
一绝缘膜夹置于焊盘与电容器的下电极之间。
附图说明
根据以下参照附图对本发明的优选实施例的详细描述,将更好地理解上述和其他目的、方面和优点,在附图中:
图1A是示出根据本发明的第一实施例的半导体器件的平面图,以及图1B示出了沿着图1A中所示的线Ib-Ib截取的截面图;
图2A至图2H示出了根据本发明的第一实施例的形成图1A所示的半导体器件的处理;
图3A是示出与本发明相比较的半导体器件的平面图,以及图3B示出了沿着图3A所示的线IIIb-IIIb截取的截面图;
图4A是示出又一半导体器件的平面图,图4B示出了沿着图4A所示的线IVb-IVb截取的半导体器件的截面图,以及图4C还示出了焊盘有故障的半导体器件的截面图;
图5A是根据本发明的第二实施例的半导体器件的平面图,以及图5B示出了沿着图5A中所示的线Vb-Vb截取的截面图;以及
图6A是根据本发明的第三实施例的半导体器件的平面图,以及图6B示出了沿着图6A所示的线VIb-VIb截取的截面图。
具体实施方式
接下来,将参照附图来描述根据本发明的优选实施例。在描述附图时,彼此相似或相同的标记或符号指的是彼此相同或相似的元件,而无需重复说明。
第一实施例
图1A是示出根据本发明的第一实施例的半导体器件的平面图,以及图1B示出了沿着图1A所示的线Ib-Ib截取的截面图。半导体器件100设置有过孔10a、电容器26、可以称为第一金属层的焊盘28、以及可以称为第一绝缘膜的另一绝缘膜40,其中,这些元件10a至40沿着与衬底10正交的方向重叠。
如图1B所示那样在其上设置有半导体层11的衬底10可以由电绝缘材料制成,该电绝缘材料通常为碳化硅(SiC)、蓝宝石(Al2O3)等。半导体层11包括由镓氮化物(GaN)制成的沟道层、由铝镓氮化物(AlGaN)制成的阻挡层或其它层。衬底10和半导体层11的总厚度可以为约100μm。半导体层11可以例如形成电连接至互连部的场效应晶体管(FET),该互连部可以是微带线。电容器26连接在该互连部与地之间。
衬底10和半导体层11设置有从衬底10的底面贯穿至半导体层11的顶表面的过孔10a,其中,过孔10a的直径为约100μm。在过孔10a的侧壁设置有金属层,该金属层从侧壁延伸到衬底10的整个底面,该金属层可以称为金属层16。可以作为FET和微带线的地使用的金属层16由厚度为5μm至10μm的金(Au)制成。过孔10a也设置有过孔电极18,其可以通过电镀来形成以填充金属层16上的整个过孔10a。过孔电极18可以由铜(Cu)制成。
面积比电容器26的下电极20大的焊盘28设置在半导体层11和过孔10a上。即,焊盘28覆盖整个过孔10a。焊盘28与金属层16直接接触,即,焊盘28电连接至过孔电极18和金属层16。焊盘28可以由厚度为50nm的镍(Ni)和厚度为500nm的金(Au)的堆叠金属制成。由例如硅氮化物(SiN)制成的绝缘膜12设置在焊盘28上。
可以在绝缘膜12上设置第一绝缘膜40,以使得第一绝缘膜40与焊盘28和过孔10a完全重叠。第一绝缘膜40可以由厚度为200nm的硅氧化物(SiO)、硅氮化物(SiN)和硅氧氮化物(SixOyNz,0<x<1,0<y<1,0<z<1)之一制成。
电容器26的下电极20设置在第一绝缘膜40上。第二绝缘膜22设置在下电极20的侧面和顶部。即,第二绝缘膜22覆盖下电极20的侧面和顶部。上电极24设置在第二绝缘膜22上以与下电极20和过孔10a完全重叠。下电极20、第二绝缘膜22和上电极24构成金属绝缘体金属(MIM)型的电容器26。下电极20、第二绝缘膜22和上电极24重叠的区域位于焊盘28内但覆盖整个过孔10a。下电极20和上电极24由厚度为10nm的钛(Ti)、厚度为200nm的金(Au)和厚度为50nm的其他钛(Ti)的堆叠金属制成。下电极的宽度为例如155μm,而上电极24的宽度为150μm。第二绝缘膜22可以由厚度为200nm的硅氮化物制成。
可以由厚度为50nm至100nm的硅氮化物(SiN)制成的又一绝缘膜14覆盖绝缘膜12、第二绝缘膜22和上电极24的顶部。绝缘膜14设置有在上电极24上的开口,上电极24的顶部通过该开口暴露。设置在绝缘膜14上的互连部30与上电极14直接接触。因此,上电极24可通过互连部30电连接至例如衬底10上的传输线,即,电容器26可以连接至传输线和/或通过传输线连接至如FET的有源器件。
绝缘膜12和14设置有在焊盘28上但在下电极20外部的另一开口13,焊盘28的顶部通过该另一开口13暴露。此外,绝缘膜12和14设置有在下电极20上但在上电极24外部的又一开口23,其中,下电极20的顶部通过该又一开口23暴露。互连部32可以通过这些开口13和23将下电极20与焊盘28电连接。因而,下电极20可以通过互连部32和焊盘28连接至金属层16或者过孔10a中的过孔电极18。
图2A至图2H示出了形成半导体器件100的处理。如图2A所示,首先在衬底10上生长半导体层11,然后,伴随随后的剥离技术的金属蒸镀或者伴随随后的蚀刻的喷镀可以将焊盘28形成在半导体层11上。此后,化学气相沉积(CVD)技术等可以将绝缘膜12沉积在焊盘28上,此外,如图2B所示,CVD技术等可以将第一绝缘膜40沉积在前一绝缘膜12上。
此后,伴随剥离技术的金属蒸镀或者伴随蚀刻的喷镀可以形成下电极20。CVD可以沉积第二绝缘膜22以覆盖下电极20的顶部和侧面以及从下电极20暴露的第一绝缘膜40的顶部。然后,伴随剥离技术的金属蒸镀或者伴随蚀刻的喷镀可将上电极24形成在第二绝缘膜22上以与下电极20重叠。因此,包括下电极20、第二绝缘膜22和上电极24的电容器26可以形成在第一绝缘膜40上,如图2C所示。
此后,蚀刻可以部分地去除第二绝缘膜22和第一绝缘膜40以留出第二绝缘膜22的覆盖下电极20的侧面的一部分以及第一绝缘膜40的在下电极20和第二绝缘膜22下面的一部分,如图2D所示。然后,如图2E所示,CVD可以沉积绝缘膜14以覆盖整个衬底10;即,绝缘膜14覆盖从电容器26暴露的绝缘膜12以及电容器26的顶部和侧面。
此后,如图2F所示,蚀刻可以在绝缘膜14、第二绝缘膜22和绝缘膜12中形成开口13、15和23。由于这些绝缘膜12、14和22由含硅(Si)的无机材料制成,因此利用含氟(F)的活性气体的蚀刻可以蚀刻这些绝缘膜12、14和22,而无需更换蚀刻气体。此外,由于金属层存在于这些绝缘膜12、14和22下面,即,上电极24在绝缘膜14下面,下电极20在绝缘膜14和22下面,并且焊盘28在绝缘膜12和14下面;对于这些绝缘膜12、14和22的蚀刻可以安全地停止在金属层24、20和28处。如图2G所示,在形成开口13、15和23之后,金属电镀等可形成互连部30和32,以与上电极24、下电极20和焊盘28接触。
此后,该处理通过从衬底10的底面对其进行研磨来使衬底10变薄以使包括半导体层11的其总厚度为约100μm。然后,形成过孔10a以使其穿过衬底10和半导体层11。即,从衬底10的底面到焊盘28的蚀刻可以形成过孔10a。焊盘28的底面暴露在过孔10a的底部内。金属蒸镀等可以形成金属层16以覆盖过孔10a的底部和侧面以及衬底10的整个底面。然后,如图2H所示,使用金属层16作为种子金属的电镀可以在过孔10a内形成过孔电极18。由此,完成了形成具有电容器26的半导体器件100的处理。
图3A是示出与本发明相比较的半导体器件100R的平面图,以及图3B示出了沿着图3A所示的线IIIb-IIIb截取的截面图。半导体器件100R具有并排布置在衬底10上的电容器26和焊盘28R。焊盘28R与过孔电极18重叠。因此,虽然电容器26(尤其是其下电极20)可以不用进行形成过孔10a的处理即,衬底10和半导体层11的蚀刻基本上对电容器26的下电极20没有任何影响,但是电容器26的包括焊盘28的区域不可避免地变得更宽。
图4A是示出又一半导体器件的平面图,图4B示出了沿着图4A所示的线IVb-IVb截取的半导体器件的截面图,以及图4C还示出了焊盘有故障的半导体器件的截面图。如图4A和图4B所示,半导体器件200R中的电容器26与过孔电极18重叠,并且电容器26的下电极20与过孔10a中的金属层16直接接触。因此,电容器26的下电极20起到上述半导体器件中的焊盘28的作用。由于电容器26与过孔电极18重叠,因此与上述最后说明的半导体器件100R相比,半导体器件200R可以节省其在衬底10上的区域。
然而,可能使下电极20变形的包括对衬底10和半导体层11的硬蚀刻的形成过孔10a的处理和/或随后对金属层16和过孔电极18执行的热处理可能引起下电极20的故障,这使留在过孔10a内的清洁溶剂或电镀液扩大。因此,下电极20可能在与金属层16的界面内引起空隙20a,并且这些空隙可能在绝缘膜22中反映为减小绝缘膜22的有效厚度的突起22a。因此,降低了电容器26的击穿电压。
本实施例的半导体器件100设置有与过孔电极18重叠的焊盘28,并且第一绝缘膜40也与焊盘28和过孔电极18这两者重叠。需要焊盘28针对衬底10和半导体层11的半导体材料的蚀刻选择性与针对金属层16的降低的接触电阻相兼容。金(Au)是用于焊盘28的典型金属。然而,金(Au)是用于抑制产生空隙20a和22a的相对软质的材料。因此,本实施例的半导体器件100在焊盘28上设置由硬质材料制成的第一绝缘膜40以增强焊盘28的刚度。
第一绝缘膜40可以由硅氧化物(SiO)、钛(Ti)等制成,但从可加工性的角度而言,硅氧化物(SiO)是优选的。为了防止空隙,更厚地形成的硬质材料是优选的;例如,厚度大于500nm的硬质材料是优选的。钛(Ti)可以以大于500nm的厚度沉积,但在随后的处理中很难被蚀刻。因此,当半导体器件设置有在焊盘28与下电极之间的由钛(Ti)制成的材料时,钛膜(Ti)有必要形成得更薄。因此,用于抑制空隙20a和22a的、置于下电极20与焊盘28之间的材料优选地由硅氧化物(SiO)制成。由于由硅氧化物(SiO)制成的第一绝缘膜40覆盖焊盘28(至少与过孔电极18重叠的区域),因此可以防止焊盘28引起空隙。相应地,下电极20基本上没有引起空隙20a,第二绝缘膜22也没有引起空隙。
由于第一绝缘膜40置于下电极20与焊盘28之间,因此需要将下电极20与焊盘28连接的附加互连部32。本实施例的半导体器件100设置有将下电极20的顶部通过开口23与焊盘28的顶部通过开口13相连接的互连部32。下电极28需要延伸以形成开口23,并且焊盘28也需要延伸以在电容器26的侧面形成开口13,这加宽了半导体器件100在衬底10上占据的区域。然而,电容器26本身与过孔电极18和焊盘28重叠,下电极20和焊盘28的延伸是受限制的。因此,半导体器件100可以抑制衬底10的平面尺寸,而不会降低电容器26的击穿电压。
第一绝缘膜40可以是含的硅的无机材料,诸如硅氧化物(SiOx)、硅氮化物(SiNx)、硅氮氧化物(SiON)等。这些材料具有足够的刚度以有效地防止在形成过孔10a和过孔电极18期间焊盘28的变形。仅仅需要构成第一绝缘膜40的材料的刚度大于焊盘28的刚度,并且氧化铝(Al2O3)、铪氧化物(HfO)、钽氧化物(TaO)等可应用于第一绝缘膜40。第一绝缘膜40的厚度可以大于100nm以展示刚度,但比600nm薄以抑制应力并且降低电容器26的高度。
包括金(Au)的焊盘28在形成过孔10a期间展示针对半导体层11的蚀刻选择性。即,对于过孔10a的蚀刻可以有效地停止于焊盘28的底部。此外,包括金(Au)的焊盘28展示较低电阻率。因此,由于焊盘28具有相对小的刚度但具有更好的导电性,所以第一绝缘膜40可以对该较小的刚度进行补偿。焊盘28可以由替代金(Au)的铝(Al)、铜(Cu)和其他金属制成。
下电极20和焊盘28通过置于其之间的第一绝缘膜40电隔离。然而,在电容器26外部的互连部32可以将焊盘28与下电极20连接。如图1B所示,互连部32在上电极24外部的区域中与下电极20接触并且在下电极20外部的区域中与焊盘28接触。因此,下电极20可以通过互连部32和焊盘28连接至可以设置为地的金属层16或过孔电极18。
第二实施例
图5A是示出根据本发明的第二实施例的另一半导体器件200的平面图,以及图5B示出了沿着图5A所示的线Vb-Vb截取的半导体器件200的截面图。
如图5A和图5B所示,第二实施例的电容器26与焊盘28重叠,同时第一绝缘膜40置于电容器26与焊盘28之间。第二实施例的半导体器件200具有作为第三互连部的另一互连部34围绕电容器26并且焊盘28连接至半导体层11的特征。通过焊盘28连接至金属层16和过孔电极18的第三互连部34给出接地电平。连接至上电极24的互连部30与第三互连部34重叠但与第三互连部34形成间隙。互连部32和34可以通过电镀同时形成,而独立于互连部30的形成,该互连部30也可以通过在对于互连部32和34的前一电镀之后的金属电镀来形成。
第二实施例的半导体器件200可以有效地抑制电容器26的劣化,具体地,抑制其击穿电压的降低而不会扩大电容器26的空间。第三互连部34形成在电容器26周围且延伸到半导体层11,其中,该布置可以有效地通过第三互连部34按下焊盘28。结果,第三互连部34可以抑制焊盘26在蚀刻过孔10a以及沉积过孔电极18期间变形。可以抑制电容器26的击穿电压降低。
第三实施例
图6A是根据本发明的又一实施例的平面图,以及图6B示出了沿着图6A所示的线IVb-IVb截取的截面图。半导体器件300具有第一绝缘膜40A的区域比焊盘28宽的特征。即,本实施例的第一绝缘膜40A覆盖焊盘28的顶部和侧面,并且延伸至半导体层11的顶部。第二绝缘膜22覆盖下电极20的顶部、第一绝缘膜40A的顶部和侧面。绝缘膜14覆盖上电极24的顶部和第二绝缘膜22的顶部。第一开口13设置在绝缘膜12、40A、22和14中,以使焊盘28的顶部暴露。
由于下电极20通过第一绝缘膜40A与焊盘28隔离,因此下电极20变得与过孔10a和过孔电极18的形成无关。即,绝缘膜40A可以通过第一绝缘膜40A的存在而有效地抑制由衬底10和半导体层11的蚀刻以及金属层16和过孔电极18的形成而引起的下电极20的变形。此外,电容器26完全与焊盘28重叠,不需要扩大半导体器件300的平面尺寸。由于第一绝缘膜40A覆盖焊盘28和半导体层11,因此不需要蚀刻第一绝缘膜40A以跟随焊盘28的平面形状。
上述的第一至第三实施例的互连部32将下电极20与焊盘28连接。然而,互连部32可以将下电极20和上电极24中的至少一个与焊盘28连接。当互连部32将上电极24与焊盘28连接时,下电极20与另一互连部连接。
在上述实施例中,过孔10a穿过衬底10和半导体层11。然而,当半导体层11没有在整个衬底10上延伸时,过孔10a可以形成为仅穿过衬底10,并且伴随焊盘28的电容器26可以由衬底10形成。此外,并不始终形成过孔电极18。仅金属层16可以起到过孔电极18的作用。
在上述实施例中,电容器26、焊盘28和第一绝缘膜40或40A与过孔10a或过孔电极18垂直地重叠。然而,这些垂直布置可以与过孔10a或过孔电极18的一部分重叠。此外,下电极20和上电极24的平面尺寸比过孔10a或过孔电极18的平面尺寸宽,但是过孔电极18在顶部的平面尺寸可以比下电极20和上电极24的平面尺寸宽。
并不总是需要其他绝缘膜12和14。此外,互连部30和32可以被替换为接合带和/或接合线。半导体层11可以由砷化物半导体材料和/或氮化物半导体材料制成。氮化物半导体材料含氮,通常为镓氮化物(GaN)、铝镓氮化物(AlGaN)、铟镓氮化物(InGaN)、铟氮化物(InN)和铝铟镓氮化物(AlInGaN)。砷化物半导体材料可以包括砷化镓(GaAs)、砷化铝镓(AlGaAs)等。半导体层11可以包括除了FET外的有源器件。电容器26、焊盘28和金属层16或过孔电极18可以连接至这些有源器件。
尽管本文中出于说明的目的而描述了本发明的具体实施例,但是许多变型和改变对于本领域的技术人员而言是显而易见的。因此,所附权利要求旨在包括落入本发明的真实精神和范围内的所有这样的变型和改变。
Claims (10)
1.一种半导体器件,包括:
衬底;
半导体层,其设置在所述衬底上,所述衬底具有从所述衬底的底部贯穿到所述半导体层的顶部的过孔,过孔金属设置在所述过孔中;
焊盘,其设置在所述半导体层上并且与所述过孔金属电连接,所述焊盘完全覆盖所述过孔;
第一绝缘膜,其覆盖所述焊盘;
电容器,其设置在所述第一绝缘膜上,所述电容器从所述第一绝缘膜一侧起包括下电极、第二绝缘膜和上电极;以及
互连部,其与在所述焊盘的周边与所述焊盘连接,所述互连部围绕所述焊盘并且延伸至使所述半导体层暴露的区域,
其中,所述第一绝缘膜夹置于所述焊盘与所述电容器的下电极之间。
2.根据权利要求1所述的半导体器件,
其中,所述过孔金属填充所述过孔。
3.根据权利要求1或2所述的半导体器件,
其中,所述过孔金属覆盖所述过孔的侧面并且延伸至所述衬底的底面。
4.根据权利要求1所述的半导体器件,
其中,所述第一绝缘膜延伸至所述焊盘的外部,并且覆盖所述衬底上的所述半导体层。
5.根据权利要求1所述的半导体器件,
其中,所述电容器与所述第一绝缘膜完全重叠,并且所述第一绝缘膜与所述焊盘完全重叠。
6.根据权利要求1所述的半导体器件,还包括将所述下电极与所述焊盘连接的互连部,
其中,所述互连部在所述上电极外部的区域中与所述下电极连接,以及
其中,所述互连部在所述电容器外部的区域中与所述焊盘连接。
7.根据权利要求1所述的半导体器件,还包括将所述上电极与所述焊盘连接的另一互连部,
其中,所述另一互连部在所述电容器外部的区域中与所述焊盘连接。
8.根据权利要求1所述的半导体器件,
其中,所述第二绝缘膜在所述电容器外部延伸并且覆盖所述下电极的侧面和所述焊盘的顶部。
9.根据权利要求1所述的半导体器件,
其中,所述焊盘包含金(Au)。
10.根据权利要求1所述的半导体器件,
其中,所述第一绝缘膜由硅氧化物(SiOx)、硅氮化物(SiNx)和硅氧氮化物(SiON)之一制成。
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US10622302B2 (en) | 2018-02-14 | 2020-04-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Via for semiconductor device connection and methods of forming the same |
JP6981601B2 (ja) | 2018-05-29 | 2021-12-15 | 住友電工デバイス・イノベーション株式会社 | 半導体装置の製造方法 |
US11158775B2 (en) | 2018-06-08 | 2021-10-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
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US10992100B2 (en) | 2018-07-06 | 2021-04-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
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