CN107706113A - A kind of FinFET and preparation method, electronic installation - Google Patents
A kind of FinFET and preparation method, electronic installation Download PDFInfo
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- CN107706113A CN107706113A CN201610647023.0A CN201610647023A CN107706113A CN 107706113 A CN107706113 A CN 107706113A CN 201610647023 A CN201610647023 A CN 201610647023A CN 107706113 A CN107706113 A CN 107706113A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 24
- 238000009434 installation Methods 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 102
- 239000000463 material Substances 0.000 claims abstract description 72
- 238000005530 etching Methods 0.000 claims abstract description 65
- 239000007787 solid Substances 0.000 claims abstract description 50
- 239000004065 semiconductor Substances 0.000 claims abstract description 49
- 239000003054 catalyst Substances 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 238000003486 chemical etching Methods 0.000 claims abstract description 26
- 229910000673 Indium arsenide Inorganic materials 0.000 claims description 23
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 claims description 23
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 238000005566 electron beam evaporation Methods 0.000 claims description 4
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 2
- 230000003628 erosive effect Effects 0.000 claims 1
- 150000002736 metal compounds Chemical class 0.000 claims 1
- 239000007788 liquid Substances 0.000 abstract description 2
- 239000002184 metal Substances 0.000 description 29
- 239000000126 substance Substances 0.000 description 18
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 13
- 239000012212 insulator Substances 0.000 description 10
- 229910052732 germanium Inorganic materials 0.000 description 7
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 229910052729 chemical element Inorganic materials 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000000737 periodic effect Effects 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 229910003978 SiClx Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 238000004090 dissolution Methods 0.000 description 2
- 238000000609 electron-beam lithography Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000002105 nanoparticle Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 2
- 239000003039 volatile agent Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910020750 SixGey Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 239000000047 product Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
The present invention relates to a kind of FinFET and preparation method, electronic installation.Methods described includes：Semiconductor substrate is provided, is sequentially formed with fin material layer and Seed Layer on the semiconductor substrate；The mask layer with patterns of openings is formed in the Seed Layer, the patterns of openings exposes the Seed Layer；Etching catalyst layer is formed on the mask layer and the Seed Layer exposed, to cover the mask layer and the Seed Layer；Chemical etching is performed using the mask layer as mask, by auxiliary of the etching catalyst layer, is open with being formed in the Seed Layer；The fin material layer is etched by gas liquid solid engraving method in said opening, to form the fin at interval.Methods described can ensure that the FinFET of the more large ratio of height to width (High aspect ratio) is against damages, have good profile in the FinFET for making to be prepared, so as to improve the performance of the semiconductor devices and yield.
Description
Technical field
The present invention relates to technical field of semiconductors, is filled in particular to a kind of FinFET and preparation method, electronics
Put.
Background technology
With the continuous development of semiconductor technology, the raising of performance of integrated circuits is mainly by constantly reducing integrated circuit
The size of device is to improve its speed to realize.At present, due to the demand of high device density, high-performance and low cost, half
Conductor industry has advanced to nanometer technology process node, and the preparation of semiconductor devices is limited by various physics limits.
With the continuous diminution of cmos device size, the challenge from manufacture and design aspect has promoted three dimensional design such as fin
The development of gate fin-fet (FinFET).Relative to existing planar transistor, FinFET is to be used for 20nm and following work
The advanced semiconductor device of skill node, its can effectively control device it is scaled caused by the short channel for being difficult to overcome effect
Answer, the density of the transistor array formed on substrate can also be effectively improved, meanwhile, the grid in FinFET is around fin
(fin-shaped channel) is set, therefore can control electrostatic from three faces, and the performance in terms of Electrostatic Control is also more prominent.
It is raw generally on stress relaxation substrate Si xGey (strain relaxed buffer SixGey) in technique at present
The Ge of long tension, form fin, last epitaxial growth extension source/drain stress riser, to form extra stress increase.
The change of FinFET (Epi-defined FinFET) for threshold voltage that extension limits embodies more preferable property
Energy.Therefore how the significantly more efficient FinFET for preparing the extension restriction turns into solves the problems, such as at present.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will enter in specific embodiment part
One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical scheme claimed
Key feature and essential features, the protection domain for attempting to determine technical scheme claimed is not meant that more.
In order to overcome the problem of presently, there are, the invention provides a kind of preparation method of FinFET, methods described
Including：
Semiconductor substrate is provided, is sequentially formed with fin material layer and Seed Layer on the semiconductor substrate；
The mask layer with patterns of openings is formed in the Seed Layer, the patterns of openings exposes the Seed Layer；
Etching catalyst layer is formed on the mask layer and the Seed Layer exposed, to cover the mask layer and institute
State Seed Layer；
Chemical etching is performed using the mask layer as mask, by auxiliary of the etching catalyst layer, with the seed
Layer forms opening；
The fin material layer is etched by gas-liquid-solid engraving method in said opening, to form interval
Fin.
Alternatively, etching solution includes H described in described in chemical etching the step of Seed Layer2O2And H2SO4。
Alternatively, the fin material layer includes III-V fin material layer.
Alternatively, the fin material layer includes InAs layers.
Alternatively, the Seed Layer selects layer of InP.
Alternatively, the forming method of the Seed Layer includes MOCVD.
Alternatively, the etching catalyst layer is formed by the method for electron beam evaporation.
Alternatively, the step of methods described also includes removing the mask layer and the etching catalyst layer.
Alternatively, methods described also includes passing through HCl and H3PO4The step of removing the Seed Layer, to expose the fin
Piece.
Present invention also offers a kind of FinFET, the FinFET is prepared by the above method.
Present invention also offers a kind of electronic installation, the electronic installation includes above-mentioned FinFET.
In order to solve problem present in current technique, the invention provides a kind of preparation method of FinFET, institute
State method and form fin material layer, such as InAs materials on a semiconductor substrate first, then the shape on the fin material layer
Into Seed Layer, and etching catalyst layer is formed after the Seed Layer is patterned, then pass through metal assisted chemical etch side
The method of method (Metal-Assisted Chemical Etching) etches the Seed Layer, then in the etching catalyst
(Vapor-Liquid-Solid Etch) method is etched by gas-liquid-solid under the auxiliary of layer and etches the fin material
Layer, to form the fin at interval.
Wherein, the gas-liquid-solid etches (Vapor-Liquid-Solid Etch) method for the etching
Catalyst layer and the fin material layer have great etching selectivity, so as to which more large ratio of height to width (High- be prepared
Aspect-ratio FinFET), it is often more important that (Vapor-Liquid- is etched by the gas-liquid-solid
Solid Etch) it can also ensure that the FinFET of the more large ratio of height to width (High-aspect-ratio) is against damages, make
There is good profile, so as to improve the performance of the semiconductor devices and yield in the FinFET being prepared.
The FinFET of the present invention, as a result of above-mentioned manufacture method, thus equally has above-mentioned advantage.The present invention
Electronic installation, as a result of above-mentioned FinFET, thus equally there is above-mentioned advantage.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the principle of the present invention.
In accompanying drawing：
Fig. 1 shows the preparation technology flow chart of FinFET of the present invention；
Fig. 2 a-2f show that the preparation method of FinFET of the present invention is implemented the section of obtained structure and shown successively
It is intended to；
Fig. 3 shows the schematic diagram of electronic installation according to an embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated.From beginning to end
Same reference numerals represent identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " other members
When part or layer, its can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be element or layer between two parties.On the contrary, when element be referred to as " on directly existing ... ", " with ... direct neighbor ", " be directly connected to
To " or when " being directly coupled to " other elements or layer, then element or layer between two parties is not present.It should be understood that although art can be used
Language first, second, third, etc. describe various elements, part, area, floor and/or part, these elements, part, area, floor and/or portion
Dividing to be limited by these terms.These terms are used merely to distinguish an element, part, area, floor or part and another
Element, part, area, floor or part.Therefore, do not depart from present invention teach that under, the first element discussed below, part, area,
Floor or part are represented by the second element, part, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... on ",
" above " etc., herein can for convenience description and by using so as to describe an element shown in figure or feature with it is other
The relation of element or feature.It should be understood that in addition to the orientation shown in figure, spatial relationship term be intended to also including the use of with
The different orientation of device in operation.For example, if the device upset in accompanying drawing, then, is described as " below other elements "
Or " under it " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, exemplary term
" ... below " and " ... under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other takes
To) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when in this specification in use, determining the feature, whole
Number, step, operation, the presence of element and/or part, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, part and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description, to explain this
Invent the technical scheme proposed.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, this hair
It is bright to have other embodiment.
In order to solve above mentioned problem present in current technique, the invention provides a kind of preparation side of FinFET
Method, methods described include：
Semiconductor substrate is provided, is sequentially formed with fin material layer and Seed Layer on the semiconductor substrate；
The mask layer with patterns of openings is formed in the Seed Layer, the patterns of openings exposes the Seed Layer；
Etching catalyst layer is formed on the mask layer and the Seed Layer exposed, to cover the mask layer and institute
State Seed Layer；
Chemical etching is performed using the mask layer as mask, by auxiliary of the etching catalyst layer, with the seed
Layer forms opening；
The fin material layer is etched by gas-liquid-solid engraving method in said opening, to form interval
Fin.
Alternatively, the step of methods described also includes removing the mask layer and the etching catalyst layer, to expose
State Seed Layer.
Methods described also includes passing through HCl and H3PO4The step of removing the Seed Layer, to expose the fin.
Wherein, the chemical etching in the present invention is metal assisted chemical etch method (Metal-Assisted
Chemical Etching), i.e., Seed Layer is formed in the bottom of etching, then sequentially form material to be etched, eventually form
Metal level, chemical etching, the metal assisted chemical etch method are carried out on the premise of the metal level is as catalyst
(Metal-Assisted Chemical Etching) has the selectivity of height.
Specifically, the Seed Layer selects layer of InP in the present invention, but is not limited to the example.
Wherein, the etching catalyst layer includes metal level, such as can select Au, but be not limited to that described show
Example.
Wherein, the metal assisted chemical etch method (Metal-Assisted Chemical Etching) is to described
Seed Layer and the Semiconductor substrate and the metal level have very big etching selectivity, are removing the mistake of the Seed Layer
The Semiconductor substrate and the metal level will not be had any impact in journey.
Alternatively, the fin material layer includes III-V fin material layer.
Wherein described III-V fin material layer has the following advantages that：
(1) process costs are relatively small, inexpensively many compared to SOI pieces；
(2) due to using germanium, III-V substrate, so the mobility ratio of device is higher, therefore larger open can be obtained
State electric current, wherein the ratio of the ON state current and off-state current can reach 106More than；
(3) can effective adjusting means threshold voltage.
Wherein described III-V fin material layer refers to include the masters of the 3rd main group IIIA and the 5th in the periodic table of chemical element
Race VA semi-conducting material, such as InAs etc., but the species of specific fin and composition can be carried out according to being actually needed
Selection.
Wherein, the fin material layer can be crystal structure, and the scope of its lattice constant is not limited to a certain numerical value
Scope.
Further, the fin material layer can pass through MOCVD (Metal-organic
Chemical Vapor Deposition, MOCVD) method formed.
Wherein, MOCVD (Metal-organic Chemical Vapor are passed through
Deposition, MOCVD) performance of the III-V fin material layer that is formed is more excellent, can further improve described
The performance and yield of semiconductor devices.
Wherein, the step of forming the fin includes：Using the mask layer and the Seed Layer as mask, by gas-
Liquid-solid etching (Vapor-Liquid-Solid Etch) method etches the fin material layer, to form the fin at interval
Piece.
Wherein, in the gas-liquid-solid etches (Vapor-Liquid-Solid Etch) method, the gas
Body-liquid-solid includes the etching catalyst layer and InAs of vapor, aqueous water and solid-state, produces vapor during heating, institute
The Au nano-particles for stating etching catalyst layer freely move on (001) surface of the InAs, with the golden nanometer particle
Movement, on the InAs surfaces along alignment groove (aligned grooves) crystallization ground etching (etch
Crystallographically) extremely below the InAs surfaces.
The InAs reacts by the catalyst dissolution, and with vapor in this process, forms volatile compound
Into the opening, InAs is removed completely, and methods described has higher selection compared to other method.
In order to solve problem present in current technique, the invention provides a kind of preparation method of FinFET, institute
State method and form fin material layer, such as InAs materials on a semiconductor substrate first, then the shape on the fin material layer
Into Seed Layer, and etching catalyst layer is formed after the Seed Layer is patterned, then pass through metal assisted chemical etch side
The method of method (Metal-Assisted Chemical Etching) etches the Seed Layer, then in the etching catalyst
(Vapor-Liquid-Solid Etch) method is etched by gas-liquid-solid under the auxiliary of layer and etches the fin material
Layer, to form the fin at interval.
Wherein, the gas-liquid-solid etches (Vapor-Liquid-Solid Etch) method for the etching
Catalyst layer and the fin material layer have great etching selectivity, so as to which more large ratio of height to width (High- be prepared
Aspect-ratio FinFET), it is often more important that (Vapor-Liquid- is etched by the gas-liquid-solid
Solid Etch) method can also ensure the FinFET of the more large ratio of height to width (High-aspect-ratio) from damage
It is bad, there is good profile in the FinFET for making to be prepared, so as to improve the performance of the semiconductor devices and good
Rate.
Etching (Vapor-Liquid-Solid Etch) method by the gas-liquid-solid can make to be prepared
The depth-width ratio (High-aspect-ratio) of fin reach 45:More than 1, but also can ensure that the fin profile has
Good performance, profile defects will not occur, so as to improve the performance of the semiconductor devices and yield.
The FinFET of the present invention, as a result of above-mentioned manufacture method, thus equally has above-mentioned advantage.The present invention
Electronic installation, as a result of above-mentioned FinFET, thus equally there is above-mentioned advantage.
Embodiment one
The preparation method of the FinFET of the present invention is described in detail below with reference to Fig. 1 and Fig. 2 a-2f, Fig. 1 is shown
The preparation technology flow chart of FinFET of the present invention；Fig. 2 a-2f show the system of FinFET of the present invention
Preparation Method implements the diagrammatic cross-section of obtained structure successively.
The present invention provides a kind of preparation method of FinFET, as shown in figure 1, the key step bag of the preparation method
Include：
Step S1：Semiconductor substrate is provided, is sequentially formed with fin material layer and Seed Layer on the semiconductor substrate；
Step S2：The mask layer with patterns of openings is formed in the Seed Layer, the patterns of openings exposes the kind
Sublayer；
Step S3：Etching catalyst layer is formed on the mask layer and the Seed Layer exposed, to be covered described in covering
Film layer and the Seed Layer；
Step S4：Chemical etching is performed using the mask layer as mask, by auxiliary of the etching catalyst layer, with institute
State Seed Layer and form opening；
Step S5：The fin material layer is etched by gas-liquid-solid engraving method in said opening, with shape
Fin at interval.
Below, the embodiment of the preparation method of the FinFET of the present invention is described in detail.
First, step 1 is performed, there is provided Semiconductor substrate (not shown), sequentially form on the semiconductor substrate
There are fin material layer 201 and Seed Layer 202.
Specifically, as shown in Figure 2 a, the Semiconductor substrate can be in the following material being previously mentioned in this step
It is at least one：Silicon, silicon-on-insulator (SOI), silicon (SSOI) is laminated on insulator, is laminated SiGe (S- on insulator
SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..
Semiconductor substrate selects silicon in this embodiment.
Fin material layer 201 and Seed Layer 202 are sequentially formed on the semiconductor substrate, wherein, the fin material
Layer 201 includes III-V fin material layer.
Wherein described III-V fin material layer has the following advantages that：
(1) process costs are relatively small, inexpensively many compared to SOI pieces；
(2) due to using germanium, III-V substrate, so the mobility ratio of device is higher, therefore larger open can be obtained
State electric current, wherein the ratio of the ON state current and off-state current can reach 106More than；
(3) can effective adjusting means threshold voltage.
Wherein described III-V fin material layer refers to include the masters of the 3rd main group IIIA and the 5th in the periodic table of chemical element
Race VA semi-conducting material, such as InAs etc., but the species of specific fin and composition can be carried out according to being actually needed
Selection.
Wherein, the fin material layer can be crystal structure, and the scope of its lattice constant is not limited to a certain numerical value
Scope.
Further, the fin material layer can pass through MOCVD (Metal-organic
Chemical Vapor Deposition, MOCVD) method formed.
Wherein, MOCVD (Metal-organic Chemical Vapor are passed through
Deposition, MOCVD) performance of the III-V fin material layer that is formed is more excellent, can further improve described
The performance and yield of semiconductor devices.
The Seed Layer selects layer of InP in the present invention, but is not limited to the example.
Further, InAlAs layers can also be formed between the Semiconductor substrate and the fin material layer, wherein,
The thickness of the InAlAs layers is much smaller than the thickness of the fin material layer.
Step 2 is performed, the mask layer 203 with patterns of openings is formed in the Seed Layer, the patterns of openings is exposed
The Seed Layer.
Specifically, as shown in Figure 2 a, the mask layer 203 can select hydrogen-silsesquioxane in this step
(Hydrogen silesquioxane, HSQ) material.
The mask layer 203 is patterned to form patterns of openings, such as forms the photoresist layer of patterning, with photoresist layer
For mask layer described in mask etch.
The patterning method can select e-beam patterning (E-beam patterning) method in this step.
Step 3 is performed, etching catalyst layer 204 is formed on the mask layer and the Seed Layer exposed, with covering
The mask layer and the Seed Layer；
Specifically, as shown in Figure 2 b, etching catalyst is formed on the mask layer 203 and the Seed Layer exposed
Layer 204, so that the mask layer and the Seed Layer, including the top and side of the mask layer and the Seed Layer is completely covered
Wall.
Wherein, the etching catalyst layer 204 includes metal level, such as can select Au, but be not limited to that described
Example.
Wherein, in this step from electron beam evaporation (E-beam evaporation) method formed it is described etching urge
Agent layer 204, such as the thin layer by electron beam evaporation deposition technique formation metal Au.
Step 4 is performed, chemical etching is performed using the mask layer as mask, by auxiliary of the etching catalyst layer, with
Formed and be open in the Seed Layer.
Specifically, as shown in Figure 2 c, H can be selected in the step 12SO4And H2O2In it is one or more as anti-
Liquid is answered to be reacted, to form the opening in the Seed Layer.
Such as from H2SO4And H2O2Reacted as reaction solution, to form the opening in the Seed Layer.
Wherein, the etching of the metal assisted chemical etch method (Metal-Assisted Chemical Etching)
Temperature can be room temperature.
Wherein, the metal assisted chemical etch method (Metal-Assisted Chemical Etching) is to described
Seed Layer and the metal level have very big etching selectivity, will not be to the metal during the Seed Layer is removed
Layer has any impact.
Step 5 is performed, the fin material layer is etched by gas-liquid-solid engraving method in said opening,
To form the fin at interval.
Specifically, as shown in Figure 2 d, wherein, (Vapor-Liquid-Solid is etched in the gas-liquid-solid
Etch) in method, the gas-liquid-solid includes the etching catalyst layer and InAs of vapor, aqueous water and solid-state,
Vapor is produced during heating, the Au nano-particles of the etching catalyst layer freely move on (001) surface of the InAs,
With the movement of the golden nanometer particle, along groove (aligned grooves) the crystallization ground of alignment on the InAs surfaces
(etch crystallographically) is etched extremely below the InAs surfaces.
The InAs reacts by the catalyst dissolution, and with vapor in this process, forms volatile compound
Removed completely to the InAs, methods described has higher selection compared to other method.
Etching (Vapor-Liquid-Solid Etch) method by the gas-liquid-solid can make to be prepared
The depth-width ratio (High-aspect-ratio) of fin reach 45:More than 1, but also can ensure that the fin profile has
Good performance, profile defects will not occur, so as to improve the performance of the semiconductor devices and yield.
Wherein, the fin can include spaced several columns, such as the fin can be arranged in parallel or institute
Fin is stated in mutually nested loop configuration etc., it is not limited to a certain.
Step 6 is performed, the mask layer and the etching catalyst layer are removed, to expose the Seed Layer.
Specifically, as shown in Figure 2 e, the minimizing technology, which can be selected, with the Semiconductor substrate there is larger etching to select
Select than method.
Step 7 is performed, the Seed Layer is removed, to expose the fin.
Specifically, as shown in figure 2f, HCl and H are passed through in this step3PO4The Seed Layer is removed, to expose the fin
Piece.
HCl and H is selected in this step3PO4To the etching selectivity of the Seed Layer and the fin material layer 1000
More than, therefore can ensure to avoid the damage to the fin while Seed Layer is removed completely.
For example, the Seed Layer is InP in this application, when the fin is InAs, from HCl and H3PO4Etching choosing
Select than bigger, much larger than 1000.
Wherein, the HCl and H3PO4Volume ratio 1:3.
So far, the introduction of the correlation step of the preparation method of the FinFET of the embodiment of the present invention is completed.The side
The step of method can also include forming transistor and other correlation steps, here is omitted.Also, except above-mentioned steps it
Outside, the preparation method of the present embodiment can also include other steps among above-mentioned each step or between different steps, this
A little steps can realize that here is omitted by the various techniques in current technique.
In order to solve problem present in current technique, the invention provides a kind of preparation method of FinFET, institute
State method and form fin material layer, such as InAs materials on a semiconductor substrate first, then the shape on the fin material layer
Into Seed Layer, and etching catalyst layer is formed after the Seed Layer is patterned, then pass through metal assisted chemical etch side
The method of method (Metal-Assisted Chemical Etching) etches the Seed Layer, then in the etching catalyst
(Vapor-Liquid-Solid Etch) method is etched by gas-liquid-solid under the auxiliary of layer and etches the fin material
Layer, to form the fin at interval.
Wherein, the gas-liquid-solid etches (Vapor-Liquid-Solid Etch) method for the etching
Catalyst layer and the fin material layer have great etching selectivity, so as to which more large ratio of height to width (High- be prepared
Aspect-ratio FinFET), it is often more important that (Vapor-Liquid- is etched by the gas-liquid-solid
Solid Etch) method can also ensure the FinFET of the more large ratio of height to width (High-aspect-ratio) from damage
It is bad, there is good profile in the FinFET for making to be prepared, so as to improve the performance of the semiconductor devices and good
Rate.
Embodiment two
Present invention also offers a kind of FinFET, the FinFET includes：
Semiconductor substrate；
Fin, positioned at the semiconductor substrate.
Wherein, the fin can include spaced several columns, such as the fin can be arranged in parallel or institute
Fin is stated in mutually nested loop configuration etc., it is not limited to a certain.
Wherein, the FinFET includes Semiconductor substrate, and the Semiconductor substrate can be the following material being previously mentioned
At least one of material：Silicon, silicon-on-insulator (SOI), silicon (SSOI) is laminated on insulator, is laminated SiGe (S- on insulator
SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..Semiconductor substrate is selected in this embodiment
Use silicon.
Wherein, the fin includes III-V material.
Wherein described III-V material has the following advantages that：
(1) process costs are relatively small, inexpensively many compared to SOI pieces；
(2) due to using germanium, III-V substrate, so the mobility ratio of device is higher, therefore larger open can be obtained
State electric current, wherein the ratio of the ON state current and off-state current can reach more than 106；
(3) can effective adjusting means threshold voltage.
Wherein described III-V fin material layer refers to include the masters of the 3rd main group IIIA and the 5th in the periodic table of chemical element
Race VA semi-conducting material, such as InAs etc., but the species of specific semi-conducting material and composition can be according to actual need
Selected.
Wherein described III-V fin material layer refers to include the masters of the 3rd main group IIIA and the 5th in the periodic table of chemical element
Race VA semi-conducting material, such as InAs etc., but the species of specific fin and composition can be carried out according to being actually needed
Selection.
Wherein, the fin material layer can be crystal structure, and the scope of its lattice constant is not limited to a certain numerical value
Scope.
Further, the fin material layer can pass through MOCVD (Metal-organic
Chemical Vapor Deposition, MOCVD) method formed.
Wherein, MOCVD (Metal-organic Chemical Vapor are passed through
Deposition, MOCVD) performance of the III-V fin material layer that is formed is more excellent, can further improve described
The performance and yield of semiconductor devices.
Opening in heretofore described Seed Layer passes through metal assisted chemical etch method (Metal-Assisted
Chemical Etching) formed.
Wherein, heretofore described metal assisted chemical etch method (Metal-Assisted Chemical
Etching) include：Seed Layer is formed in the bottom of etching, material to be etched is then sequentially formed, eventually forms metal level,
Chemical etching, the metal assisted chemical etch method (Metal- are carried out on the premise of the metal level is as catalyst
Assisted Chemical Etching) there is the selectivity of height.
Specifically, the Seed Layer selects layer of InP in the present invention, but is not limited to the example.
Wherein, the etching catalyst layer includes metal level, such as can select Au, but be not limited to that described show
Example.
Wherein, the metal assisted chemical etch method (Metal-Assisted Chemical Etching) is to described
Seed Layer and the metal level have very big etching selectivity, will not partly be led to described during the Seed Layer is removed
Body substrate and the metal level have any impact.
Wherein, the etching of the metal assisted chemical etch method (Metal-Assisted Chemical Etching)
Temperature can be room temperature.
Institute is etched by the method for metal assisted chemical etch method (Metal-Assisted Chemical Etching)
After stating Seed Layer, (Vapor-Liquid- is etched by gas-liquid-solid under the auxiliary of the etching catalyst layer
Solid Etch) the method etching fin material layer, to form the fin at interval.
Wherein, the gas-liquid-solid etches (Vapor-Liquid-Solid Etch) method for the etching
Catalyst layer and the fin material layer have great etching selectivity, so as to which more large ratio of height to width (High- be prepared
Aspect-ratio FinFET), it is often more important that (Vapor-Liquid- is etched by the gas-liquid-solid
Solid Etch) method can also ensure the FinFET of the more large ratio of height to width (High-aspect-ratio) from damage
It is bad, there is good profile in the FinFET for making to be prepared, so as to improve the performance of the semiconductor devices and good
Rate.
Etching (Vapor-Liquid-Solid Etch) method by the gas-liquid-solid can make to be prepared
The depth-width ratio (High-aspect-ratio) of fin reach 45:More than 1, but also can ensure that the fin profile has
Good performance, profile defects will not occur, so as to improve the performance of the semiconductor devices and yield.
Embodiment three
An alternative embodiment of the invention provides a kind of electronic installation, and it includes FinFET, and the FinFET is
FinFET in previous embodiment two, or obtained by the preparation method of FinFET according to embodiment one
FinFET.
The electronic installation, can be mobile phone, tablet personal computer, notebook computer, net book, game machine, television set, VCD,
Any electronic product such as DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment or have
The intermediate products of above-mentioned FinFET, such as：Cell phone mainboard with the integrated circuit etc..
Due to including FinFET part there is higher performance, the electronic installation equally has above-mentioned advantage.
Wherein, Fig. 3 shows the example of mobile phone handsets.Mobile phone handsets 300, which are equipped with, to be included in shell 301
Display portion 302, operation button 303, external connection port 304, loudspeaker 305, microphone 306 etc..
Wherein described mobile phone handsets include foregoing FinFET, or the FinFET devices according to embodiment one
FinFET obtained by the preparation method of part, first formed on a semiconductor substrate in the preparation process of the FinFET
Fin material layer, such as InAs materials, Seed Layer is then formed on the fin material layer, and patterning the Seed Layer
Etching catalyst layer is formed afterwards, then passes through metal assisted chemical etch method (Metal-Assisted Chemical
Etching method) etches the Seed Layer, then passes through gas-liquid-solid under the auxiliary of the etching catalyst layer
(Vapor-Liquid-Solid Etch) method of etching etches the fin material layer, to form the fin at interval.Wherein, institute
Gas-liquid-solid etching (Vapor-Liquid-Solid Etch) method is stated for the etching catalyst layer and described
Fin material layer has great etching selectivity, so as to which more large ratio of height to width (High-aspect-ratio) be prepared
FinFET, it is often more important that (Vapor-Liquid-Solid Etch) method is etched by the gas-liquid-solid
It can also ensure that the FinFET of the more large ratio of height to width (High-aspect-ratio) is against damages, make what is be prepared
There is good profile, so as to improve the performance of the semiconductor devices and yield in FinFET.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member can also make more kinds of it is understood that the invention is not limited in above-described embodiment according to the teachings of the present invention
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (11)
1. a kind of preparation method of FinFET, it is characterised in that methods described includes：
Semiconductor substrate is provided, is sequentially formed with fin material layer and Seed Layer on the semiconductor substrate；
The mask layer with patterns of openings is formed in the Seed Layer, the patterns of openings exposes the Seed Layer；
Etching catalyst layer is formed on the mask layer and the Seed Layer exposed, to cover the mask layer and the kind
Sublayer；
Chemical etching is performed using the mask layer as mask, by auxiliary of the etching catalyst layer, with the Seed Layer shape
Into opening；
The fin material layer is etched by gas-liquid-solid engraving method in said opening, to form the fin at interval
Piece.
2. according to the method for claim 1, it is characterised in that described in chemical etching the step of Seed Layer described in etching solution
Including H2O2And H2SO4。
3. according to the method for claim 1, it is characterised in that the fin material layer includes III-V fin material layer.
4. the method according to claim 1 or 3, it is characterised in that the fin material layer includes InAs layers.
5. according to the method for claim 1, it is characterised in that the Seed Layer selects layer of InP.
6. method according to claim 1 or 5, it is characterised in that it is organic that the forming method of the Seed Layer includes metal
Compound chemical vapor deposition.
7. according to the method described in claim 1, it is characterised in that form the etching catalyst by the method for electron beam evaporation
Layer.
8. according to the method for claim 1, it is characterised in that methods described also includes removing the mask layer and the erosion
The step of carving catalyst layer.
9. according to the method for claim 1, it is characterised in that methods described also includes passing through HCl and H3PO4Described in removal
The step of Seed Layer, to expose the fin.
10. a kind of FinFET, it is characterised in that the FinFET passes through one of claim 1 to 9 methods described system
It is standby to obtain.
11. a kind of electronic installation, it is characterised in that the electronic installation includes the FinFET described in claim 10.
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| CN108766886A (en) * | 2018-05-24 | 2018-11-06 | 上海集成电路研发中心有限公司 | A kind of forming method of fin formula field effect transistor structure |
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