CN107706113B - FinFET device, preparation method thereof and electronic device - Google Patents

FinFET device, preparation method thereof and electronic device Download PDF

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CN107706113B
CN107706113B CN201610647023.0A CN201610647023A CN107706113B CN 107706113 B CN107706113 B CN 107706113B CN 201610647023 A CN201610647023 A CN 201610647023A CN 107706113 B CN107706113 B CN 107706113B
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layer
etching
seed layer
fin material
mask
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CN107706113A (en
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张海洋
王彦
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
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Abstract

The invention relates to a FinFET device, a preparation method and an electronic device. The method comprises the following steps: providing a semiconductor substrate, and sequentially forming a fin material layer and a seed layer on the semiconductor substrate; forming a mask layer with an opening pattern on the seed layer, wherein the opening pattern exposes the seed layer; forming an etching catalyst layer on the mask layer and the exposed seed layer to cover the mask layer and the seed layer; performing chemical etching with the mask layer as a mask and the etching catalyst layer as an auxiliary to form an opening in the seed layer; the fin material layer is etched in the openings by a gas-liquid-solid etching process to form spaced fins. The method can ensure that the FinFET device with the larger height-aspect-ratio (High-aspect-ratio) is prevented from being damaged, so that the prepared FinFET device has a good profile, and the performance and the yield of the semiconductor device are improved.

Description

FinFET device, preparation method thereof and electronic device
Technical Field
The invention relates to the technical field of semiconductors, in particular to a FinFET device, a manufacturing method of the FinFET device and an electronic device.
Background
With the continuous development of semiconductor technology, the performance of integrated circuits is improved mainly by the continuous reduction of the size of integrated circuit devices to increase the speed thereof. Currently, the semiconductor industry has progressed to nanotechnology process nodes due to demands for high device density, high performance, and low cost, and the fabrication of semiconductor devices is limited by various physical limitations.
As CMOS device dimensions continue to shrink, challenges from manufacturing and design aspects have prompted the development of three-dimensional designs such as fin field effect transistors (finfets). Compared with the existing planar transistor, the FinFET is an advanced semiconductor device for process nodes of 20nm and below, can effectively control the short channel effect which is difficult to overcome due to the fact that the device is scaled down, can also effectively improve the density of a transistor array formed on a substrate, and meanwhile, a grid electrode in the FinFET is arranged around a fin (a fin-shaped channel), so that static electricity can be controlled from three surfaces, and the performance in the aspect of static electricity control is more outstanding.
In the prior art, Ge with tensile stress is generally grown on a stress relaxation substrate sixgey (strained buffer sixgey) to form a fin, and finally, an epitaxial source/drain stressor is epitaxially grown to form additional stress increase.
Epitaxially defined finfets (Epi-defined finfets) exhibit better performance for variations in threshold voltage. It is therefore a problem to date how to more efficiently fabricate such epitaxially defined FinFET devices.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In order to overcome the existing problems, the invention provides a preparation method of a FinFET device, which comprises the following steps:
providing a semiconductor substrate, and sequentially forming a fin material layer and a seed layer on the semiconductor substrate;
forming a mask layer with an opening pattern on the seed layer, wherein the opening pattern exposes the seed layer;
forming an etching catalyst layer on the mask layer and the exposed seed layer to cover the mask layer and the seed layer;
performing chemical etching with the mask layer as a mask and the etching catalyst layer as an auxiliary to form an opening in the seed layer;
the fin material layer is etched in the openings by a gas-liquid-solid etching process to form spaced fins.
Optionally, the etching solution in the step of chemically etching the seed layer includes H2O2And H2SO4。
Optionally, the fin material layer comprises a iii-v family fin material layer.
Optionally, the fin material layer comprises an InAs layer.
Optionally, the seed layer is an InP layer.
Optionally, the method for forming the seed layer includes metal organic compound chemical vapor deposition.
Alternatively, the etching catalyst layer is formed by an electron beam evaporation method.
Optionally, the method further comprises the step of removing the mask layer and the etching catalyst layer.
Optionally, the method further comprises passing HCl and H3PO4And removing the seed layer to expose the fins.
The invention also provides a FinFET device prepared by the method.
The invention also provides an electronic device comprising the FinFET device.
In order to solve the problems in the prior art, the present invention provides a method for manufacturing a FinFET device, which includes forming a fin material layer, such as InAs, on a semiconductor substrate, forming a seed layer on the fin material layer, forming an Etching catalyst layer after patterning the seed layer, Etching the seed layer by a Metal-Assisted Chemical Etching method (Metal-Assisted Chemical Etching), and Etching the fin material layer by a gas-Liquid-Solid Etching (Vapor-Liquid-Solid Etching) method with the aid of the Etching catalyst layer to form spaced fins.
The gas-Liquid-Solid etching (Vapor-Liquid-Solid Etch) method has a very large etching selection ratio for the etching catalyst layer and the fin material layer, so that a FinFET device with a larger height-aspect-ratio (High-aspect-ratio) is prepared, and more importantly, the FinFET device with the larger height-aspect-ratio (High-aspect-ratio) can be ensured to be free from damage through the gas-Liquid-Solid etching (Vapor-Liquid-Solid Etch), so that a good profile is obtained in the prepared FinFET device, and the performance and yield of the semiconductor device are improved.
The FinFET device of the invention also has the advantages due to the adoption of the manufacturing method. The electronic device of the invention also has the advantages because the FinFET device is adopted.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
fig. 1 illustrates a process flow diagram for fabricating a FinFET device in accordance with the present invention;
fig. 2a-2f are schematic cross-sectional views of structures obtained by implementing the method of fabricating a FinFET device of the present invention in sequence;
fig. 3 shows a schematic view of an electronic device according to an embodiment of the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relationship terms such as "under …", "under …", "below", "under …", "above …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below …" and "below …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
In order to solve the above problems in the prior art, the present invention provides a method for manufacturing a FinFET device, including:
providing a semiconductor substrate, and sequentially forming a fin material layer and a seed layer on the semiconductor substrate;
forming a mask layer with an opening pattern on the seed layer, wherein the opening pattern exposes the seed layer;
forming an etching catalyst layer on the mask layer and the exposed seed layer to cover the mask layer and the seed layer;
performing chemical etching with the mask layer as a mask and the etching catalyst layer as an auxiliary to form an opening in the seed layer;
the fin material layer is etched in the openings by a gas-liquid-solid etching process to form spaced fins.
Optionally, the method further comprises the step of removing the mask layer and the etching catalyst layer to expose the seed layer.
The process further comprises passing HCl and H3PO4And removing the seed layer to expose the fins.
In the invention, the Chemical Etching is a Metal-Assisted Chemical Etching method (Metal-Assisted Chemical Etching), namely, a seed layer is formed at the bottom of Etching, then a material to be etched is sequentially formed, finally a Metal layer is formed, and the Chemical Etching is carried out on the premise that the Metal layer is used as a catalyst, wherein the Metal-Assisted Chemical Etching method (Metal-Assisted Chemical Etching) has high selectivity.
Specifically, the InP layer is used as the seed layer in the present invention, but is not limited to the above example.
Wherein the etching catalyst layer includes a metal layer, for example, Au is selected, but not limited to the example.
Wherein the Metal-Assisted Chemical Etching method (Metal-Assisted Chemical Etching) has a large Etching selectivity ratio for the seed layer and the semiconductor substrate and the Metal layer, and does not affect the semiconductor substrate and the Metal layer in the process of removing the seed layer.
Optionally, the fin material layer comprises a iii-v family fin material layer.
The III-V group fin material layer has the following advantages:
(1) the process cost is relatively low, and compared with an SOI (silicon on insulator) sheet, the process cost is much lower;
(2) as the germanium and III-V group substrate is adopted, the mobility ratio of the device is higher, so that larger on-state current can be obtained, wherein the ratio of the on-state current to the off-state current can reach 106The above;
(3) the threshold voltage of the device can be effectively adjusted.
The fin material layer of the third-fifth group refers to a semiconductor material including a third main group IIIA and a fifth main group VA in the periodic table of chemical elements, such as InAs, but the type and composition of a specific fin can be selected according to actual needs.
The fin material layer may have a crystal structure, and the range of the lattice constant is not limited to a certain range of values.
Further, the fin material layer may be formed by Metal-organic Chemical Vapor Deposition (MOCVD).
The performance of the three-five group fin material layer formed by Metal-organic Chemical Vapor Deposition (MOCVD) is more excellent, and the performance and yield of the semiconductor device can be further improved.
Wherein the step of forming the fin includes: and etching the fin material layer by using the mask layer and the seed layer as masks through a gas-Liquid-Solid etching (Vapor-Liquid-Solid Etch) method to form spaced fins.
Wherein, in the gas-Liquid-Solid etching (Vapor-Liquid-Solid Etch) method, the gas-Liquid-Solid comprises water Vapor, Liquid water, and a Solid etching catalyst layer and InAs, water Vapor is generated when heating, Au nanoparticles of the etching catalyst layer freely move on the (001) surface of the InAs, and the InAs surface is crystallographically etched (etched) along aligned grooves (aligned grooves) to be below the InAs surface along with the movement of the Au nanoparticles.
During which the InAs is dissolved by the catalyst and reacts with water vapor to form volatile compounds until the InAs is completely removed from the openings, which method has a higher selectivity than other methods.
In order to solve the problems in the prior art, the present invention provides a method for manufacturing a FinFET device, which includes forming a fin material layer, such as InAs, on a semiconductor substrate, forming a seed layer on the fin material layer, forming an Etching catalyst layer after patterning the seed layer, Etching the seed layer by a Metal-Assisted Chemical Etching method (Metal-Assisted Chemical Etching), and Etching the fin material layer by a gas-Liquid-Solid Etching (Vapor-Liquid-Solid Etching) method with the aid of the Etching catalyst layer to form spaced fins.
The gas-Liquid-Solid etching (Vapor-Liquid-Solid etching) method has a very large etching selection ratio for the etching catalyst layer and the fin material layer, so that a FinFET device with a larger height-to-width ratio (High-aspect-ratio) is prepared, and more importantly, the gas-Liquid-Solid etching (Vapor-Liquid-Solid etching) method can also ensure that the FinFET device with the larger height-to-width ratio (High-aspect-ratio) is prevented from being damaged, so that the prepared FinFET device has a good profile, and thus the performance and yield of the semiconductor device are improved.
The gas-Liquid-Solid etching (Vapor-Liquid-Solid Etch) method can enable the height-to-width ratio (High-aspect-ratio) of the prepared fin to be more than 45:1, and can ensure that the fin profile has good performance and profile defects do not occur, so that the performance and yield of the semiconductor device are improved.
The FinFET device of the invention also has the advantages due to the adoption of the manufacturing method. The electronic device of the invention also has the advantages because the FinFET device is adopted.
Example one
A method of fabricating a FinFET device of the present invention is described in detail below with reference to fig. 1 and 2a-2f, where fig. 1 shows a flow chart of a process for fabricating a FinFET device of the present invention; fig. 2a-2f show schematic cross-sectional views of structures obtained by implementing the method of fabricating a FinFET device of the present invention in sequence.
The invention provides a preparation method of a FinFET device, which mainly comprises the following steps of:
step S1: providing a semiconductor substrate, and sequentially forming a fin material layer and a seed layer on the semiconductor substrate;
step S2: forming a mask layer with an opening pattern on the seed layer, wherein the opening pattern exposes the seed layer;
step S3: forming an etching catalyst layer on the mask layer and the exposed seed layer to cover the mask layer and the seed layer;
step S4: performing chemical etching with the mask layer as a mask and the etching catalyst layer as an auxiliary to form an opening in the seed layer;
step S5: the fin material layer is etched in the openings by a gas-liquid-solid etching process to form spaced fins.
A detailed description of a specific embodiment of the method of fabricating a FinFET device of the present invention is provided below.
First, a first step is performed to provide a semiconductor substrate (not shown), on which a fin material layer 201 and a seed layer 202 are sequentially formed.
Specifically, as shown in fig. 2a, the semiconductor substrate in this step may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others.
In this embodiment the semiconductor substrate is selected from silicon.
A fin material layer 201 and a seed layer 202 are sequentially formed on the semiconductor substrate, wherein the fin material layer 201 includes three-five fin material layers.
The III-V group fin material layer has the following advantages:
(1) the process cost is relatively low, and compared with an SOI (silicon on insulator) sheet, the process cost is much lower;
(2) as the germanium and III-V group substrate is adopted, the mobility ratio of the device is higher, so that larger on-state current can be obtained, wherein the ratio of the on-state current to the off-state current can reach 106The above;
(3) the threshold voltage of the device can be effectively adjusted.
The fin material layer of the third-fifth group refers to a semiconductor material including a third main group IIIA and a fifth main group VA in the periodic table of chemical elements, such as InAs, but the type and composition of a specific fin can be selected according to actual needs.
The fin material layer may have a crystal structure, and the range of the lattice constant is not limited to a certain range of values.
Further, the fin material layer may be formed by Metal-organic Chemical Vapor Deposition (MOCVD).
The performance of the three-five group fin material layer formed by Metal-organic Chemical Vapor Deposition (MOCVD) is more excellent, and the performance and yield of the semiconductor device can be further improved.
In the present invention, the seed layer is an InP layer, but is not limited to the above example.
Further, an InAlAs layer may be further formed between the semiconductor substrate and the fin material layer, wherein the thickness of the InAlAs layer is much smaller than the thickness of the fin material layer.
And step two, forming a mask layer 203 with an opening pattern on the seed layer, wherein the opening pattern exposes the seed layer.
Specifically, as shown in fig. 2a, the mask layer 203 may be Hydrogen Silsesquioxane (HSQ) material in this step.
The masking layer 203 is patterned to form an opening pattern, for example, a patterned photoresist layer is formed, and the masking layer is etched using the photoresist layer as a mask.
In this step, the patterning method may be an electron beam patterning (E-beam patterning) method.
Step three, forming an etching catalyst layer 204 on the mask layer and the exposed seed layer to cover the mask layer and the seed layer;
specifically, as shown in fig. 2b, an etching catalyst layer 204 is formed on the mask layer 203 and the exposed seed layer to completely cover the mask layer and the seed layer, including the top and the sidewalls of the mask layer and the seed layer.
The etching catalyst layer 204 includes a metal layer, such as Au, but not limited to the above example.
Wherein, in this step, the etching catalyst layer 204 is formed by electron beam evaporation (E-beam evaporation), for example, a thin layer of metal Au is formed by an electron beam evaporation plating process.
And performing chemical etching with the mask layer as a mask and the etching catalyst layer as an auxiliary to form an opening in the seed layer.
Specifically, as shown in fig. 2c, H may be selected in the step 12SO4And H2O2As a reaction liquid to form the openings in the seed layer.
For example, H is selected2SO4And H2O2And performing a reaction as a reaction liquid to form the opening in the seed layer.
Wherein, the Etching temperature of the Metal-Assisted Chemical Etching method (Metal-Assisted Chemical Etching) may be room temperature.
Wherein the Metal-Assisted Chemical Etching method (Metal-Assisted Chemical Etching) has a large Etching selectivity ratio for the seed layer and the Metal layer, and does not affect the Metal layer during the process of removing the seed layer.
And step five, etching the fin material layer in the opening by a gas-liquid-solid etching method to form spaced fins.
Specifically, as shown in fig. 2d, wherein in the gas-Liquid-Solid etching (Vapor-Liquid-Solid Etch) method, the gas-Liquid-Solid includes water Vapor, Liquid water, and a Solid etching catalyst layer and InAs, Vapor is generated when heating, the Au nanoparticles of the etching catalyst layer freely move on the (001) surface of the InAs, and the aligned grooves (aligned grooves) are crystallographically etched (Etch) on the InAs surface to below the InAs surface as the gold nanoparticles move.
During which the InAs is dissolved by the catalyst and reacts with water vapor to form volatile compounds until the InAs is completely removed, which process has a higher selectivity than other processes.
The gas-Liquid-Solid etching (Vapor-Liquid-Solid Etch) method can enable the height-to-width ratio (High-aspect-ratio) of the prepared fin to be more than 45:1, and can ensure that the fin profile has good performance and profile defects do not occur, so that the performance and yield of the semiconductor device are improved.
The fins may include several rows spaced apart from each other, for example, the fins may be arranged in parallel, or the fins may be in a ring structure nested in each other, and the like, but is not limited to one.
And sixthly, removing the mask layer and the etching catalyst layer to expose the seed layer.
Specifically, as shown in fig. 2e, the removing method may be a method having a larger etching selectivity ratio than the semiconductor substrate.
And seventhly, removing the seed layer to expose the fins.
Specifically, as shown in FIG. 2f, HCl and H are passed through in this step3PO4And removing the seed layer to expose the fins.
HCl and H are selected for use in this step3PO4The etching selection ratio of the seed layer and the fin material layer is more than 1000, so that the seed layer can be completely removed, and the damage to the fin can be avoided.
For example, in the case where the seed layer is InP and the fins are InAs, HCl and H are selected3PO4Is much larger than 1000 a.
Wherein the HCl and H3PO4In a volume ratio of 1: 3.
This completes the description of the relevant steps of the method of fabricating a FinFET device according to an embodiment of the present invention. The method may further include the step of forming a transistor and other related steps, which are not described in detail herein. Besides the above steps, the preparation method of this embodiment may further include other steps in the above steps or between different steps, and these steps may be implemented by various processes in the current process, and are not described herein again.
In order to solve the problems in the prior art, the present invention provides a method for manufacturing a FinFET device, which includes forming a fin material layer, such as InAs, on a semiconductor substrate, forming a seed layer on the fin material layer, forming an Etching catalyst layer after patterning the seed layer, Etching the seed layer by a Metal-Assisted Chemical Etching method (Metal-Assisted Chemical Etching), and Etching the fin material layer by a gas-Liquid-Solid Etching (Vapor-Liquid-Solid Etching) method with the aid of the Etching catalyst layer to form spaced fins.
The gas-Liquid-Solid etching (Vapor-Liquid-Solid etching) method has a very large etching selection ratio for the etching catalyst layer and the fin material layer, so that a FinFET device with a larger height-to-width ratio (High-aspect-ratio) is prepared, and more importantly, the gas-Liquid-Solid etching (Vapor-Liquid-Solid etching) method can also ensure that the FinFET device with the larger height-to-width ratio (High-aspect-ratio) is prevented from being damaged, so that the prepared FinFET device has a good profile, and thus the performance and yield of the semiconductor device are improved.
Example two
The present invention also provides a FinFET device comprising:
a semiconductor substrate;
a fin located over the semiconductor substrate.
The fins may include several rows spaced apart from each other, for example, the fins may be arranged in parallel, or the fins may be in a ring structure nested in each other, and the like, but is not limited to one.
Wherein the FinFET device includes a semiconductor substrate, which may be at least one of the following: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others. In this embodiment the semiconductor substrate is selected from silicon.
Wherein the fins comprise a III-V material.
The three-five family material has the following advantages:
(1) the process cost is relatively low, and compared with an SOI (silicon on insulator) sheet, the process cost is much lower;
(2) because the germanium and III-V group substrate is adopted, the mobility ratio of the device is higher, so that larger on-state current can be obtained, wherein the ratio of the on-state current to the off-state current can reach more than 106;
(3) the threshold voltage of the device can be effectively adjusted.
The fin material layer of the third group and the fifth group refers to a semiconductor material including the third main group IIIA and the fifth main group VA in the periodic table of chemical elements, such as InAs, but the specific type and composition of the semiconductor material can be selected according to actual needs.
The fin material layer of the third-fifth group refers to a semiconductor material including a third main group IIIA and a fifth main group VA in the periodic table of chemical elements, such as InAs, but the type and composition of a specific fin can be selected according to actual needs.
The fin material layer may have a crystal structure, and the range of the lattice constant is not limited to a certain range of values.
Further, the fin material layer may be formed by Metal-organic Chemical Vapor Deposition (MOCVD).
The performance of the three-five group fin material layer formed by Metal-organic Chemical Vapor Deposition (MOCVD) is more excellent, and the performance and yield of the semiconductor device can be further improved.
The openings in the seed layer described in the present invention are formed by a Metal-Assisted Chemical Etching process (Metal-Assisted Chemical Etching).
The Metal-Assisted Chemical Etching method (Metal-Assisted Chemical Etching) in the invention comprises the following steps: forming a seed layer at the bottom of the Etching, then sequentially forming materials to be etched, and finally forming a Metal layer, and performing Chemical Etching on the premise that the Metal layer is used as a catalyst, wherein the Metal-Assisted Chemical Etching method (Metal-Assisted Chemical Etching) has high selectivity.
Specifically, the InP layer is used as the seed layer in the present invention, but is not limited to the above example.
Wherein the etching catalyst layer includes a metal layer, for example, Au is selected, but not limited to the example.
Wherein the Metal-Assisted Chemical Etching method (Metal-Assisted Chemical Etching) has a large Etching selectivity ratio for the seed layer and the Metal layer, and does not affect the semiconductor substrate and the Metal layer in the process of removing the seed layer.
Wherein, the Etching temperature of the Metal-Assisted Chemical Etching method (Metal-Assisted Chemical Etching) may be room temperature.
After Etching the seed layer by a Metal-Assisted Chemical Etching method (Metal-Assisted Chemical Etching), the fin material layer is etched by a gas-Liquid-Solid Etching (Vapor-Liquid-Solid Etch) method with the aid of the Etch catalyst layer to form spaced fins.
The gas-Liquid-Solid etching (Vapor-Liquid-Solid etching) method has a very large etching selection ratio for the etching catalyst layer and the fin material layer, so that a FinFET device with a larger height-to-width ratio (High-aspect-ratio) is prepared, and more importantly, the gas-Liquid-Solid etching (Vapor-Liquid-Solid etching) method can also ensure that the FinFET device with the larger height-to-width ratio (High-aspect-ratio) is prevented from being damaged, so that the prepared FinFET device has a good profile, and thus the performance and yield of the semiconductor device are improved.
The gas-Liquid-Solid etching (Vapor-Liquid-Solid Etch) method can enable the height-to-width ratio (High-aspect-ratio) of the prepared fin to be more than 45:1, and can ensure that the fin profile has good performance and profile defects do not occur, so that the performance and yield of the semiconductor device are improved.
EXAMPLE III
Another embodiment of the present invention provides an electronic device, which includes a FinFET device, the FinFET device being the FinFET device in the second embodiment or the FinFET device manufactured by the method for manufacturing a FinFET device in the first embodiment.
The electronic device may be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game machine, a television, a VCD, a DVD, a navigator, a camera, a video camera, a recording pen, an MP3, an MP4, a PSP, or an intermediate product having the FinFET device, for example: a mobile phone mainboard with the integrated circuit, and the like.
The electronic device also has the advantages described above due to the higher performance of the FinFET devices included.
Wherein figure 3 shows an example of a mobile telephone handset. The mobile phone handset 300 is provided with a display portion 302, operation buttons 303, an external connection port 304, a speaker 305, a microphone 306, and the like, which are included in a housing 301.
In the manufacturing process of the FinFET device, a fin material layer, such as InAs material, is formed on a semiconductor substrate, a seed layer is formed on the fin material layer, an Etching catalyst layer is formed after the seed layer is patterned, the seed layer is etched by a Metal-Assisted Chemical Etching method (Metal-Assisted Chemical Etching), and the fin material layer is etched by a gas-Liquid-Solid Etching (Vapor-Liquid-Solid Etching) method with the aid of the Etching catalyst layer to form spaced fins. The gas-Liquid-Solid etching (Vapor-Liquid-Solid etching) method has a very large etching selection ratio for the etching catalyst layer and the fin material layer, so that a FinFET device with a larger height-to-width ratio (High-aspect-ratio) is prepared, and more importantly, the gas-Liquid-Solid etching (Vapor-Liquid-Solid etching) method can also ensure that the FinFET device with the larger height-to-width ratio (High-aspect-ratio) is prevented from being damaged, so that the prepared FinFET device has a good profile, and thus the performance and yield of the semiconductor device are improved.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims (11)

1. A method of fabricating a FinFET device, the method comprising:
providing a semiconductor substrate, and sequentially forming a fin material layer and a seed layer on the semiconductor substrate;
forming a mask layer with an opening pattern on the seed layer, wherein the opening pattern exposes the seed layer;
forming an etching catalyst layer on the mask layer and the exposed seed layer to cover the mask layer and the seed layer;
performing chemical etching with the mask layer as a mask and the etching catalyst layer as an auxiliary to form an opening in the seed layer, and covering the etching catalyst layer on the surface of the fin material layer of the opening;
etching the fin material layer in the openings by a gas-liquid-solid etching process in which a gas-liquid-solid includes the etch catalyst layer of water vapor, liquid water, and solid to form spaced fins;
the method also includes the step of removing the seed layer to expose the fins.
2. The method of claim 1, wherein the step of chemically etching the seed layer comprises etching a solution comprising H2O2And H2SO4。
3. The method of claim 1, wherein the fin material layer comprises a group iii-v fin material layer.
4. The method of claim 1 or 3, wherein the fin material layer comprises an InAs layer.
5. The method of claim 1, wherein the seed layer is an InP layer.
6. The method of claim 1 or 5, wherein the seed layer is formed by chemical vapor deposition of metal organic compounds.
7. The method of claim 1, wherein the etching catalyst layer is formed by an electron beam evaporation method.
8. The method of claim 1, further comprising the step of removing the mask layer and the etch catalyst layer.
9. The process of claim 1, wherein the reaction is carried out by HCl and H3PO4And removing the seed layer.
10. A FinFET device prepared by the method of any of claims 1 to 9.
11. An electronic device, comprising the FinFET device of claim 10.
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