CN108766886A - A kind of forming method of fin formula field effect transistor structure - Google Patents
A kind of forming method of fin formula field effect transistor structure Download PDFInfo
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- CN108766886A CN108766886A CN201810509583.9A CN201810509583A CN108766886A CN 108766886 A CN108766886 A CN 108766886A CN 201810509583 A CN201810509583 A CN 201810509583A CN 108766886 A CN108766886 A CN 108766886A
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- effect transistor
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- 238000000034 method Methods 0.000 title claims abstract description 37
- 230000005669 field effect Effects 0.000 title claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 62
- 229910052751 metal Inorganic materials 0.000 claims abstract description 44
- 239000002184 metal Substances 0.000 claims abstract description 44
- 239000004065 semiconductor Substances 0.000 claims abstract description 41
- 239000010408 film Substances 0.000 claims abstract description 37
- 238000005530 etching Methods 0.000 claims abstract description 25
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims abstract description 20
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims abstract description 19
- 239000010409 thin film Substances 0.000 claims abstract description 17
- 239000003795 chemical substances by application Substances 0.000 claims abstract description 9
- 239000013528 metallic particle Substances 0.000 claims abstract description 6
- 239000003054 catalyst Substances 0.000 claims abstract description 5
- 239000002245 particle Substances 0.000 claims abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 20
- 229910052710 silicon Inorganic materials 0.000 claims description 20
- 239000010703 silicon Substances 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 9
- 238000004140 cleaning Methods 0.000 claims description 6
- 229910052709 silver Inorganic materials 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 229910052697 platinum Inorganic materials 0.000 claims description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 4
- 239000012459 cleaning agent Substances 0.000 claims description 3
- 239000008367 deionised water Substances 0.000 claims description 3
- 229910021641 deionized water Inorganic materials 0.000 claims description 3
- 238000003487 electrochemical reaction Methods 0.000 claims description 3
- 239000011888 foil Substances 0.000 claims 1
- 239000012528 membrane Substances 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 6
- 238000005260 corrosion Methods 0.000 description 6
- 230000007797 corrosion Effects 0.000 description 6
- 238000001259 photo etching Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 101100373011 Drosophila melanogaster wapl gene Proteins 0.000 description 1
- 229910003638 H2SiF6 Inorganic materials 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000003197 catalytic effect Effects 0.000 description 1
- 238000006555 catalytic reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- XLYOFNOQVPJJNP-ZSJDYOACSA-N heavy water Substances [2H]O[2H] XLYOFNOQVPJJNP-ZSJDYOACSA-N 0.000 description 1
- 239000002105 nanoparticle Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 210000004483 pasc Anatomy 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000011856 silicon-based particle Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- ZEFWRWWINDLIIV-UHFFFAOYSA-N tetrafluorosilane;dihydrofluoride Chemical compound F.F.F[Si](F)(F)F ZEFWRWWINDLIIV-UHFFFAOYSA-N 0.000 description 1
- 238000000101 transmission high energy electron diffraction Methods 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The invention discloses a kind of forming methods of fin formula field effect transistor structure, include the following steps：Step S01：Semi-conductive substrate is provided, deposits one layer of metallic film on the semiconductor substrate；Step S02：Patterned metal film；Step S03：Using hydrofluoric acid and hydrogen peroxide as etching agent, the semiconductor substrate surface to being covered with metal thin-film pattern carries out full wafer etching, and relatively raised fin is formed between virgin metal film pattern position；Step S04：It is developed across the gate structure of fin at the top of fin and side wall；Wherein, by using metallic particles as local cathode and catalyst, local microscopic electrochemical occurs between the semiconductor substrate particle as local anode to react, the semiconductor substrate surface of metal thin-film pattern lower zone is preferentially corroded to formation recess, to form relatively raised fin between virgin metal film pattern position.The present invention can accurately control the width and height of fin.
Description
Technical field
The present invention relates to integrated circuit technology manufacturing technology fields, more particularly, to a kind of fin formula field effect transistor
The forming method of structure.
Background technology
With the continuous development of semiconductor technology, traditional planar device has been difficult to the need for meeting people to high performance device
It asks.
Fin formula field effect transistor (Fin Field-Effect Transistor, FinFET) is a kind of solid type device,
Including the fin vertically formed on substrate and the stacking gate intersected with fin.This design can greatly improve circuit control and subtract
Few electric leakage mouth, while the lock that can also substantially shorten transistor is long.
Referring to Fig. 1, Fig. 1 is a kind of dimensional structure diagram of existing fin formula field effect transistor.As shown in Figure 1,
Fin formula field effect transistor structure includes：Positioned at the semiconductor substrate 10 of bottom, it is formed in the semiconductor substrate 10 convex
The fin 14 risen, fin 14 are obtained generally by being etched to semiconductor substrate 10；Dielectric layer 11 is covered in the semiconductor
A part for 10 surface and the side wall of fin 14；Gate structure 12 across in the fin 14 top and side wall, grid
Structure 12 includes gate dielectric layer (not shown) and the gate electrode (not shown) on gate dielectric layer.More about fin
The introduction of formula field-effect transistor please refers to the United States Patent (USP) of Publication No. " US7868380B2 ".
The forming method of existing fin formula field effect transistor fin is first to deposit hard mask layer on a semiconductor substrate, so
Self aligned Dual graphing (self-aligned double patterning, SADP) method is used afterwards, is sequentially etched hard
Mask layer and semiconductor substrate, eventually form fin.However, the fin formed in this way, not to its height and width
Good control；Also, it is formed by the edge of fin and the pattern lack of homogeneity of side wall.This can make fin formula field effect transistor
Threshold voltage shifts, and influences the stability of fin formula field effect transistor.
So be badly in need of finding a kind of forming method of new fin formula field effect transistor, it is of the existing technology to eliminate
It is insufficient.
Invention content
It is an object of the invention to overcome drawbacks described above of the existing technology, a kind of new fin field effect crystal is provided
The forming method of pipe structure.
To achieve the above object, technical scheme is as follows：
A kind of forming method of fin formula field effect transistor structure, includes the following steps：
Step S01：Semi-conductive substrate is provided, deposits one layer of metallic film on the semiconductor substrate；
Step S02：Patterned metal film；
Step S03：Using hydrofluoric acid and hydrogen peroxide as etching agent, to be covered with the semiconductor substrate surface of metal thin-film pattern into
Row full wafer etches, and relatively raised fin is formed between virgin metal film pattern position；
Step S04：It is developed across the gate structure of fin at the top of fin and side wall；
Wherein, by using metallic particles as local cathode and catalyst, with the semiconductor substrate as local anode
The reaction of local microscopic electrochemical occurs between particle, the semiconductor substrate surface of metal thin-film pattern lower zone is preferentially corroded
Recess is formed, to form relatively raised fin between virgin metal film pattern position.
Preferably, according to the relative mistake between semiconductor substrate surface and metal thin-film pattern surface on etch rate
It is different, the width and height dimension of metal thin-film pattern are determined, to accurately control the width and height of the required fin formed.
Preferably, it in step S03, is corroded using metallic film clean as etching terminal.
Preferably, the metallic film material deposition thickness is 50nm~200nm.
Preferably, further include the steps that being cleaned to semiconductor substrate surface before step S04.
Preferably, when being cleaned, using deionized water as cleaning agent.
Preferably, it is carried out in cleaning self-stopping technology has etched 0~2 minute.
Preferably, the semiconductor substrate is silicon substrate.
Preferably, the metallic film material is Au, Ag or Pt.
Preferably, the gate structure includes gate dielectric layer and gate electrode.
It can be seen from the above technical proposal that the present invention is by using hydrofluoric acid and hydrogen peroxide as etching agent, to being covered with metal
The semiconductor substrate surface of film pattern carries out full wafer etching, as local cathode and is urged using the metallic particles in metallic film
Agent, generation local microscopic electrochemical reacts between the substrate grain of the semiconductor substrate surface as local anode, will be golden
Belong to film pattern lower zone semiconductor substrate surface preferentially corrode formation recess, thus virgin metal film pattern position it
Between form relatively raised fin.The present invention can accurately control the width and height of fin, improve the row of fin on substrate
Cloth density；Meanwhile the present invention is compatible with conventional silicon substrate super large-scale integration manufacturing technology, has simply, convenient, the period is short
The characteristics of, reduce process costs.
Description of the drawings
Fig. 1 is a kind of dimensional structure diagram of existing fin formula field effect transistor；
Fig. 2 is a kind of forming method flow signal of fin formula field effect transistor structure of a preferred embodiment of the present invention
Figure；
Fig. 3~Fig. 8 is processing step signal when method according to fig. 2 forms a kind of fin formula field effect transistor structure
Figure；
Fig. 9 is the etching principle schematic of the present invention.
Specific implementation mode
Below in conjunction with the accompanying drawings, the specific implementation mode of the present invention is described in further detail.
It should be noted that in following specific implementation modes, when embodiments of the present invention are described in detail, in order to clear
Ground indicates the structure of the present invention in order to illustrate, spy does not draw to the structure in attached drawing according to general proportion, and has carried out part
Amplification, deformation and simplified processing, therefore, should avoid in this, as limitation of the invention to understand.
In specific implementation mode of the invention below, referring to Fig. 2, Fig. 2 is one kind of a preferred embodiment of the present invention
The forming method flow diagram of fin formula field effect transistor structure；Meanwhile Fig. 3~Fig. 8 is please referred to, Fig. 3~Fig. 8 is according to figure
2 method forms processing step schematic diagram when a kind of fin formula field effect transistor structure.As shown in Fig. 2, one kind of the present invention
The forming method of fin formula field effect transistor structure, it may include following steps：
Step S01：Semi-conductive substrate is provided, deposits one layer of metallic film on the semiconductor substrate.
Please refer to Fig. 3.First, the general PVD process manufacturing method of industry can be used, deposit on a semiconductor substrate 100
Form one layer of metallic film 101.Wherein,
Silicon substrate etc. can be used in semiconductor substrate 100.The present embodiment is illustrated by taking silicon substrate as an example.
Au, Ag or Pt etc. can be used in 101 material of metallic film.The present embodiment is illustrated by taking Ag as an example.
The deposition thickness of 101 material of metallic film is 50nm~200nm.
Step S02：Patterned metal film.
Please refer to Fig. 4 and Fig. 5.Then, can be used the general technique manufacturing method of industry carry out photoetching, development and etching,
The techniques such as cleaning, including elder generation is in 101 surface coating photoresist of metallic film；Then, by photoetching, development, the photoetching to coating
Glue is patterned, and forms photoetching offset plate figure 102；Next, continuing with patterned photoresist 102 to be mask, to photoresist
101 material of metallic film of 102 lower section of figure performs etching, and forms corresponding metal thin-film pattern 101 '；It later, will be remaining
Photoresist 102 removes, and is cleaned.
Step S03：Using hydrofluoric acid and hydrogen peroxide as etching agent, to be covered with the semiconductor substrate surface of metal thin-film pattern into
Row full wafer etches, and relatively raised fin is formed between virgin metal film pattern position.
Please refer to Fig. 6.Then, hydrofluoric acid (HF) and hydrogen peroxide (H are passed through2O2) it is used as etching agent, to being covered with metallic film figure
The semiconductor substrate surface of shape 101 ' carries out full wafer etching (corrosion).It includes lining that the object that (corrosion) is directed to is etched in the present embodiment
Bottom silicon and the Ag films for being covered in substrate silicon surface.
In etching process, the height of metal 101 ' is because by hydrofluoric acid (HF) and hydrogen peroxide (H2O2) corrosiveness and it is continuous
It reduces；Meanwhile etching speed of the substrate silicon below metal 101 ' because of etch rate much larger than 101 ' both side surface substrate silicon of metal
Rate, so that constantly sinking and forming recess.
In this way after over etching (corrosion), relatively raised fin 103 is just formed between virgin metal film pattern position
(please also refer to Fig. 7).
When silicon substrate to being covered with metal carries out full wafer etching, it is corroded using metallic film clean as etching terminal；
Therefore, once metallic film is corroded totally, just stop etching technics.
The present invention manufacture fin formula field effect transistor basic principle be, substrate silicon surface deposition metal Ag particles and its
Region, can occur the local cathode of local microscopic electrochemical reaction as silicon face, and become local cathode and local
Anode (silicon particle of substrate surface and its region, can as occur local microscopic electrochemical reaction local anode) it
Between charge transfer center；Simultaneously as the silver nano-grain formed has apparent catalytic activity for corrosion reaction, it can profit
It uses Argent grain as catalyst, thus corrosion rate can be greatly increased.And the hole needed for pasc reaction can be by H2O2In silver
Reduction at nano particle obtains.Total reaction equation is：
Si+H2O2+ 6HF=2H2O+H2SiF6+H2
Reaction process can be explained by Fig. 9：
1) at the surface metal (such as Au, Ag, Pt), oxidant H2O2(Ox) (Red) is restored by preferential catalysis, generates hole
(+)；
2) hole is injected by metallic particles (Metal) in the silicon contacted (Si)；
3) in the interface that metal and silicon contact, silica is melted into silica by injected holes, and then, silica is molten
Solution is in HF solution；
4) due to the local hole solubility highest that metal is contacted with silicon, corrosion rate is also most fast.Therefore, with metal contact zone
The silicon in domain compares the silicon in no plated region, and the speed being corroded is faster.In this way, can will be below metal thin-film pattern
The substrate silicon surface in region preferentially corrodes formation recess, to form relatively raised fin between virgin metal film pattern position
Portion 103.
Compared with prior art, the fin formula field effect transistor of above method manufacture using the present invention, can be according to semiconductor
Relative different between substrate surface and metal thin-film pattern surface on etch rate, determine metal thin-film pattern width and
Height dimension, thus the width and height of the required fin formed can be accurately controlled, improve the arrangement density of fin on substrate；
The technique of the present invention can be compatible with conventional silicon substrate super large-scale integration manufacturing technology simultaneously, has simply, and convenient, the period is short
The characteristics of, reduce process costs.
Step S04：It is developed across the gate structure of fin at the top of fin and side wall.
Please refer to Fig. 7.Then, it needs to clean semiconductor substrate surface, to remove semiconductor substrate surface not phase
The residual substance of prestige keeps the cleaning of semiconductor substrate surface.
It when being cleaned, can be used deionized water as cleaning agent, full wafer cleaning carried out to semiconductor substrate surface.
As preferred embodiment, above-mentioned cleaning answers self-stopping technology etching (by HF and H2O2After etching agent takes out) rise 0~
It is carried out in 2 minutes.
After washing with water, that is, forming fin formula field effect transistor has the fin 103 of strict width and height.
Please refer to Fig. 8.Next, the material and technique manufacturing method of the general formation grid of industry can be used, above-mentioned
103 surface deposition grid material of device and fin, and gate structure 104 is formed by photoetching, etching.Gate structure 104 can wrap
Include the gate dielectric layer positioned at lower layer and the gate electrode on gate dielectric layer.
In addition, after completing the procedure, other techniques to form cmos device can be continued to execute, these processing steps can
To be formed using method familiar to those skilled in the art, details are not described herein.
To sum up, the present invention is by the way that using hydrofluoric acid and hydrogen peroxide as etching agent, the semiconductor to being covered with metal thin-film pattern serves as a contrast
Bottom surface carries out full wafer etching, and local cathode and catalyst are used as using the metallic particles in metallic film, and positive as local
The reaction of local microscopic electrochemical occurs between the substrate grain of the semiconductor substrate surface of pole, by metal thin-film pattern lower zone
Semiconductor substrate surface preferentially corrode formation recess, to form relatively raised fin between virgin metal film pattern position
Portion.The present invention can accurately control the width and height of fin, improve the arrangement density of fin on substrate；Meanwhile the present invention
It is compatible with conventional silicon substrate super large-scale integration manufacturing technology, have simple, convenient, period short feature reduces technique
Cost.
Above-described to be merely a preferred embodiment of the present invention, the embodiment is not to be protected to limit the patent of the present invention
Range, therefore equivalent structure variation made by every specification and accompanying drawing content with the present invention are protected, similarly should be included in
In protection scope of the present invention.
Claims (10)
1. a kind of forming method of fin formula field effect transistor structure, which is characterized in that include the following steps：
Step S01：Semi-conductive substrate is provided, deposits one layer of metallic film on the semiconductor substrate；
Step S02：Patterned metal film；
Step S03：Using hydrofluoric acid and hydrogen peroxide as etching agent, the semiconductor substrate surface to being covered with metal thin-film pattern carries out whole
Piece etches, and relatively raised fin is formed between virgin metal film pattern position；
Step S04：It is developed across the gate structure of fin at the top of fin and side wall；
Wherein, by using metallic particles as local cathode and catalyst, with the semiconductor substrate particle as local anode
Between occur local microscopic electrochemical reaction, the semiconductor substrate surface of metal thin-film pattern lower zone is preferentially corroded to be formed
Recess, to form relatively raised fin between virgin metal film pattern position.
2. the forming method of fin formula field effect transistor structure according to claim 1, which is characterized in that according to semiconductor
Relative different between substrate surface and metal thin-film pattern surface on etch rate, determine metal thin-film pattern width and
Height dimension, to accurately control the width and height of the required fin formed.
3. the forming method of fin formula field effect transistor structure according to claim 1, which is characterized in that in step S03,
It is corroded using metallic film clean as etching terminal.
4. the forming method of fin formula field effect transistor structure according to claim 1, which is characterized in that the metal foil
Membrane material deposition thickness is 50nm~200nm.
5. the forming method of fin formula field effect transistor structure according to claim 1, which is characterized in that in step S04
Before, further include the steps that being cleaned to semiconductor substrate surface.
6. the forming method of fin formula field effect transistor structure according to claim 5, which is characterized in that cleaned
When, using deionized water as cleaning agent.
7. the forming method of fin formula field effect transistor structure according to claim 5, which is characterized in that cleaning self-stopping technology
It is carried out in 0~2 minute etched.
8. the forming method of the fin formula field effect transistor structure according to claim 1-7 any one, which is characterized in that
The semiconductor substrate is silicon substrate.
9. the forming method of the fin formula field effect transistor structure according to claim 1-7 any one, which is characterized in that
The metallic film material is Au, Ag or Pt.
10. the forming method of fin formula field effect transistor structure according to claim 1, which is characterized in that the grid
Structure includes gate dielectric layer and gate electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810509583.9A CN108766886A (en) | 2018-05-24 | 2018-05-24 | A kind of forming method of fin formula field effect transistor structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810509583.9A CN108766886A (en) | 2018-05-24 | 2018-05-24 | A kind of forming method of fin formula field effect transistor structure |
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| Publication Number | Publication Date |
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| CN108766886A true CN108766886A (en) | 2018-11-06 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080073723A1 (en) * | 2006-09-22 | 2008-03-27 | Willy Rachmady | Selective anisotropic wet etching of workfunction metal for semiconductor devices |
| CN103145090A (en) * | 2011-12-06 | 2013-06-12 | 林清富 | Technology for manufacturing large-area thin monocrystalline silicon |
| CN106328513A (en) * | 2015-07-02 | 2017-01-11 | 中芯国际集成电路制造(上海)有限公司 | Method of forming semiconductor structure |
| CN107706113A (en) * | 2016-08-09 | 2018-02-16 | 中芯国际集成电路制造(上海)有限公司 | A kind of FinFET and preparation method, electronic installation |
-
2018
- 2018-05-24 CN CN201810509583.9A patent/CN108766886A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080073723A1 (en) * | 2006-09-22 | 2008-03-27 | Willy Rachmady | Selective anisotropic wet etching of workfunction metal for semiconductor devices |
| CN103145090A (en) * | 2011-12-06 | 2013-06-12 | 林清富 | Technology for manufacturing large-area thin monocrystalline silicon |
| CN106328513A (en) * | 2015-07-02 | 2017-01-11 | 中芯国际集成电路制造(上海)有限公司 | Method of forming semiconductor structure |
| CN107706113A (en) * | 2016-08-09 | 2018-02-16 | 中芯国际集成电路制造(上海)有限公司 | A kind of FinFET and preparation method, electronic installation |
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Application publication date: 20181106 |