CN107623035B - Semiconductor device, preparation method and electronic device - Google Patents
Semiconductor device, preparation method and electronic device Download PDFInfo
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- CN107623035B CN107623035B CN201610561428.2A CN201610561428A CN107623035B CN 107623035 B CN107623035 B CN 107623035B CN 201610561428 A CN201610561428 A CN 201610561428A CN 107623035 B CN107623035 B CN 107623035B
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Abstract
The invention relates to a semiconductor device, a preparation method and an electronic device. Providing a semiconductor substrate, and forming a sacrificial layer and a mask layer on the semiconductor substrate; patterning the mask layer and the sacrificial layer to form a first groove and a second groove which are spaced from each other in the mask layer and the sacrificial layer, wherein the transverse size of the first groove is smaller than that of the second groove; epitaxially growing a semiconductor material layer in the first groove to form a first fin, and epitaxially growing the semiconductor material layer in the second groove to form a second fin, wherein the height of the second fin is less than that of the first fin; removing the mask layer and the sacrificial material layer to expose the first fin and the second fin; trimming the second fin such that a lateral dimension of the second fin is equal to a lateral dimension of the first fin. The height of the fin can be better controlled by the method.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a preparation method and an electronic device.
Background
With the continuous development of semiconductor technology, the performance of integrated circuits is improved mainly by the continuous reduction of the size of integrated circuit devices to increase the speed thereof. Currently, the semiconductor industry has progressed to nanotechnology process nodes due to demands for high device density, high performance, and low cost, and the fabrication of semiconductor devices is limited by various physical limitations.
As CMOS device dimensions continue to shrink, challenges from manufacturing and design aspects have prompted the development of three-dimensional designs such as fin field effect transistors (finfets). Compared with the existing planar transistor, the FinFET is an advanced semiconductor device for process nodes of 20nm and below, can effectively control the short channel effect which is difficult to overcome due to the fact that the device is scaled down, can also effectively improve the density of a transistor array formed on a substrate, and meanwhile, a grid electrode in the FinFET is arranged around a fin (a fin-shaped channel), so that static electricity can be controlled from three surfaces, and the performance in the aspect of static electricity control is more outstanding.
In the FinFET device, fins with different heights need to be prepared in an NMOS FinFET device and a PMOS FinFET device to match the NMOS FinFET device and the PMOS FinFET device, but the current method for preparing fins with different heights is not only cumbersome but also difficult to control the heights of the fins.
In addition, the OFF-state current (I) of the scallop-Shaped FinFET (S-FinFET)off) The absolute value aspect proves to have better performance, and therefore how to more efficiently fabricate the S-FinFET device becomes a problem to be solved at present.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In order to overcome the problems existing at present, the invention provides a method for manufacturing a semiconductor device, which comprises the following steps:
providing a semiconductor substrate, and forming a sacrificial layer and a mask layer on the semiconductor substrate;
patterning the mask layer and the sacrificial layer to form a first groove and a second groove which are spaced from each other in the mask layer and the sacrificial layer, wherein the transverse size of the first groove is smaller than that of the second groove;
epitaxially growing a semiconductor material layer in the first groove to form a first fin, and epitaxially growing the semiconductor material layer in the second groove to form a second fin, wherein the height of the second fin is less than that of the first fin;
removing the mask layer and the sacrificial material layer to expose the first fin and the second fin;
trimming the second fin such that a lateral dimension of the second fin is equal to a lateral dimension of the first fin.
Optionally, the first groove comprises a first sub-groove and a second sub-groove which are arranged alternately from top to bottom, and the transverse opening size of the second sub-groove is larger than that of the first sub-groove;
the second groove comprises a third sub-groove and a fourth sub-groove which are alternately arranged from top to bottom, and the transverse opening size of the fourth sub-groove is larger than that of the third sub-groove;
and the transverse opening size of the third sub-groove is larger than that of the first sub-groove, and the transverse opening size of the fourth sub-groove is larger than that of the second sub-groove.
Optionally, epitaxially growing the semiconductor material layer to form a first sub-fin in the first sub-groove and a second sub-fin in the second sub-groove to form the first fin; simultaneously forming a third sub-fin in the third sub-groove and a fourth sub-fin in the fourth sub-groove to form the second fin;
trimming the second fin such that the lateral dimension of the third sub-fin is equal to the lateral dimension of the first sub-fin and the lateral dimension of the fourth sub-fin is equal to the lateral dimension of the second sub-fin.
Optionally, in a cross-sectional view along the first groove and the second groove in a direction perpendicular to the surface of the semiconductor substrate, the first sub-groove is square, the third sub-groove is square, the second sub-groove is elliptical or fan-shaped, and the fourth sub-groove is elliptical or fan-shaped.
Optionally, the step of forming the first groove and the second groove comprises:
anisotropically etching the mask layer and the sacrificial layer to form the first sub-groove and the second sub-groove in the mask layer and on the top of the sacrificial layer, and simultaneously form the third sub-groove and the fourth sub-groove, continuing to perform the anisotropic etching to form the first sub-groove and the second sub-groove which are alternately arranged, and to form the third sub-groove and the fourth sub-groove which are alternately arranged;
wherein, the first recess least significant end is first sub-recess, the least significant end of second recess is third sub-recess.
Optionally, a mixed pulse etching process is selected to etch the first and second grooves.
Optionally, the epitaxial rate of the semiconductor material layer decreases with increasing recess opening.
Optionally, a step of passivating the sidewalls of the first and second grooves is further included before epitaxially growing the semiconductor material layer to form a passivation layer on the sidewalls of the first and second grooves.
Optionally, the semiconductor substrate includes an NMOS region in which the first fin is formed and a PMOS region in which the second fin is formed.
Optionally, a protective layer is formed on the first fins to cover the first fins when the second fins are trimmed, and the protective layer is removed after the trimming.
Optionally, the method further comprises the step of etching back the first fin and the second fin to a target size.
The invention discloses a semiconductor device, comprising:
a semiconductor substrate;
the first fin is positioned on the semiconductor substrate;
the second fin is positioned on the semiconductor substrate, and the height of the second fin is smaller than that of the first fin;
the first fins comprise first sub-fins and second sub-fins which are alternately arranged from top to bottom; the second fin comprises a first sub-fin and a second sub-fin which are alternately arranged from top to bottom, wherein the transverse size of the second sub-fin is larger than that of the first sub-fin.
Optionally, in a cross-sectional view of the first fin and the second fin in a direction perpendicular to the surface of the semiconductor substrate, the first sub-fin has a square shape, and the second sub-fin has an oval shape or a fan shape.
The invention discloses an electronic device which comprises the semiconductor device.
In order to solve the above problems in the prior art, the present invention provides a method for manufacturing a semiconductor device, in which fins with different heights are formed in order to match the performance of the device, grooves with different opening sizes are formed in the sacrificial layer during the formation of the fins, and then the semiconductor material layer is epitaxially grown in the grooves, and fins with different heights are formed in the grooves with different opening sizes due to different epitaxial speeds of the semiconductor material layer due to different opening sizes.
The semiconductor device of the present invention has the same advantages as described above because of the above manufacturing method. The electronic device of the present invention also has the above advantages because of the use of the above semiconductor device.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
FIG. 1 shows a flow chart of a process for fabricating a semiconductor device according to the present invention;
FIG. 2 is a schematic cross-sectional view showing a structure obtained by implementing the method for manufacturing a semiconductor device according to the present invention;
FIG. 3 is a schematic cross-sectional view showing a structure obtained by implementing the method for manufacturing a semiconductor device according to the present invention;
FIG. 4 is a schematic cross-sectional view showing a structure obtained by implementing the method for manufacturing a semiconductor device according to the present invention;
FIG. 5 is a schematic cross-sectional view showing a structure obtained by implementing the method for manufacturing a semiconductor device according to the present invention;
FIG. 6 is a schematic cross-sectional view showing a structure obtained by implementing the method for manufacturing a semiconductor device according to the present invention;
FIG. 7 is a schematic sectional view showing a structure obtained by implementing the method for manufacturing a semiconductor device according to the present invention;
FIG. 8 is a schematic sectional view showing a structure obtained by implementing the method for manufacturing a semiconductor device according to the present invention;
FIG. 9 is a schematic sectional view showing a structure obtained by implementing the method for manufacturing a semiconductor device according to the present invention;
FIG. 10 is a schematic sectional view showing a structure obtained by implementing the method for manufacturing a semiconductor device according to the present invention;
FIG. 11 shows a schematic view of an electronic device according to an embodiment of the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relationship terms such as "under …", "under …", "below", "under …", "above …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below …" and "below …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
In order to solve the above problems in the current process, the present invention provides a method for manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate, and forming a sacrificial layer and a mask layer on the semiconductor substrate;
patterning the mask layer and the sacrificial layer to form a first groove and a second groove which are spaced from each other in the mask layer and the sacrificial layer, wherein the transverse size of the first groove is smaller than that of the second groove;
epitaxially growing a semiconductor material layer in the first groove to form a first fin, and epitaxially growing the semiconductor material layer in the second groove to form a second fin, wherein the height of the second fin is less than that of the first fin;
removing the mask layer and the sacrificial material layer to expose the first fin and the second fin;
trimming the second fin such that a lateral dimension of the second fin is equal to a lateral dimension of the first fin.
The first groove comprises a first sub-groove and a second sub-groove which are alternately arranged from top to bottom, and the opening size of the second sub-groove is larger than that of the first sub-groove; the second groove comprises a third sub-groove and a fourth sub-groove which are alternately arranged from top to bottom, and the opening size of the third sub-groove is larger than that of the fourth sub-groove; the opening size of the first sub-groove is smaller than that of the third sub-groove, and the opening size of the second sub-groove is smaller than that of the fourth sub-groove;
epitaxially growing a semiconductor material layer in the first groove, forming a first sub-fin in the first sub-groove, and forming a second sub-fin in the second sub-groove to form the first fin;
simultaneously epitaxially growing the semiconductor material layer in the second groove, forming a third sub-fin in the third sub-groove, and forming a fourth sub-fin in the fourth sub-groove to form the second fin;
trimming the second fin such that the lateral dimension of the third sub-fin is equal to the lateral dimension of the first sub-fin and the lateral dimension of the fourth sub-fin is equal to the lateral dimension of the second sub-fin.
In the invention, a mixed pulse etching process is selected to etch the first groove and the second groove.
The hybrid pulse etching process is an etching mode in a plasma processing system, and specifically, the etching parameters can be selected according to actual needs and are not limited to a certain value range.
Further, the semiconductor substrate includes an NMOS region and a PMOS region, and in order to match the performance of the device, the height of the fin in the NMOS device and the height of the fin in the PMOS device are not the same, e.g., the height of the fin in the NMOS device is less than the height of the fin in the PMOS device.
Forming the first fin in the PMOS region and the second fin in the NMOS region.
Wherein, in a cross-sectional view of the first and second grooves in a direction perpendicular to the surface of the semiconductor substrate, the first and third sub-grooves are square, and the second and fourth sub-grooves are oval or fan-shaped.
Specifically, the first sub-groove and the third sub-groove may have a square and cylindrical structure, that is, they are uniformly maintained by the upper and lower sizes, and the opening size of the first sub-groove is smaller than that of the third sub-groove, and the opening size of the second sub-groove is smaller than that of the fourth sub-groove.
The second and fourth sub-grooves may have an elliptical cubic structure or a sectoral (scanlop-Shaped) cubic structure.
Optionally, the second and fourth sub-grooves are of elliptical pyramidal or fan-Shaped (pyramidal) pyramidal configuration, but the examples are exemplary only, as long as the basic repeating units in the first and second grooves are substantially in the shape of a volumetric flask or similar in a chemical container.
Wherein off-state current (I) in the Fin-Shaped Fin (Scoop-Shaped Fin) and Fin-Shaped FinFET (S-FinFET) devicesoff) The absolute value is greatly improved, so that the performance and the yield of the semiconductor device are improved.
In order to form the fins with different heights and to control the heights more easily, grooves with different opening sizes are formed in the sacrificial layer, and a semiconductor material layer is epitaxially grown in the grooves, wherein the semiconductor material layer comprises a SiGe layer, the epitaxial rate of the SiGe layer is reduced along with the increase of the opening of the groove, the fins with different heights can be obtained due to the difference of the openings, and the method is simpler, is easier to control and does not increase the process cost.
Wherein the step of forming the first and second grooves comprises:
anisotropically etching the mask layer and the sacrificial layer to form the first sub-groove, the second sub-groove, the third sub-groove and the fourth sub-groove in the mask layer and on the top of the sacrificial layer, and cyclically performing the anisotropic etching to form the first sub-groove and the second sub-groove which are alternately arranged, and to form the third sub-groove and the fourth sub-groove which are alternately arranged to form the first groove and the second groove.
Wherein, the first recess least significant end is first sub-recess, the least significant end of second recess is third sub-recess.
Forming a protective layer on the first fins to cover the first fins while trimming the second fins, and removing the protective layer after trimming.
The method still further includes the step of etching back the first fin and the second fin to a target size.
In order to solve the above problems in the prior art, the present invention provides a method for manufacturing a semiconductor device, in which fins with different heights are formed in order to match the performance of the device, grooves with different opening sizes are formed in the sacrificial layer during the formation of the fins, and then a semiconductor material layer is epitaxially grown in the grooves, and fins with different heights are formed in the grooves with different opening sizes due to different epitaxial speeds of the semiconductor material layer due to different opening sizes, so that the heights of the fins can be better controlled by the method, and simultaneously the profiles of the first groove and the second groove can be better controlled by the method, so as to form a fan-Shaped Fin (S-Shaped Fin) device and a fan-Shaped FinFET (S-Shaped FinFET), causing off-state current (I) of the S-FinFET deviceoff) The absolute value is greatly improved, so that the performance and the yield of the semiconductor device are improved.
The semiconductor device of the present invention has the same advantages as described above because of the above manufacturing method. The electronic device of the present invention also has the above advantages because of the use of the above semiconductor device.
Example one
A method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings, and fig. 1 shows a flow chart of a manufacturing process of the semiconductor device according to the present invention; FIG. 2 is a schematic cross-sectional view showing a structure obtained by implementing the method for manufacturing a semiconductor device according to the present invention; FIG. 3 is a schematic cross-sectional view showing a structure obtained by implementing the method for manufacturing a semiconductor device according to the present invention; FIG. 4 is a schematic cross-sectional view showing a structure obtained by implementing the method for manufacturing a semiconductor device according to the present invention; FIG. 5 is a schematic cross-sectional view showing a structure obtained by implementing the method for manufacturing a semiconductor device according to the present invention; FIG. 6 is a schematic cross-sectional view showing a structure obtained by implementing the method for manufacturing a semiconductor device according to the present invention; FIG. 7 is a schematic sectional view showing a structure obtained by implementing the method for manufacturing a semiconductor device according to the present invention; FIG. 8 is a schematic sectional view showing a structure obtained by implementing the method for manufacturing a semiconductor device according to the present invention; FIG. 9 is a schematic sectional view showing a structure obtained by implementing the method for manufacturing a semiconductor device according to the present invention; FIG. 10 is a schematic sectional view showing a structure obtained by implementing the method for manufacturing a semiconductor device according to the present invention; fig. 11 is a schematic cross-sectional view showing a structure obtained by implementing the method for manufacturing a semiconductor device according to the present invention.
The invention provides a preparation method of a semiconductor device, as shown in figure 1, the main steps of the preparation method comprise:
step S1: providing a semiconductor substrate, and forming a sacrificial layer and a mask layer on the semiconductor substrate;
step S2: patterning the mask layer and the sacrificial layer to form a first groove and a second groove which are spaced from each other in the mask layer and the sacrificial layer, wherein the transverse size of the first groove is smaller than that of the second groove;
step S3: epitaxially growing a semiconductor material layer in the first groove to form a first fin, and epitaxially growing the semiconductor material layer in the second groove to form a second fin, wherein the height of the second fin is less than that of the first fin;
step S4: removing the mask layer and the sacrificial material layer to expose the first fin and the second fin;
step S5: trimming the second fin such that a lateral dimension of the second fin is equal to a lateral dimension of the first fin.
Next, a detailed description will be given of a specific embodiment of the method for manufacturing a semiconductor device of the present invention.
First, step one is performed to provide a semiconductor substrate 201 on which a sacrificial layer 203 and a mask layer 204 are formed.
Specifically, as shown in fig. 2, the semiconductor substrate in this step may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others.
In this embodiment the semiconductor substrate 201 is selected from silicon.
Wherein the semiconductor substrate includes an NMOS region and a PMOS region to form different devices in a subsequent step.
An etch stop layer 202 is then formed on the semiconductor substrate to act as a stop layer for etching the mask layer and the sacrificial layer in subsequent steps.
The etching stop layer 202 may be an oxide layer, for example, the etching stop layer 202 may be formed by a deposition method, such as a chemical vapor deposition method, an atomic layer deposition method, or formed by thermally oxidizing the surface of the semiconductor substrate, which is not described herein again.
Further, the step may further include a step of performing ion implantation to form a well in the semiconductor substrate, wherein the implanted ion species and the implantation method may be methods commonly used in the art, and are not described herein again.
The sacrificial layer has a larger etching selection ratio with respect to the epitaxially grown semiconductor material layer and has a larger etching selection ratio with respect to the etch stop layer 202, so as to avoid damage to the etch stop layer 202 and the semiconductor material layer.
In this embodiment, Si is used as the sacrificial layer, but the present invention is not limited to this example.
The mask layer 204 is a hard mask layer, such as an oxide or a nitride, but not limited to a specific one.
Step two, etching the mask layer and the sacrificial layer to form a plurality of first grooves and a plurality of second grooves which are spaced from each other in the mask layer and the sacrificial layer, wherein the first grooves comprise first sub-grooves and second sub-grooves which are alternately arranged from top to bottom, and the opening size of the second sub-grooves is larger than that of the first sub-grooves; the second groove comprises a third sub-groove and a fourth sub-groove which are alternately arranged from top to bottom, and the opening size of the fourth sub-groove is larger than that of the third sub-groove; and the opening size of the third sub-groove is larger than that of the first sub-groove, and the opening size of the fourth sub-groove is larger than that of the second sub-groove.
Specifically, the etching method comprises the following steps:
step 1: anisotropically etching the mask layer and the sacrificial layer to form the first sub-groove, the second sub-groove, the third sub-groove and the fourth sub-groove in the mask layer and on the top of the sacrificial layer, as shown in fig. 3;
step 2: and performing the anisotropic etching cyclically to form the first sub-grooves and the second sub-grooves which are alternately arranged, and to form the third sub-grooves and the fourth sub-grooves which are alternately arranged to form the first grooves and the second grooves, as shown in fig. 4, wherein the lowest end of the first grooves is the first sub-grooves, and the lowest end of the second grooves is the third sub-grooves.
Specifically, in the present invention, a mixed pulse etching process is selected to etch the first groove and the second groove.
The hybrid pulse etching process is an etching mode in a plasma processing system, and specifically, the etching parameters can be selected according to actual needs and are not limited to a certain value range.
In particular, Cl-based is selected in this step2The first recess and the second recess are formed by etching in the etching atmosphere of (1). Further, the semiconductor substrate includes an NMOS region and a PMOS region, and in order to match the performance of the device, the height of the fin in the NMOS device and the height of the fin in the PMOS device are not the same, e.g., the height of the fin in the NMOS device is less than the height of the fin in the PMOS device.
Forming the first fin in the PMOS region and the second fin in the NMOS region.
Wherein, in a cross-sectional view of the first and second grooves in a direction perpendicular to the surface of the semiconductor substrate, the first and third sub-grooves are square, and the second and fourth sub-grooves are oval or fan-shaped.
Specifically, the first sub-groove and the third sub-groove may have a square and cylindrical structure, that is, they are consistent in size from top to bottom, and the lateral opening size of the first sub-groove is smaller than that of the third sub-groove, and the lateral opening size of the second sub-groove is smaller than that of the fourth sub-groove.
The second and fourth sub-grooves may have an oval cubic structure or a fan-Shaped (Scallop-Shaped) cubic structure, but the example is only exemplary as long as the basic repeating unit in the first and second grooves has a substantially volumetric flask-Shaped structure or a similar Shaped structure in a chemical container.
Wherein off-state current (I) of the sectored Fin (Scoop-Shaped Fin) and sectored FinFET (S-FinFET) devicesoff) The absolute value is greatly improved, so that the performance and the yield of the semiconductor device are improved.
And performing a third step of passivating the side walls of the first groove and the second groove to form a passivation layer on the side walls of the first groove and the second groove.
Specifically, a passivation layer is formed on inner sidewalls of the first and second grooves by oxidation or the like to protect the profiles of the first and second grooves.
The oxidation method may be any method commonly used in the art, and is not limited to any one.
And a fourth step is executed, wherein a semiconductor material layer is epitaxially grown in the first groove to form a first fin 205, and the semiconductor material layer is epitaxially grown in the second groove to form a second fin 206, wherein the height of the second fin is smaller than that of the first fin.
Specifically, as shown in fig. 5, in this step, the semiconductor material layer includes a SiGe layer, and the epitaxial rate of the semiconductor material layer decreases with the increase of the recess opening, for example, the epitaxial rate of the SiGe layer is inversely proportional to the size of the recess opening, and the larger the recess opening, the smaller the epitaxial growth rate and the smaller the formation height.
Epitaxially growing a semiconductor material layer in the first groove, forming a first sub-fin in the first sub-groove, and forming a second sub-fin in the second sub-groove to form the first fin;
and epitaxially growing the semiconductor material layer in the second groove, forming a third sub-fin in the third sub-groove, and forming a fourth sub-fin in the fourth sub-groove to form the second fin.
In order to form the fins with different heights and to control the heights more easily, grooves with different opening sizes are formed in the sacrificial layer, and a semiconductor material layer is epitaxially grown in the grooves, wherein the semiconductor material layer comprises a SiGe layer, the epitaxial rate of the SiGe layer is reduced along with the increase of the opening of the groove, and the fins with different heights can be obtained.
And step five, removing the mask layer and the sacrificial material layer to expose the first fin and the second fin.
Specifically, as shown in fig. 6, a method with a large etching selectivity is selected for etching at this step, and dry etching, Reactive Ion Etching (RIE), ion beam etching, or plasma etching may be selected in an embodiment of the present invention.
In this step, the sacrificial layer is etched with an O-based etchant, in one embodiment of the present invention, O is used2May also be added simultaneously with other small amounts of gases such as CF4、CO2、N2The etching pressure can be 50-200mTorr, preferably 100-150mTorr, power 200-600W, the etching time in the present invention is 5-80s, more preferably 10-60s, while the larger gas flow is selected in the present invention, preferably, O in the present invention2The flow rate of (b) is 30 to 300sccm, more preferably 50 to 100 sccm.
Or in the step, the sacrificial layer is removed by wet etching, and hydrofluoric acid (HF) or diluted hydrofluoric acid (DHF) is selected for etching, wherein the composition of HF: H2O is 1:2-1:10, so as to remove the sacrificial layer, and the etching temperature is 20-25 ℃.
And executing a sixth step of trimming the second fin to enable the transverse size of the third sub-fin to be equal to that of the first sub-fin and enable the transverse size of the fourth sub-fin to be equal to that of the second sub-fin.
Specifically, as shown in fig. 7, in this step, when the second fins are trimmed, a protective layer is formed on the first fins to cover the first fins, as shown in fig. 8, and the protective layer is removed after trimming, as shown in fig. 9.
Wherein, the protective layer can be one or more of an Organic Distribution Layer (ODL), a silicon-containing bottom anti-reflection coating (Si-BARC) and a photoresist layer.
And seventhly, etching back the first fin and the second fin to a target size.
Specifically, as shown in fig. 10, the first fin and the second fin are etched back to further reduce the size of the first fin and the second fin, so that the size of the first fin and the second fin reaches a target size.
Thus, the description of the steps related to the fabrication of the semiconductor device of the embodiment of the present invention is completed. After the above steps, other related steps may also be included, which are not described herein again. Besides the above steps, the preparation method of this embodiment may further include other steps among the above steps or between different steps, and these steps may be implemented by various processes in the prior art, and are not described herein again.
In order to solve the above problems in the prior art, the present invention provides a method for manufacturing a semiconductor device, in which fins with different heights are formed in order to match the performance of the device, grooves with different opening sizes are formed in the sacrificial layer during the formation of the fins, and then a semiconductor material layer is epitaxially grown in the grooves, and fins with different heights are formed in the grooves with different opening sizes due to different epitaxial speeds of the semiconductor material layer due to different opening sizes, so that the heights of the fins can be better controlled by the method, and simultaneously the profiles of the first groove and the second groove can be better controlled by the method, so as to form a fan-Shaped Fin (S-Shaped Fin) device and a fan-Shaped FinFET (S-Shaped FinFET), causing off-state current (I) of the S-FinFET deviceoff) The absolute value is greatly improved, so that the performance and the yield of the semiconductor device are improved.
The semiconductor device of the present invention has the same advantages as described above because of the above manufacturing method. The electronic device of the present invention also has the above advantages because of the use of the above semiconductor device.
Example two
The present invention also provides a semiconductor device including:
a semiconductor substrate;
the first fin is positioned on the semiconductor substrate;
the second fin is positioned on the semiconductor substrate;
wherein the height of the first fin is greater than the height of the second fin.
The first fin and the second fin respectively comprise a first sub-fin and a second sub-fin which are alternately arranged from top to bottom, wherein the transverse size of the second sub-fin is larger than that of the first sub-fin.
In a cross-sectional view along the first fin and the second fin perpendicular to the surface of the semiconductor substrate, the first sub-fin has a square shape, and the second sub-fin has an oval shape or a fan shape.
Wherein the semiconductor substrate includes an NMOS region and a PMOS region to form different devices in a subsequent step.
Forming the first fin in the PMOS region and the second fin in the NMOS region.
Wherein, in a cross-sectional view of the first and second grooves, the first and third sub-grooves are square, and the second and fourth sub-grooves are oval or fan-shaped.
Specifically, the first sub-groove and the third sub-groove may have a square and cylindrical structure, that is, they are uniformly maintained by the upper and lower sizes, and the opening size of the first sub-groove is smaller than that of the third sub-groove, and the opening size of the second sub-groove is smaller than that of the fourth sub-groove.
Optionally, the second and fourth sub-grooves are of elliptical pyramidal or fan-Shaped (pyramidal) pyramidal configuration, but the examples are exemplary only, as long as the basic repeating units in the first and second grooves are substantially in the shape of a volumetric flask or similar in a chemical container.
Wherein the Fin-Shaped Fin (S-FinFET) and Fin-Shaped FinFET (S-FinFET) devices cause an off-state current (I) of the S-FinFET devicesoff) The absolute value is greatly improved, so that the performance and the yield of the semiconductor device are improved.
In order to solve the above problems in the prior art, the present invention provides a semiconductor device, in a method for manufacturing the semiconductor device, in order to match the performance of the device, fins with different heights are formed, grooves with different opening sizes are formed in the sacrificial layer in the Fin forming process, then a semiconductor material layer is epitaxially grown in the grooves, fins with different heights are formed in the grooves with different opening sizes due to different epitaxial speeds of the semiconductor material layer, the heights of the fins can be better controlled by the method, and simultaneously the profiles in the first groove and the second groove op can be better controlled by the method, so as to form a fan-Shaped Fin (scanll-Shaped Fin) device and a fan-Shaped FinFET (S-FinFET) device, causing off-state current (I) of the S-FinFET deviceoff) The absolute value is greatly improved, so that the performance and the yield of the semiconductor device are improved.
The semiconductor device of the present invention has the same advantages as described above because of the above manufacturing method. The electronic device of the present invention also has the above advantages because of the use of the above semiconductor device.
EXAMPLE III
Another embodiment of the present invention provides an electronic device, which includes a semiconductor device, wherein the semiconductor device is the semiconductor device in the second embodiment or the semiconductor device manufactured by the method of manufacturing the semiconductor device in the first embodiment.
The electronic device may be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game machine, a television, a VCD, a DVD, a navigator, a camera, a video camera, a recording pen, an MP3, an MP4, and a PSP, or may be an intermediate product having the semiconductor device, for example: a mobile phone mainboard with the integrated circuit, and the like.
The electronic device also has the above-described advantages because the semiconductor device included has higher performance.
Fig. 11 shows an example of a mobile phone handset. The mobile phone handset 300 is provided with a display portion 302, operation buttons 303, an external connection port 304, a speaker 305, a microphone 306, and the like, which are included in a housing 301.
Wherein the mobile phone handset comprises the semiconductor device described above, or the semiconductor device manufactured according to the manufacturing method of the semiconductor device described in the first embodiment, in the manufacturing method of the semiconductor device, in order to match the performance of the device, fins with different heights are formed, grooves with different opening sizes are formed in the sacrificial layer in the Fin forming process, then the semiconductor material layer is epitaxially grown in the grooves, because the opening sizes are different, the epitaxial speeds of the semiconductor material layer are different, so that fins with different heights are formed in the grooves with different opening sizes, by which the heights of the fins can be better controlled, and by which the profiles in the first groove and the second groove can be better controlled, so as to form the fan-Shaped Fin (scanlop-Shaped Fin) and the fan-Shaped FinFET (scanlop-Shaped FinFET, S-FinFET) device, off-state current (I) of said S-FinFET deviceoff) The absolute value is greatly improved, so that the performance and the yield of the semiconductor device are improved.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (11)
1. A method of fabricating a semiconductor device, the method comprising:
providing a semiconductor substrate, and forming a sacrificial layer and a mask layer on the semiconductor substrate;
patterning the mask layer and the sacrificial layer to form a first groove and a second groove which are spaced from each other in the mask layer and the sacrificial layer, wherein the transverse size of the first groove is smaller than that of the second groove;
epitaxially growing a semiconductor material layer in the first groove to form a first fin, and epitaxially growing the semiconductor material layer in the second groove to form a second fin, wherein the height of the second fin is less than that of the first fin;
removing the mask layer and the sacrificial layer to expose the first fin and the second fin;
trimming the second fin such that a lateral dimension of the second fin is equal to a lateral dimension of the first fin.
2. The method of claim 1, wherein the first grooves comprise a first sub-groove and a second sub-groove which are alternately arranged from top to bottom, and the transverse opening size of the second sub-groove is larger than that of the first sub-groove;
the second groove comprises a third sub-groove and a fourth sub-groove which are alternately arranged from top to bottom, and the transverse opening size of the fourth sub-groove is larger than that of the third sub-groove;
and the transverse opening size of the third sub-groove is larger than that of the first sub-groove, and the transverse opening size of the fourth sub-groove is larger than that of the second sub-groove.
3. The method of claim 2, wherein the layer of semiconductor material is epitaxially grown to form a first sub-fin in the first sub-recess and a second sub-fin in the second sub-recess to form the first fin; simultaneously forming a third sub-fin in the third sub-groove and a fourth sub-fin in the fourth sub-groove to form the second fin;
trimming the second fin such that the lateral dimension of the third sub-fin is equal to the lateral dimension of the first sub-fin and the lateral dimension of the fourth sub-fin is equal to the lateral dimension of the second sub-fin.
4. The method of claim 2, wherein in a cross-sectional view of the first and second grooves in a direction perpendicular to the surface of the semiconductor substrate, the first sub-groove is square, the third sub-groove is square, the second sub-groove is oval or fan-shaped, and the fourth sub-groove is oval or fan-shaped.
5. The method of claim 2, wherein the step of forming the first and second grooves comprises:
anisotropically etching the mask layer and the sacrificial layer to form the first sub-groove and the second sub-groove in the mask layer and on the top of the sacrificial layer, and simultaneously form the third sub-groove and the fourth sub-groove, continuing to perform the anisotropic etching to form the first sub-groove and the second sub-groove which are alternately arranged, and to form the third sub-groove and the fourth sub-groove which are alternately arranged;
wherein, the first recess least significant end is first sub-recess, the least significant end of second recess is third sub-recess.
6. The method of claim 1 or 2, wherein the first recess and the second recess are etched using a hybrid pulse etching process.
7. The method of claim 1, wherein the epitaxial rate of the layer of semiconductor material decreases with increasing recess opening.
8. The method of claim 1 or 2, further comprising the step of passivating the sidewalls of the first and second recesses prior to epitaxially growing the layer of semiconductor material to form a passivation layer on the sidewalls of the first and second recesses.
9. The method of claim 1, wherein the semiconductor substrate comprises an NMOS region and a PMOS region, wherein the first fin is formed in the PMOS region and the second fin is formed in the NMOS region.
10. The method of claim 1, wherein a protective layer is formed over the first fins to cover the first fins while trimming the second fins, and wherein the protective layer is removed after the trimming.
11. The method of claim 1, further comprising the step of etching back the first fin and the second fin to a target size.
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