CN107689355B - 半导体器件和方法 - Google Patents

半导体器件和方法 Download PDF

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Publication number
CN107689355B
CN107689355B CN201710402652.1A CN201710402652A CN107689355B CN 107689355 B CN107689355 B CN 107689355B CN 201710402652 A CN201710402652 A CN 201710402652A CN 107689355 B CN107689355 B CN 107689355B
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conductive contact
semiconductor device
insulating material
disposed
contact
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CN107689355A (zh
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张哲诚
林志翰
曾鸿辉
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种用于制造半导体器件(例如，鳍式场效应晶体管)的代表性方法包括以下步骤：在衬底上方沉积第一绝缘材料，并且在第一绝缘材料中形成第一导电接触件。第一导电接触件具有突出的最上表面，具有沿着第一导电接触件的中心部分的第一高度和沿着第一导电接触件的侧壁的垂直矢量投影的第二高度。第一高度大于第二高度。在第一绝缘材料上方设置第二绝缘材料，并且在第二绝缘材料中形成第二导电接触件。在第一导电接触件上方设置第二导电接触件并且至少部分地位于第一导电接触件内。第二导电接触件的最下表面和第一导电接触件的突出的最上表面之间的距离小于约1.0nm。本发明实施例涉及半导体器件和方法。

Description

半导体器件和方法
技术领域
本发明实施例涉及半导体器件和方法。
背景技术
半导体器件用于例如，诸如个人计算机、手机、数码相机和其他电子设备的各种电子应用中。通常通过在半导体衬底上方依次沉积绝缘或介电层、导电层和半导体材料层以及使用光刻图案化各个材料层以在各个材料层上形成电路组件和元件来制造半导体器件。
半导体产业通过最小部件尺寸的不断减小来持续地改进各个电子组件 (例如，晶体管、二极管、电阻器、电容器等)的集成密度，这允许在给定的区域中集成更多的组件。然而，随着最小部件尺寸的减小，出现了应该解决的额外的问题。
发明内容
根据本发明的一些实施例，提供了一种半导体器件，包括：第一导电接触件，设置在衬底上方，所述第一导电接触件包括具有第一横向宽度的最上表面；以及第二导电接触件，位于所述第一导电接触件上方，所述第二导电接触件包括具有第二横向宽度的下部，其中，所述第一横向宽度大于所述第二横向宽度。
根据本发明的另一些实施例，还提供了一种半导体器件，包括：第一绝缘材料，设置在衬底上方；第一导电接触件，设置在所述第一绝缘材料中，所述第一导电接触件包括突出的最上表面，所述第一导电接触件具有沿着所述第一导电接触件的中心线的第一高度，所述第一导电接触件具有沿着所述第一导电接触件的侧壁的垂直矢量投影的第二高度，其中，所述第一高度大于所述第二高度；第二绝缘材料，设置在所述第一绝缘材料上方；以及第二导电接触件，位于所述第二绝缘材料中，所述第二导电接触件设置在所述第一导电接触上方并且至少部分地位于所述第一导电接触件内。
根据本发明的又一些实施例，还提供了一种形成半导体器件的方法，包括：在衬底上方沉积第一绝缘材料；在所述第一绝缘材料中形成第一导电接触件，所述第一导电接触件包括突出的最上表面，所述第一导电接触件具有沿着所述第一导电接触件的中心线的第一高度，所述第一导电接触件具有沿着所述第一导电接触件的侧壁的垂直矢量投影的第二高度，其中，所述第一高度大于所述第二高度；在所述第一绝缘材料上方沉积第二绝缘材料；以及在所述第二绝缘材料中形成第二导电接触件，所述第二导电接触件设置在所述第一导电接触件上方并且至少部分地位于所述第一导电接触件内，其中，所述第二导电接触件的最下表面和所述第一导电接触件的最上表面之间的距离小于1.0nm。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳地理解本发明的各个方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或减小。
图1示出了根据一些实施例形成finFET器件的工艺中的步骤。
图2A至图2B示出了根据一些实施例形成源极/漏极区。
图3示出了根据一些实施例形成第一开口。
图4示出了根据一些实施例形成介电层和第二开口。
图5示出了根据实施例形成第二接触件。
图6A至6C示出了根据实施例调整源极/漏极区。
图7A至图7C示出了根据实施例形成接缝。
图8A至图8B示出了根据实施例调整第一接触件。
图9A至图9C示出了根据实施例形成接缝。
图10A至10B示出了根据实施例位于第一接触件上的垂直侧壁。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为了便于描述，在此可以使用诸如“在…下方”、“在…下面”、“下部”、“在…之上”、“上部”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，并且在此使用的空间相对描述符可以同样地作出相应的解释。
现在参考图1，示出诸如finFET器件的半导体器件100的透视图。在实施例中，半导体器件100包括其中形成有第一沟槽103的衬底101。衬底101可以是硅衬底，但是可以使用诸如绝缘体上半导体(SOI)、应变 SOI和绝缘体上的硅锗的其他衬底。衬底101可以是p型半导体，但是在其他实施例中，它可以是n型半导体。
可以形成第一沟槽103作为最终形成第一隔离区105的初始步骤。可以使用掩蔽层(在图1中未单独示出)以及合适的蚀刻工艺来形成第一沟槽103。例如，掩蔽层可以是包括通过诸如化学汽相沉积(CVD)工艺形成的氮化硅的硬掩模，然而，可以利用诸如氧化物、氮氧化物、碳化硅、它们的组合等的其他材料以及诸如等离子体增强化学汽相沉积(PECVD)、低压化学汽相沉积(LPCVD)、或甚至形成氧化硅，接着氮化的其他工艺。一旦形成掩蔽层，可以通过合适的光刻工艺图案化掩蔽层以暴露衬底101 的将被去除以形成第一沟槽103的那些部分。
本领域技术人员将意识到，上述用于形成掩蔽层的工艺和材料并不是用于保护衬底101的部分同时暴露衬底101的其他部分以形成第一沟槽103 的唯一方法。诸如图案化和显影光刻胶的任何合适的工艺可以用于暴露衬底101的将要去除的部分从而形成第一沟槽103。所有此类方法都完全旨在包括在本实施例的范围内。
一旦已经形成和图案化掩蔽层，则在衬底101中形成第一沟槽103。可以通过诸如反应离子蚀刻(RIE)的合适的工艺去除暴露的衬底101以在衬底101中形成第一沟槽103，但是可以使用任何合适的工艺。在实施例中，第一沟槽103可以形成为具有从衬底101表面的小于约
Figure BDA0001310080000000041
的第一深度，诸如约
Figure BDA0001310080000000042
然而，如本领域普通技术人员将意识到，形成第一沟槽103的上述工艺仅仅是一个潜在的工艺，并且不意味着是唯一的实施例。相反，可以利用能够形成第一沟槽103的任何合适的工艺，该合适的工艺包括任何数量的掩蔽和去除步骤。
除了形成第一沟槽103之外，掩蔽和蚀刻工艺从衬底101的保持未被去除的那些部分额外地形成鳍107。为了简便起见，鳍107在图中示出为通过虚线与衬底101分离，但是分离的物理指示可以存在或可以不存在。如下所述，可以使用这些鳍107以形成多栅极FinFET晶体管的沟道区。尽管图1仅示出由衬底101形成的三个鳍107，但是可以使用任何数量的鳍107。
鳍107可以形成为使得它们在衬底101的表面处具有介于约5nm和约 80nm之间(诸如约30nm)的宽度。此外，鳍107可以彼此间隔开介于约 10nm和约100nm之间(诸如约50nm)的距离。通过以这种方式间隔开鳍 107，鳍107可以各自形成单独的沟道区，同时仍然足够接近以共享共同的栅极(下面进一步讨论)。
一旦已经形成第一沟槽103和鳍107，可以用介电材料填充第一沟槽 103，并且可以在第一沟槽103内凹进介电材料以形成第一隔离区105。介电材料可以是氧化物材料、高密度等离子体(HDP)氧化物等。在第一沟槽103的可选的清洁和加衬之后，可以使用化学汽相沉积(CVD)方法(例如，HARP工艺)、高密度等离子体CVD方法或本领域中已知的其他合适的形成方法来形成介电材料。
可以通过用介电材料过填充第一沟槽103和衬底101，并且然后通过诸如化学机械抛光(CMP)、蚀刻、它们的组合等的合适的工艺去除第一沟槽103和鳍107外部的多余材料来填充第一沟槽103。在实施例中，去除工艺还去除位于鳍107上方的任何介电材料，从而使得介电材料的去除将暴露鳍107的表面以用于进一步的处理步骤。
一旦已经用介电材料填充第一沟槽103，然后可以将介电材料凹进为远离鳍107的表面。可以实施凹进以暴露邻近鳍107顶面的鳍107的侧壁的至少部分。可以使用通过将鳍107的顶面浸入诸如HF的蚀刻剂的湿蚀刻来凹进介电材料，但是可以使用诸如H2的其他蚀刻剂，和诸如反应离子蚀刻、利用诸如NH3/NF3的蚀刻剂的干蚀刻、化学氧化去除或干化学清洁的其他方法。可以使介电材料从鳍107的表面凹进介于约
Figure BDA0001310080000000051
和约
Figure BDA0001310080000000052
之间(诸如约
Figure BDA0001310080000000053
)的距离。此外，凹进还可以去除位于鳍107上方的任何剩余的介电材料，以确保鳍107暴露从而用于进一步处理。
然而，本领域普通技术人员将意识到，上述步骤可以仅仅是用于填充和凹进介电材料的全部工艺的部分。例如，还可以利用加衬步骤、清洁步骤、退火步骤、间隙填充步骤、它们的组合等以形成沟槽103并且用介电材料填充沟槽103。所有潜在的工艺步骤完全旨在包括在本发明的范围内。
在已经形成第一隔离区105之后，可以在每个鳍107上方形成伪栅极电介质109、位于伪栅极电介质109上方的伪栅电极111和第一间隔件113。在实施例中，可以通过热氧化、化学汽相沉积、溅射或本领域已知和使用的用于形成栅极电介质的任何其他方法来形成伪栅极电介质109。根据栅极电介质的形成技术，鳍107的顶部上的伪栅极电介质109的厚度可以不同于鳍107的侧壁上的栅极电介质的厚度。
伪栅极电介质109可以包括诸如具有从约3埃至约100埃(诸如约10 埃)的范围内的厚度的二氧化硅或者氮氧化硅的材料。伪栅极介电质109 可由具有约0.5埃至约100埃(诸如10埃或更小)的等效氧化物厚度的诸如氧化镧(La2O3)、氧化铝(Al2O3)、氧化铪(HfO2)、氮氧化铪(HfON) 或氧化锆(ZrO2)或它们的组合的高介电常数(高k)材料(例如，其相对介电常数大于约5)形成。此外，还可以将二氧化硅、氮氧化硅和/或高 k材料的任何组合用于伪栅极介电质109。
伪栅电极111可以包括导电材料并且可以选自包括W、Al、Cu、AlCu、 W、Ti、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、Ta、TaN、Co、Ni、它们的组合等的组。伪栅电极111可以通过化学汽相沉积(CVD)、溅射沉积或者本领域已知和使用的用于沉积导电材料的其他技术来沉积。伪栅电极111的厚度可以在约
Figure BDA0001310080000000061
至约
Figure BDA0001310080000000062
的范围内。伪栅电极111的顶面可以具有非平坦的顶面，并且可以在伪栅电极111的图案化或栅极蚀刻之前被平坦化。在此点处，可以向伪栅电极111中引入或者不引入离子。例如，可以通过离子注入技术引入离子。
一旦形成，可以图案化伪栅极电介质109和伪栅电极111以在鳍107 上方形成一系列堆叠件115。堆叠件115限定位于伪栅极电介质109下方的鳍107的每侧上的多个沟道区。可以通过使用例如本领域中已知的沉积和光刻技术在伪栅电极111上沉积和图案化栅极掩模(在图1中未单独示出)来形成堆叠件115。栅极掩模可以结合通常使用的诸如(但不限于)氧化硅、氮氧化硅、SiCON、SiC、SiOC和/或氮化硅的掩模和牺牲材料，并且可以沉积至介于约
Figure BDA0001310080000000063
和约
Figure BDA0001310080000000064
之间的厚度。可以使用干蚀刻工艺蚀刻伪栅电极111和伪栅极电介质109以形成图案化的堆叠件115。
一旦已经图案化堆叠件115，就可以形成第一间隔件113。可以在堆叠件115的相对两侧上形成第一间隔件113。通常通过在先前形成的结构上毯式沉积间隔件层(在图1中未单独示出)来形成第一间隔件113。间隔件层可包括SiN、氮氧化物、SiC、SiON、SiOCN、SiOC、氧化物等，并且可以通过用于形成这种层的诸如化学汽相沉积(CVD)、等离子体增强 CVD、溅射和本领域已知的其他方法的方法来形成。间隔件层可以包括具有不同蚀刻特性的不同材料或与第一隔离区105内的介电材料相同的材料。然后，诸如通过一次或多次蚀刻以从该结构的层级去除间隔件层来图案化第一间隔件113以形成第一间隔件113。
在实施例中，第一间隔件113可以形成为具有介于约
Figure BDA0001310080000000065
和约
Figure BDA0001310080000000066
之间的第一厚度T1。此外，一旦已经形成第一间隔件113，邻近一个堆叠件 115的第一间隔件113可以与邻近另一堆叠件115的第一间隔件113分开介于约
Figure BDA0001310080000000071
和约
Figure BDA0001310080000000072
之间(诸如约
Figure BDA0001310080000000073
)的第一距离D1。然而，可以使用任何合适的厚度和距离。
图2A-图2B示出从未被堆叠件115和第一间隔件113保护的那些区域去除鳍107并且再生长源极/漏极区201(图2B示出沿着线B-B'的图2A的截面图)。可以使用堆叠件115和第一隔离件113作为硬掩模通过反应离子蚀刻(RIE)，或者通过任何其他合适的去除工艺来实施从未被堆叠件 115和第一隔离件113保护的那些区域去除鳍107。可以继续去除直到鳍107与第一隔离区105的表面齐平(如图所示)或低于第一隔离区105的表面。
一旦已经去除了鳍107的这些部分，就放置且图案化硬掩模(未单独示出)以覆盖伪栅极材料111，以防止生长，并且可以再生长源极/漏极区 201以与每个鳍107接触。在实施例中，可以再生长源极/漏极区201，并且在一些实施例中，可以再生长源极/漏极区201以形成应力源，该应力源将对位于堆叠件115下方的鳍107的沟道区施加应力。在鳍107包括硅并且FinFET是p型器件的实施例中，可以利用诸如硅或具有与沟道区不同的晶格常数的诸如硅锗的其他材料的材料通过选择性外延工艺再生长源极/ 漏极区201。外延生长工艺可以使用诸如硅烷、二氯硅烷、锗烷等的前体，并且可以持续介于约5分钟和约120分钟之间(诸如约30分钟)。在其他实施例中，源极/漏极区201可以包括诸如GaAs、GaP、GaN、InP、InAs、 InSb、GaAsP、AlGaN、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP 或它们的组合等的材料。
在实施例中，源极/漏极区201可以形成为具有介于约
Figure BDA0001310080000000074
和约
Figure BDA0001310080000000075
之间的厚度，和位于第一隔离区105上方的介于约1nm和约100nm之间(诸如约55nm)的第一高度H1。在本实施例中，源极/漏极区201可以形成为具有位于第一隔离区105的上表面之上的介于约5nm和约250nm之间(诸如约100nm)的高度。然而，可以利用任何合适的高度。
一旦形成源极/漏极区201，可以通过注入适当的掺杂剂来将掺杂剂注入到源极/漏极区201中以补充鳍107中的掺杂剂。例如，可以注入诸如硼、镓、铟等的p型掺杂剂以形成PMOS器件。或者，可以注入诸如磷、砷、锑等的n型掺杂剂以形成NMOS器件。可以使用堆叠件115和第一间隔件 113作为掩模来注入这些掺杂剂。应当注意，本领域的普通技术人员将意识到，可使用许多其他工艺、步骤等来注入掺杂剂。例如，本领域的普通技术人员将意识到，可以使用间隔件和衬垫的各个组合来实施多个注入，以形成具有适合于特定目的的特定形状或特性的源极/漏极区。这些工艺中的任何工艺都可以用于注入掺杂剂，并且以上描述并不意味着将本发明限制于上述步骤。
此外，在此点处，去除在形成源极/漏极区201期间覆盖伪栅极材料111 的硬掩模。在实施例中，例如，可以使用对硬掩模的材料具有选择性的湿蚀刻或干蚀刻工艺来去除硬掩模。然而，可以使用任何合适的去除工艺。
图2A还示出在堆叠件115和源极/漏极区201上方形成层间介电(ILD) 层203(在图2A中以虚线示出以便更清楚地示出下面的结构)。ILD层203 可包括诸如硼磷硅酸盐玻璃(BPSG)的材料，但是可以使用任何合适的电介质。可以使用诸如PECVD的工艺形成ILD层203，但是可以可选地使用诸如LPCVD的其他工艺。ILD层203可以形成为具有介于约
Figure BDA0001310080000000083
和约
Figure BDA0001310080000000084
之间的厚度。一旦形成，可使用例如平坦化工艺(诸如化学机械抛光工艺)使ILD层203与第一间隔件113齐平，但是可以使用任何合适的工艺。
在形成ILD层203之后，可以去除并替换伪栅电极111和伪栅极电介质109的材料以形成栅极堆叠件205。在实施例中，可以使用例如利用对伪栅电极111的材料具有选择性的蚀刻剂的湿蚀刻或干蚀刻工艺来去除伪栅电极111。然而，可以使用任何合适的去除工艺。
一旦已经去除伪栅电极111，可以重新填充留下的开口以形成栅极堆叠件205。在特定实施例中，栅极堆叠件205包括第一介电材料211、第一金属材料213、第二金属材料215和第三金属材料217。在实施例中，第一介电材料211是通过诸如原子层沉积、化学汽相沉积等的工艺沉积的诸如 HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、LaO、ZrO、Ta2O5、它们的组合等的高k材料。第一介电材料211可以沉积至介于约
Figure BDA0001310080000000081
和约
Figure BDA0001310080000000082
之间的厚度，但是可以使用任何合适的材料和厚度。
第一金属材料213可以形成为邻近第一介电材料211，并且可以由诸如Ti、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、TaN、Ru、Mo、WN、其他金属氧化物、金属氮化物、金属硅酸盐、过渡金属氧化物、过渡金属氮化物、过渡金属硅酸盐、金属的氮氧化物、金属铝酸盐、硅酸锆、铝酸锆、它们的组合等的金属材料形成。可以使用诸如原子层沉积、化学汽相沉积、溅射等的沉积工艺来将第一金属材料213沉积至介于约
Figure BDA0001310080000000091
和约
Figure BDA0001310080000000092
之间的厚度，但是可以使用任何合适的沉积工艺或厚度。
第二金属材料215可以形成为邻近第一金属材料213，并且在特定实施例中，第二金属材料215可以类似于第一金属材料213。例如，第二金属材料215可以由诸如Ti、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、 TaN、Ru、Mo、WN、其他金属氧化物、金属氮化物、金属硅酸盐、过渡金属氧化物、过渡金属氮化物、过渡金属硅酸盐、金属的氮氧化物、金属铝酸盐、硅酸锆、铝酸锆、它们的组合等的金属材料形成。此外，可以使用诸如原子层沉积、化学汽相沉积、溅射等的沉积工艺来将第二金属材料 215沉积至介于约
Figure BDA0001310080000000093
和约
Figure BDA0001310080000000094
之间的厚度，但是可以使用任何合适的沉积工艺或厚度。
第三金属材料217填充通过去除伪栅电极111而留下的开口的剩余部分。在实施例中，第三金属材料217是诸如W、Al、Cu、AlCu、W、Ti、 TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、Ta、TaN、Co、Ni、它们的组合等的金属材料，并且可以使用诸如原子层沉积、化学汽相沉积、溅射等的沉积工艺来沉积，以填充和/或过填充通过去除伪栅电极111留下的开口。在特定实施例中，第三金属材料217可沉积为具有介于约
Figure BDA0001310080000000095
和约
Figure BDA0001310080000000096
之间的厚度，但是可以使用任何合适的材料、沉积工艺和厚度。
一旦已经填充通过去除伪栅电极111留下的开口，则可以平坦化材料，以便去除通过去除伪栅电极111留下的开口外部的任何材料。在特定实施例中，可以使用诸如化学机械抛光的平坦化工艺来实施去除。然而，可以使用任何合适的平坦化和去除工艺。
在已经形成和平坦化栅极堆叠件205的材料之后，可以凹进栅极堆叠件205的材料并且用覆盖层221覆盖。在实施例中，可以使用例如利用对栅极堆叠件205的材料具有选择性的蚀刻剂的湿蚀刻或干蚀刻工艺来凹进栅极堆叠件205的材料。在实施例中，可以将栅极堆叠件205的材料凹进介于约5nm和约150nm之间(诸如约120nm)的距离。然而，可以使用任何合适的工艺和距离。
一旦已经凹进栅极堆叠件205的材料，则可以沉积覆盖层221并且将覆盖层221平坦化为与第一间隔件113共面。在实施例中，覆盖层221是使用诸如原子层沉积、化学汽相沉积、溅射等的沉积工艺沉积的诸如SiN、 SiON、SiCON、SiC、SiOC、它们的组合等的材料。覆盖层221可以沉积为介于约
Figure BDA0001310080000000101
和约
Figure BDA0001310080000000102
之间的厚度，并且然后使用诸如化学机械抛光的平坦化工艺平坦化，从而使得覆盖层221与第一间隔件113共面。
图3示出穿过ILD层203形成第一开口305，以便暴露源极/漏极区201，以准备形成第一接触件401(图3中未示出，但是下面相对于图4示出和描述)。另外，为了简便起见，以简化的形式示出栅极堆叠件205，而不示出额外层。在实施例中，可以通过首先在源极/漏极区201上方放置并图案化硬掩模301来形成第一开口305。在实施例中，硬掩模301可以是诸如氮化硅的介电材料，但是可以使用任何合适的掩蔽材料。
一旦已经放置硬掩模301，则图案化硬掩模301。在实施例中，可以通过沉积并且然后将光敏材料曝光到硬掩模301上来图案化硬掩模301。能量的撞击将在被图案化的能量源撞击的光敏材料的那些部分中引起化学反应，从而改变光刻胶的曝光部分的物理性质，从而使得光敏材料的曝光部分的物理性质不同于光敏材料的未曝光部分的物理性质。然后可以利用例如显影剂(未单独示出)显影光敏材料，以便将光敏材料的曝光部分与光敏材料的未曝光部分分离，以及然后可以使用各向异性蚀刻并且以光敏材料作为掩模来图案化硬掩模301。
一旦已经图案化硬掩模301，则可以使用硬掩模301作为掩模来形成第一开口305。在实施例中，可以使用第一蚀刻工艺(在图3中由标记为 303的波浪线表示)形成第一开口305，其可以是诸如反应离子蚀刻工艺的各向异性蚀刻工艺。然而，可以使用诸如湿蚀刻工艺的任何合适的工艺，以及任何合适的反应物。
第一蚀刻工艺303可以用于形成第一开口305，以准备形成第一接触件401。在特定实施例中，可利用第一蚀刻工艺303来将ILD层203的材料去除介于约10nm和约100nm之间(诸如约80nm)的第二距离D2。然而，可以利用任何合适的深度。此外，在邻近第一间隔件113的顶部的点处的第一开口305可以具有介于约10nm和约50nm之间的第一宽度W1(从硬掩模301起)，并且在第一开口305的底部处还可以具有介于约8nm和约40nm之间的第二宽度W2。然而，可以利用任何合适的尺寸。
一旦已经形成第一开口305，可以去除硬掩模301。在实施例中，可以使用例如使用对硬掩模301的材料具有选择性的蚀刻剂的湿蚀刻或干蚀刻工艺来去除硬掩模301。然而，还可以使用任何合适的去除工艺。
图4示出形成第一接触件401以及形成第一蚀刻停止层403和第一介电层405。可选地，在形成第一接触件401之前，可以形成硅化物接触件。硅化物接触件可以包括钛、镍、钴或铒、以便降低接触件的肖特基势垒高度。然而，还可以使用诸如铂、钯等的其他金属。可以通过毯式沉积适当的金属层，接着是退火步骤以使金属与下面暴露的硅反应来实施硅化。然后诸如利用选择性蚀刻工艺来去除未反应的金属。硅化物接触件的厚度可以介于约5nm和约50nm之间。
在实施例中，第一接触件401可以是诸如Al、Cu、W、Co、Ti、Ta、 Ru、TiN、TiAl、TiAlN、TaN、TaC、NiSi、CoSi、它们的组合等的导电材料，但是可以使用诸如溅射、化学汽相沉积、电镀、化学镀等沉积工艺将任何合适的材料沉积到第一开口305中以填充和/或过填充由第一蚀刻工艺 303形成的第一开口305。一旦填充或过填充，可以使用诸如化学机械抛光 (CMP)的平坦化工艺去除由第一蚀刻工艺303形成的第一开口305外部的任何沉积的材料。然而，可以利用任何合适的材料和形成工艺。此外，第一接触件401可以具有介于约
Figure BDA0001310080000000111
和约
Figure BDA0001310080000000112
之间的厚度，并且将具有第一宽度W1和第二宽度W2。
在一个实施例中，第一蚀刻停止层403可以使用等离子体增强化学汽相沉积(PECVD)由氮化硅形成，但是可以可选地使用诸如SiON、SiCON、 SiC、SiOC、SiCxNy、SiOx，其他电介质、它们的组合等的其他材料，并且可以可选地使用形成第一蚀刻停止层403的诸如低压CVD(LPCVD)、PVD 等的可选技术。第一蚀刻停止层403可以具有介于约
Figure BDA0001310080000000121
和约
Figure BDA0001310080000000122
之间的厚度。
一旦已经形成第一蚀刻停止层403，就形成第一介电层405。第一介电层405可以由诸如碳掺杂的氧化物的低k电介质、诸如多孔碳掺杂的二氧化硅、氧化硅、氮化硅的极低k电介质、诸如聚酰亚胺的聚合物，它们的组合等的一种或多种合适的介电材料制成。可以通过诸如旋涂工艺或化学汽相沉积(CVD)的工艺形成第一介电层405，但是可以使用任何合适的工艺，并且可以具有介于约
Figure BDA0001310080000000123
和约
Figure BDA0001310080000000124
之间(诸如约
Figure BDA0001310080000000125
)的厚度。
图4还示出图案化第一介电层405和第一蚀刻停止层403两者以形成暴露第一接触件401的第二开口407。在实施例中，可以通过首先在第一介电层405上方放置和图案化第二光刻胶409来图案化第一介电层405和第一蚀刻停止层403。在实施例中，第二光刻胶409可以是用图案化的能量曝光的三层光刻胶，以便图案化第二光刻胶409。然后可以显影并且蚀刻第二光刻胶409以图案化第二光刻胶409。
一旦已经图案化第二光刻胶409，则可以使用第二光刻胶409作为掩模将第二光刻胶409的图案转印至第一介电层405和第一蚀刻停止层403。在实施例中，可以使用第二蚀刻工艺(在图4中由标记为411的波浪线表示)来图案化第一介电层405，其可以是诸如反应离子蚀刻工艺的各向异性蚀刻工艺。然而，可以使用诸如湿蚀刻工艺的任何合适的工艺，以及任何合适的反应物。
可以使用第二蚀刻工艺411去除第一介电层405的材料以形成第二开口，以准备形成第二接触件501(图4中未示出，但是在下面相对于图5 示出和讨论)。在特定实施例中，可利用第二蚀刻工艺411来去除第一介电层405的材料，直到暴露第一蚀刻停止层403。然而，可以使用诸如湿蚀刻的任何合适的去除工艺。
一旦已经暴露第一蚀刻停止层403，则可以通过第一蚀刻停止层403 转印第一介电层405的图案，以暴露第一接触件401。在实施例中，可以使用例如各向异性蚀刻工艺(诸如反应离子蚀刻)来转印图案，该工艺使用对第一蚀刻停止层403的材料具有选择性的蚀刻剂。然而，还可以使用诸如湿蚀刻的任何合适的蚀刻剂或工艺。
此外，在已经在第一蚀刻停止层403形成开口以暴露下面的第一接触件401之后，蚀刻可以停止而不延伸到第一接触件401中，或者可以继续稍微过蚀刻并且形成第二开口407以部分地延伸到第一接触件401中。在特定实施例中，第二开口407可以延伸到第一接触件401中介于约2nm和约20nm之间(诸如小于约1.0nm)的第三距离D3。然而，可以利用任何合适的距离。
图5示出去除第二光刻胶409的以及形成第二接触件501。在实施例中，可以使用例如灰化工艺去除第二光刻胶409，从而增加第二光刻胶409 的温度，直到第二光刻胶409经历热分解，此时可以容易地去除第二光刻胶409。然而，还可以使用诸如湿蚀刻的任何合适的去除工艺。
一旦已经暴露第一接触件401，就可以沉积导电材料以填充和/或过填充第二开口407，以与第一接触件401电连接。在实施例中，第二接触件 501可以是诸如钨(W)的导电材料，但是可以使用诸如铝、铜、它们的合金、它们的组合等的任何合适的材料，并且可以使用诸如溅射、化学汽相沉积、电镀(利用晶种层)、化学镀等的沉积工艺来沉积，以填充和/或过填充第二开口407。
一旦填充或过填充，可以使用诸如化学机械抛光(CMP)的平坦化工艺去除第二开口407外部的任何沉积的材料。通过填充第二开口407，第二接触件501将呈现第二开口407的形状，并且随着第二接触件501远离第一接触件401延伸而具有一系列逐渐增加的宽度。在特定实施例中，第二接触件501可具有邻近第一接触件401的介于约3nm和约20nm之间的第三宽度W3，同时邻近第一蚀刻停止层403的顶面，第二接触件501可具有介于约3nm和约30nm的第四宽度W4。此外，在第二接触件501的顶部处，第二接触件501可以具有介于约5nm和约35nm之间的第五宽度W5。然而，可以利用任何合适的尺寸。
在特定实施例中，第一接触件401和第二接触件501的各个宽度彼此相关，以确保适当的接触。在一个实例中，第一宽度W1与第四宽度W4的比率大于1，而第五宽度W5与第三宽度W3的比率也大于1。在另一实施例中，第三宽度W3与第二宽度W2的比率小于1，并且第二宽度W2与第四宽度W4的比率大于1，使得第四宽度W4减去第二宽度W2小于零。在又一实施例中，第一宽度W1大于第二宽度W2，第二宽度W2大于第五宽度W5，第五宽度W5大于第四宽度W4，四宽度W4大于第三宽度W3。
图6A-图6C示出根据期望调整源极/漏极区201的形状的额外的实施例。在图6A所示的实施例中，将源极/漏极区201的顶面的形状调整为在结构内具有凹形，其中邻近的栅极堆叠件205之间的距离是小于约15nm 的第一间距P1。在特定实施例中，可以在蚀刻ILD层203期间获得凹形，以在已经暴露源极/漏极区201之后通过过蚀刻源极/漏极区201来暴露源极 /漏极区201。例如，在利用终点检测来确定何时源极/漏极区201已被暴露的实施例中，可以实施小于终点检测时间的约30％的额外过蚀刻。这种额外过蚀刻与间距的组合导致源极/漏极区201具有凹形顶面形状以及完全去除ILD层203。
接下来参见图6B，将源极/漏极区201的顶面的形状调整为当它在第一间隔件113之间延伸时具有平面形状。在图6B所示的实施例中，将源极/ 漏极区201的顶面的形状调整为在其中器件的沟道长度大于约50nm的结构内具有平面形状。在特定实施例中，通过在端点检测指示已经暴露源极/ 漏极区201时停止蚀刻的蚀刻ILD层203以暴露源极/漏极区201期间，获得该平面形状。该蚀刻与沟道长度结合使得源极/漏极区201具有平坦的顶面形状以及完全去除ILD层203。
接下来参见图6C，将源极/漏极区201的顶面的形状调整为当它在第一间隔件113之间延伸时具有凸形形状。在该实施例中，可以实施与上面相对于图6A所描述的类似的去除工艺(例如，用于暴露源极/漏极区201的蚀刻工艺)。然而，在该实施例中，栅极堆叠件205的第一间距P1可以介于约15nm和约20nm之间。因此，通过利用去除工艺以及过蚀刻，将源极/漏极区201的顶面形状调整为具有凸形形状。
图7A-7C示出分别类似于上面相对于图6A-6C描述的实施例的额外实施例。在这些实施例中，栅极堆叠件205包括位于栅极堆叠件205的材料内的接缝701或空隙，而不是具有无缝栅极堆叠件205。当用于短沟道器件的栅极宽度小并且利用非共形沉积工艺时，在栅极堆叠件205内沉积第三金属材料217的工艺期间形成接缝701。在获得形成接缝的特定实施例中，在其中栅极宽度W1等于或小于15nm的器件上利用诸如化学汽相沉积或物理汽相沉积的非共形沉积工艺。
图8A-图8B示出另一实施例，其中将第一接触件401的顶面形状调整为远离如上所述的平面形状。在图8A所示的实施例中，调整第一接触件 401的顶面，使得第一接触件401的顶面具有凹形形状。在实施例中，可以将第一接触件401的顶面向下下降介于约1nm和约10nm之间的第四距离D4。然而，可以利用任何合适的距离。
为了获得第一接触件401的凹形形状，可以修改以上相对于图4描述的平坦化工艺。特别地，在平坦化工艺是使用浆料的化学机械抛光的实施例中，可以选择对第一接触件401(例如钨)的材料具有优先的选择性的浆料，从而使得第一接触件401的材料具有高蚀刻速率。通过这种高蚀刻速率，第一接触件401的材料将成为碟状，从而使得第一接触件401的材料凹进成凹形形状。
图8B示出另一实施例，其中将第一接触件401的顶面调整为具有凸形形状，而不是调整为具有凹形形状。在该实施例中，第一接触件401的顶面可以向上延伸，从而使得第一接触件401的中心高度比第一接触件401 的边缘高度高出第五距离D5，第五距离D5大于约1nm。然而，可以利用任何合适的距离。
为了获得第一接触件401的凸形形状，可以修改以上相对于图4描述的平坦化工艺。特别地，在平坦化工艺是使用浆料的化学机械抛光的实施例中，可以选择浆料以缓慢地去除第一接触件401的材料。通过较慢地去除第一接触件401的材料，将以较慢的速率去除第一接触件401的材料，并且使得第一接触件401的材料形成凸形形状。
在另一实施例中，可以不通过修改浆料而是通过修改栅极堆叠件205 之间的第一间距P1来调整第一接触件401的顶面形状。在图8A是期望的凹形形状实施例中，第一间距P1可以形成为大于约80nm。在图8B是期望的凸形形状的实施例中，可以将第一间距P1修改为小于30nm。最后，如果期望第一接触件401的顶面是平面，则可以将第一间距P1调整为介于约 30nm和约80nm之间。
图9A-图9C还分别示出类似于图8A-8B 中描述的实施例的另一实施例。然而，在图9A-图9C所示的实施例中，栅极堆叠件205形成为包括相对于图7A-图7C所讨论的接缝701。
图10A-图10B示出第一接触件401形成有垂直或大致垂直的侧壁的实施例。在该实施例中，第一接触件401可以具有诸如介于约5nm和约40nm 之间(诸如约20nm)的第六宽度W6的恒定宽度。然而，可以利用任何合适的宽度。
为了将第一接触件401的侧壁形成为垂直或大致垂直，可以调整第一蚀刻工艺303(上文相对于图3所描述的)的工艺条件。在特定实施例中，可以将第一蚀刻工艺303的偏压和压力调整为高偏压和低压。这种高偏压和低压力用于将第一接触件401的侧壁形成为垂直或大致垂直。然而，可以使用用于将侧壁形成为垂直的任何合适的工艺。
图10B示出类似于上面相对于图10A描述的实施例的实施例。例如，图10B中所示的实施例可以包括具有垂直或大致垂直的侧壁的第一接触件 401。然而，在该实施例中，栅极堆叠件205额外地包括如上文相对于图 7A-图7C所讨论的接缝701。
通过利用本文所述的实施例来形成该结构，可在finFET工艺中实现更好的工艺窗口和在线控制。这允许更小的间隙和更高的产量增益。
在代表性实施例中，一种半导体器件(例如，FinFET)包括：设置在衬底上方的第一导电接触件，第一导电接触件包括具有第一横向宽度的最上表面；以及位于第一导电接触件上方的第二导电接触件，第二导电接触件包括具有第二横向宽度的下部，其中第一横向宽度大于第二横向宽度。第一导电接触件设置为横向邻近栅极结构，并且第二导电接触件设置在栅极结构之上的层级处。该半导体器件还可以包括：延伸至并接触栅极结构的顶面的至少部分的第一导电通孔；以及延伸至并接触第二导电接触件的顶面的至少部分的第二导电通孔。第二导电通孔的最底部可以设置在第一导电通孔的最底部之上的层级处。半导体器件还可以包括设置在栅极结构之上的层级处的蚀刻停止层(ESL)。第二导电接触件穿透ESL。第一导电接触件和第二导电接触件可以具有锥形侧壁轮廓。第二导电接触件可以具有设置为低于第一导电接触件的最上表面的最下表面。第一导电接触件的最上表面可以在远离衬底的方向上突出。第一导电接触件的最大垂直高度大于第一导电接触的侧壁的垂直距离的矢量投影。第二导电接触件的最下表面与第一导电接触的最上表面之间的距离可小于约1.0nm。半导体器件还可以包括插接在第一导电接触件的最下表面和源极/漏极(S/D)区之间的硅化物区。
在另一代表性实施例中，半导体器件包括设置在衬底上方的第一绝缘材料和设置在第一绝缘材料中的第一导电接触件。第一导电接触件具有突出的最上表面，沿着第一导电接触件的中心线的第一高度，以及沿着第一导电接触件的侧壁的垂直矢量投影的第二高度。第一高度大于第二高度。第二绝缘材料设置在第一绝缘材料上方，并且第二导电接触件位于第二绝缘材料中。第二导电接触件设置在第一导电接触件上方并且至少部分地位于第一导电接触件内。第一导电接触件可以横向设置为邻近鳍式场效应晶体管(FinFET)栅极结构，并且第二导电接触件可以设置在FinFET栅极结构之上的层级处。该半导体器件还可以包括：延伸至并接触FinFET栅极结构的顶面的至少部分的第一导电通孔；以及延伸至并接触第二导电接触件的顶面的至少部分的第二导电通孔。第二导电通孔的最下部可以设置第一导电通孔的突出的最上表面下面的层级处。半导体器件还可以包括设置在 FinFET栅极结构之上的层级处的蚀刻停止层(ESL)。第二导电接触件穿透ESL。第一导电接触件和第二导电接触件具有锥形侧壁轮廓。第二导电接触件的最下表面与第一导电接触件的突出的最上表面之间的距离可小于约1.0nm。
在又一代表性实施例中，一种用于制造半导体器件(例如，FinFET) 的方法开始于在衬底上方沉积第一绝缘材料的步骤。在第一绝缘材料中形成第一导电接触件。第一导电接触件具有突出的最上表面。沿着第一导电接触件的中心线的第一高度大于沿着第一导电接触件的侧壁的垂直矢量投影的第二高度。在第一绝缘材料上方设置第二绝缘材料。在第二绝缘材料中形成第二导电接触件。在第一导电接触件上方并且至少部分地在第一导电接触件内设置第二导电接触件，第二导电接触件的最下表面和第一导电接触的最上表面之间的距离小于约1.0nm。该方法还可以包括在沉积第一绝缘材料之前在衬底上方生长外延区的步骤。该方法还可以包括形成插接在第一导电接触件和外延区之间的硅化物区的步骤。该方法还可以包括形成设置在第一绝缘材料和第二绝缘材料之间的蚀刻停止层(ESL)的步骤，其中第二导电接触件穿透ESL的位于第一导电接触件上方的部分。
根据本发明的一些实施例，提供了一种半导体器件，包括：第一导电接触件，设置在衬底上方，所述第一导电接触件包括具有第一横向宽度的最上表面；以及第二导电接触件，位于所述第一导电接触件上方，所述第二导电接触件包括具有第二横向宽度的下部，其中，所述第一横向宽度大于所述第二横向宽度。
在上述半导体器件中，所述第一导电接触件横向设置为邻近栅极结构，并且所述第二导电接触件设置在所述栅极结构之上的层级处。
在上述半导体器件中，还包括位于所述栅极结构内的空隙。
在上述半导体器件中，还包括设置在所述栅极结构之上的层级处的蚀刻停止层(ESL)，其中，所述第二导电接触件穿透所述蚀刻停止层。
在上述半导体器件中，所述第一导电接触件和所述第二导电接触件具有锥形侧壁轮廓。
在上述半导体器件中，所述第二导电接触件具有设置为低于所述第一导电接触件的最上表面的最下表面。
在上述半导体器件中，所述第一导电接触件的最上表面在远离所述衬底的方向上突出。
在上述半导体器件中，所述第一导电接触件的最大垂直高度大于所述第一导电接触件的侧壁的垂直距离的矢量投影。
在上述半导体器件中，所述第二导电接触件的所述最下表面和所述第一导电接触件的所述最上表面之间的距离小于1.0nm。
在上述半导体器件中，还包括插接在所述第一导电接触件的最下表面和所述源极/漏极(S/D)区之间的硅化物区。
根据本发明的另一些实施例，还提供了一种半导体器件，包括：第一绝缘材料，设置在衬底上方；第一导电接触件，设置在所述第一绝缘材料中，所述第一导电接触件包括突出的最上表面，所述第一导电接触件具有沿着所述第一导电接触件的中心线的第一高度，所述第一导电接触件具有沿着所述第一导电接触件的侧壁的垂直矢量投影的第二高度，其中，所述第一高度大于所述第二高度；第二绝缘材料，设置在所述第一绝缘材料上方；以及第二导电接触件，位于所述第二绝缘材料中，所述第二导电接触件设置在所述第一导电接触上方并且至少部分地位于所述第一导电接触件内。
在上述半导体器件中，所述第一导电接触件横向设置为邻近鳍式场效应晶体管(FinFET)栅极结构，并且所述第二导电性接触件设置在所述鳍式场效应晶体管栅极结构之上的层级处。
在上述半导体器件中，还包括位于所述鳍式场效应晶体管栅极结构内的空隙。
在上述半导体器件中，还包括设置在所述鳍式场效应晶体管栅极结构之上的层级处的蚀刻停止层(ESL)，其中，所述第二导电接触件穿透所述蚀刻停止层。
在上述半导体器件中，所述第一导电接触件和所述第二导电接触件具有锥形侧壁轮廓。
在上述半导体器件中，所述第二导电接触件的最下表面和所述第一导电接触件的突出的最上表面之间的距离小于1.0nm。
根据本发明的又一些实施例，还提供了一种形成半导体器件的方法，包括：在衬底上方沉积第一绝缘材料；在所述第一绝缘材料中形成第一导电接触件，所述第一导电接触件包括突出的最上表面，所述第一导电接触件具有沿着所述第一导电接触件的中心线的第一高度，所述第一导电接触件具有沿着所述第一导电接触件的侧壁的垂直矢量投影的第二高度，其中，所述第一高度大于所述第二高度；在所述第一绝缘材料上方沉积第二绝缘材料；以及在所述第二绝缘材料中形成第二导电接触件，所述第二导电接触件设置在所述第一导电接触件上方并且至少部分地位于所述第一导电接触件内，其中，所述第二导电接触件的最下表面和所述第一导电接触件的最上表面之间的距离小于1.0nm。
在上述方法中，还包括在沉积所述第一绝缘材料之前，在所述衬底上方生长外延区。
在上述方法中，还包括形成插接在所述第一导电接触件和所述外延区之间的硅化物区。
在上述方法中，还包括形成设置在所述第一绝缘材料和所述第二绝缘材料之间的蚀刻停止层(ESL)，其中，所述第二导电接触件穿透所述蚀刻停止层的位于所述第一导电接触件上方的部分。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (20)

1.一种半导体器件，包括：
第一导电接触件，设置在衬底上方，所述第一导电接触件包括具有第一横向宽度的突出的最上表面，所述突出的最上表面为中心处沿垂直于所述横向的方向向外突出的曲面；以及
第二导电接触件，位于所述第一导电接触件上方并且至少部分地位于所述第一导电接触件内，所述第二导电接触件包括具有第二横向宽度的下部，其中，所述第一横向宽度大于所述第二横向宽度。
2.根据权利要求1所述的半导体器件，其中，所述第一导电接触件横向设置为邻近栅极结构，并且所述第二导电接触件设置在所述栅极结构之上的层级处。
3.根据权利要求2所述的半导体器件，还包括位于所述栅极结构内的空隙。
4.根据权利要求2所述的半导体器件，还包括设置在所述栅极结构之上的层级处的蚀刻停止层(ESL)，其中，所述第二导电接触件穿透所述蚀刻停止层。
5.根据权利要求1所述的半导体器件，其中，所述第一导电接触件和所述第二导电接触件具有锥形侧壁轮廓。
6.根据权利要求1所述的半导体器件，其中，所述第二导电接触件具有设置为低于所述第一导电接触件的最上表面的最下表面。
7.根据权利要求6所述的半导体器件，其中，所述第一导电接触件的最上表面在远离所述衬底的方向上突出。
8.根据权利要求7所述的半导体器件，其中，所述第一导电接触件的最大垂直高度大于所述第一导电接触件的侧壁的垂直距离的矢量投影。
9.根据权利要求8所述的半导体器件，其中，所述第二导电接触件的所述最下表面和所述第一导电接触件的所述最上表面之间的距离小于1.0nm。
10.根据权利要求9所述的半导体器件，还包括插接在所述第一导电接触件的最下表面和源极/漏极(S/D)区之间的硅化物区。
11.一种半导体器件，包括：
第一绝缘材料，设置在衬底上方；
第一导电接触件，设置在所述第一绝缘材料中，所述第一导电接触件包括突出的最上表面，所述第一导电接触件具有沿着所述第一导电接触件的中心线的第一高度，所述第一导电接触件具有沿着所述第一导电接触件的侧壁的垂直矢量投影的第二高度，其中，所述第一高度大于所述第二高度；
第二绝缘材料，设置在所述第一绝缘材料上方；以及
第二导电接触件，位于所述第二绝缘材料中，所述第二导电接触件设置在所述第一导电接触上方并且至少部分地位于所述第一导电接触件内。
12.根据权利要求11所述的半导体器件，其中，所述第一导电接触件横向设置为邻近鳍式场效应晶体管栅极结构，并且所述第二导电接触件设置在所述鳍式场效应晶体管栅极结构之上的层级处。
13.根据权利要求12所述的半导体器件，还包括位于所述鳍式场效应晶体管栅极结构内的空隙。
14.根据权利要求12所述的半导体器件，还包括设置在所述鳍式场效应晶体管栅极结构之上的层级处的蚀刻停止层(ESL)，其中，所述第二导电接触件穿透所述蚀刻停止层。
15.根据权利要求11所述的半导体器件，其中，所述第一导电接触件和所述第二导电接触件具有锥形侧壁轮廓。
16.根据权利要求11所述的半导体器件，其中，所述第二导电接触件的最下表面和所述第一导电接触件的突出的最上表面之间的距离小于1.0nm。
17.一种形成半导体器件的方法，包括：
在衬底上方沉积第一绝缘材料；
在所述第一绝缘材料中形成第一导电接触件，所述第一导电接触件包括突出的最上表面，所述第一导电接触件具有沿着所述第一导电接触件的中心线的第一高度，所述第一导电接触件具有沿着所述第一导电接触件的侧壁的垂直矢量投影的第二高度，其中，所述第一高度大于所述第二高度；
在所述第一绝缘材料上方沉积第二绝缘材料；以及
在所述第二绝缘材料中形成第二导电接触件，所述第二导电接触件设置在所述第一导电接触件上方并且至少部分地位于所述第一导电接触件内，其中，所述第二导电接触件的最下表面和所述第一导电接触件的最上表面之间的距离小于1.0nm。
18.根据权利要求17所述的形成半导体器件的方法，还包括在沉积所述第一绝缘材料之前，在所述衬底上方生长外延区。
19.根据权利要求18所述的形成半导体器件的方法，还包括形成插接在所述第一导电接触件和所述外延区之间的硅化物区。
20.根据权利要求17所述的形成半导体器件的方法，还包括形成设置在所述第一绝缘材料和所述第二绝缘材料之间的蚀刻停止层(ESL)，其中，所述第二导电接触件穿透所述蚀刻停止层的位于所述第一导电接触件上方的部分。
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