CN107579109A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN107579109A
CN107579109A CN201611031572.1A CN201611031572A CN107579109A CN 107579109 A CN107579109 A CN 107579109A CN 201611031572 A CN201611031572 A CN 201611031572A CN 107579109 A CN107579109 A CN 107579109A
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source electrode
semiconductor devices
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CN107579109B (zh
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周洛龙
郑永均
朴正熙
李钟锡
千大焕
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Hyundai Motor Co
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Hyundai Motor Co
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Abstract

本发明公开了半导体器件及其制造方法。一种半导体器件，包含：n‑型层，布置在n+型碳化硅衬底的第一表面上；第一沟槽和第二沟槽，形成在n‑型层中并且彼此分离；n+型区，布置在第一沟槽的侧面与第二沟槽的侧面之间并且布置在n‑型层上；栅极绝缘层，布置在第一沟槽内；源极绝缘层，布置在第二沟槽内；栅极，布置在栅极绝缘层上；氧化层，布置在栅极上；源极，布置在氧化层、n+型区、及源极绝缘层上；以及漏极，布置在n+型碳化硅衬底的第二表面上。

Description

半导体器件及其制造方法
相关申请的引证
本申请要求于2016年7月5日提交至韩国知识产权局的韩国专利申请第10-2016-0084838号的优先权权益，其全部内容通过引证方式结合于此。
技术领域
本公开内容涉及包含碳化硅(SiC)的半导体器件及其制造方法。
背景技术
为了减小在大电流量流动时的导电状态下的功率损耗，功率半导体器件应该具有低导通电阻或者低饱和电压。此外，功率半导体器件应该具有其PN结处经受反向高压的特性，反向高压在功率半导体器件关断或者当开关断开时可能施加至功率半导体器件的相对端，即，功率半导体器件应该具有高击穿电压的特性。
当满足电气条件和物理条件的各种功率半导体器件封装为一个模块时，封装模块中包含的半导体器件的数目及其电气规格可以根据系统要求的条件而改变。
通常，三相功率半导体模块用于生成驱动电动机的洛仑兹力。即，三相功率半导体模块控制施加至电动机的电流和功率，使得电动机的驱动状态得到确定。
虽然这种三相半导体模块中已包含并使用常规的硅绝缘栅双极晶体管(IGBT)和硅二极管，但是三相半导体模块近来趋向于包含碳化硅(SiC)金属氧化物半导体场效应晶体管(MOSFET)和碳化硅二极管以使其中的功率消耗最小化并且增加其开关速度。
当硅IGBT或者碳化硅MOSFET连接至单独的二极管时，需要多个配线来连接，并且因为由于多个配线导致寄生电容和电感出现，所以模块的开关速度可能降低。
本背景部分中公开的上述信息仅用于增强对本公开内容的背景技术的理解，并且因此本公开内容可能包含在该国家中未构成为本领域普通技术人员所知的现有技术的信息。
发明内容
本公开内容致力于提供包含MOSFET区和二极管区的碳化硅半导体器件。
根据本公开内容中的示例性实施方式，半导体器件包含：n-型层，布置在n+型碳化硅衬底的第一表面上；第一沟槽和第二沟槽，形成在n-型层中并且彼此分离；n+型区，布置在第一沟槽的侧面与第二沟槽的侧面之间并且布置在n-型层上；栅极绝缘层，布置在第一沟槽内部；源极绝缘层，布置在第二沟槽内部；栅极，布置在栅极绝缘层上；氧化层，布置在栅极上；源极，布置在氧化层、n+型区、及源极绝缘层上；以及漏极，布置在n+型碳化硅衬底的第二表面上。
可以进一步包含布置在第二沟槽的两个侧面上的p型区。
p型区可以布置在第二沟槽的侧面与n-型层之间。
p型区可以包围第二沟槽的拐角并且可以在第二沟槽的拐角下面延伸。
n+型区可以布置在p型区的一部分和n-型层上。
p型区的另一部分可以布置在n+型区与第二沟槽的侧面之间。
源极绝缘层和栅极绝缘层可包含相同的材料，并且源极绝缘层的厚度可以薄于栅极绝缘层的厚度。
源极可包含第一源极和第二源极，第一源极可以定位在源极绝缘层上，并且第二源极可以布置在n+型区、p型区的一部分、氧化层、及第一源极上。
第一源极和栅极可包含多晶硅，并且第二源极和漏极可包含欧姆金属。
栅极可包含多晶硅，并且第一源极、第二源极及漏极可包含欧姆金属。
栅极绝缘层和源极绝缘层可包含相同的材料，并且栅极绝缘层和源极绝缘层的厚度可以相同。
根据本公开内容中的另一示例性实施方式，半导体器件的制造方法包含以下步骤：在n+型碳化硅衬底的第一表面处形成n-型层；在n-型层上形成n+型区；蚀刻n+型区和n-型层以形成彼此分离的第一沟槽和第二沟槽；在第一沟槽内形成栅极绝缘层；在第二沟槽内形成源极绝缘层；在栅极绝缘层上形成栅极；在栅极上形成氧化层；在氧化层、n+型区、及源极绝缘层上形成源极；并且在n+型碳化硅衬底的第二表面处形成漏极。
半导体器件的制造方法可以进一步包括：在形成源极绝缘层的步骤之前将p型离子注入第二沟槽的侧面以在第二沟槽的侧面与n-型层之间形成p型区。
p型区的一部分可以形成在n+型区的下面，并且p型区的另一部分可以形成在n+型区与第二沟槽的侧面之间。
在形成p型区的步骤中，p型离子可以通过倾斜离子注入方法注入。
如上所述，根据本公开内容中的示例性实施方式，当根据本示例性实施方式的半导体器件执行MOSFET运行和二极管运行时，不需要连接常规的MOSFET元件和常规的二极管元件的配线。因此，元件的面积可以减小。
另外，当一个半导体器件在没有配线的情况下执行MOSFET运行和二极管运行时，半导体器件的开关速度可以提高并且功率损失可以减小。
附图说明
图1示出了根据本公开内容中的示例性实施方式的半导体器件的布局图。
图2示出了沿着图1的线II-II截取的截面图。
图3示出了沿着图1的线III-III截取的截面图。
图4是示出图1中示出的半导体器件的断开状态的视图。
图5是示出图1中示出的半导体器件的MOSFET的运行状态的视图。
图6是示出图1中示出的半导体器件的运行状态的视图。
图7至图11是示出图1的半导体器件的制造方法的一个实例的视图。
图12是根据本公开内容的另一示例性实施方式的半导体器件的一个实例的截面图。
具体实施方式
在下文中，将参照附图更全面地描述本公开内容，在附图中示出了本公开内容的示例性实施方式。然而，应当理解本公开内容不限于所公开的实施方式，而是相反旨在覆盖各种变型。如本领域技术人员应当认识到的，在所有修改都不偏离本公开内容的精神或范围的情况下，可以用各种不同的方式对所描述的实施方式进行修改。
在附图中，为了清楚起见，放大层、膜、面板、区等的厚度。将理解，当诸如层、膜、区或衬底的元件被称为“在”另一个元件“上”时，该元件可直接在另一个元件上或者也可存在中间元件。
图1示出了根据本公开内容中的示例性实施方式的半导体器件的布局图。图2示出了沿着图1的线II-II截取的截面图。图3示出了沿着图1的线III-III截取的截面图。
参考图1至图3，根据本示例性实施方式的半导体器件包含MOSFET(金属氧化物硅场效应晶体管)区A和二极管区B。
将对根据本示例性实施方式的半导体器件的详细结构进行描述。
根据本示例性实施方式的半导体器件包含n+型碳化硅衬底100、n-型层200、n+型区300、p型区400、栅极600、源极700、及漏极800。
n-型层200布置在n+型碳化硅衬底100的第一表面上，并且彼此分离的第一沟槽210和第二沟槽220定位在n-型层200中。
p型区400布置在第二沟槽220的两个侧面处。p型区400布置在第二沟槽220的侧面与n-型层200之间。p型区400包围第二沟槽220的拐角并且延伸至第二沟槽220的该拐角的底部。通过该结构，电场集中在p型区400的底部，因此防止电场集中在第二沟槽220的拐弯处。另一方面，p型区400未存在于第二沟槽220的下表面的下方。
n+型区300布置在第一沟槽210的侧面与第二沟槽220的侧面之间，并且布置在n-型层200上。另外，n+型区300布置在p型区400的一部分上(参考图2)。p型区400的另一部分布置在n+型区300与第二沟槽220的侧面之间。在该情况下，p型区400的另一部分的上表面的延伸线与n+型区300的上表面的延伸线相同(参考图3)。
栅极绝缘层510布置在第一沟槽210内，并且源极绝缘层520布置在第二沟槽220内。栅极绝缘层510和源极绝缘层520可包含相同的材料，并且源极绝缘层520的厚度可以薄于栅极绝缘层510的厚度。通过p型区400包围第二沟槽220的拐角使得源极绝缘层520的厚度可以形成为薄于栅极绝缘层510的厚度的结构，可以防止电场集中在第二沟槽220的拐弯处。然而，不限于此，源极绝缘层520的厚度可以与栅极绝缘层510的厚度相同。
栅极600布置在栅极绝缘层510上。栅极600填充第一沟槽210的内部并且可以突出至第一沟槽210的上侧。栅极600可包含多晶硅或者金属。
氧化层530布置在栅极600上。氧化层530覆盖栅极600的从第一沟槽210突出的侧面。
源极700布置在n+型区300、p型区400的部分、氧化层530、及源极绝缘层520上，并且包含第一源极710和第二源极720。第一源极710布置在源极绝缘层520上并且填充第二沟槽220内部。第二源极720布置在n+型区300、p型区400的部分、氧化层530、及第一源极710上。
本文中，第一源极710可包含多晶硅并且第二源极720可包含金属。在该情况下，金属可以是欧姆金属。此外，在本示例性实施方式中，描述了第一源极710和第二源极720包含不同的材料，然而不限于此，第一源极710和第二源极720可包含相同的金属。在该情况下，金属可以是欧姆金属。
漏极800布置在n+型碳化硅衬底100的第二表面上。本文中，n+型碳化硅衬底100的第二表面是指与n+型碳化硅衬底100的第一表面相对的表面。漏极800可包含金属。在该情况下金属可以是欧姆金属。
参考图2，源极700、栅极600、n+型区300、n-型层200、n+型碳化硅衬底100、及漏极800形成MOSFET区A，并且源极700、n+型区300、p型区400、n-型层200、n+型碳化硅衬底100、及漏极800形成二极管区B。
在根据本示例性实施方式的半导体器件中实现MOSFET的运行和二极管的运行。在该情况下，可以根据电压施加状态分开执行MOSFET的运行和二极管区的运行。
将参考图4至图6描述半导体器件的运行。
图4至图6是图1的半导体器件的运行的示意性视图。
图4是示出图1中示出的半导体器件的断开状态的视图。图5是示出图1中示出的半导体器件的MOSFET的运行状态的视图。图6是示出图1中示出的半导体器件的运行状态的视图。
半导体器件的断开状态通过以下条件执行。
VGS<VTH，VDS≥0V
半导体器件的MOSFET的运行通过以下条件执行。
VGS≥VTH，VDS>0V
半导体器件的运行状态通过以下条件执行。
VGS<VTH，VDS<0V
在此，VTH是MOSFET的阈值电压，VGS是VG-VS，并且VDS是VD-VS。VG是施加至栅极的电压，VD是施加至漏极的电压，以及VS是施加至源极的电压。
参考图4，耗尽层50形成在n-型层200处，使得在半导体器件的断开状态中没有产生电子电流的流动。在该情况下，耗尽层50形成在第一沟槽210与第二沟槽220之间，并且在第二沟槽220下方，并且布置为覆盖整个p型区400。
参考图5，在半导体器件的MOSFET的运行期间，电子(e-)从源极700迁移至漏极800。在此，从源极700发出的电子(e-)通过n-型层200迁移至漏极800。
在半导体器件的MOSFET的运行期间，耗尽层50由于施加至栅极600的电压而减小。即，耗尽层50形成在第二沟槽220下方，并且在第一沟槽210与第二沟槽220之间以覆盖整个p型区400，但是没有形成在第一沟槽210的侧面处。因此，电子(e-)迁移至第一沟槽210的侧面。
参考图6，在半导体器件的二极管的运行期间，电子(e-)从漏极800迁移至源极700。漏极800用作负极并且源极700用作正极。在此，从漏极800发出的电子(e-)通过n-型层200和p型区400迁移至源极700。
沟道形成在p型区400处，使得电子(e-)的移动路径在半导体器件的二极管的运行期间得到保证。在此，沟道是反型层沟道。耗尽层50形成在第一沟槽210与第二沟槽220之间、p型区400下方、及第一沟槽210下方，但是没有形成在第二沟槽220下方。即，电子(e-)迁移到n-型层200与p型区400在第二沟槽220下面的接合部分中。
如上所述，根据本示例性实施方式的半导体器件执行MOSFET的运行和二极管的运行使得不需要连接常规的MOSFET元件和常规的二极管元件的配线。因此，半导体器件的面积可以减小。
另外，因为半导体器件在没有配线的情况下执行MOSFET的运行和二极管的运行，所以半导体器件的开关速度可以提高并且功率损失可以减小。
接下来，将参考表1，通过比较普通的二极管元件与普通的MOSFET元件的特性描述根据本示例性实施方式的半导体器件。
表1表示根据本示例性实施方式的半导体器件、以及普通的二极管元件和普通的MOSFET元件的模拟结果。
比较例1是普通的结势垒肖特基(JBS)二极管元件，以及比较例2是普通的MOSFET元件。比较例3是普通的肖特基势垒二极管(SBD)元件。
在表1中，根据本示例性实施方式的半导体器件以及根据比较例1、比较例2、及比较例3的半导体器件的击穿电压被控制为几乎相等并且对电流密度进行比较。
[表1]
参考表1，针对100A电流量的载流面积在根据比较例1的JBS二极管元件中显示为0.579cm2，并且根据比较例2的MOSFET元件获取0.126cm2的载流面积。根据比较例1和比较例2的半导体器件的针对100A电流量的载流面积的总和是0.705cm2。
在根据比较例3的SBD元件中，针对100A电流量的载流面积在二极管运行期间显示为0.391cm2。根据比较例2和比较例3的半导体器件的针对100A电流量的载流面积的总和是0.517cm2。
在根据示例性实施方式的半导体器件的情况中，针对100A电流量的载流面积显示为0.385cm2。
即，作为针对100A的电流量的载流面积，可以确认根据示例性实施方式的半导体器件的面积相比于比较例1和2的总面积减小了45.4％。另外，可以确认根据示例性实施方式的半导体器件的面积相比于比较例2和3的总面积减小了25.5％。
接下来，将参考图7至11以及图2和图3描述根据图1的半导体器件的制造方法。
图7至图11是示出了制造根据图1的半导体器件的方法的一个实例的视图。
参考图7，在制备n+型碳化硅衬底100并且在n+型碳化硅衬底100的第一表面中形成n-型层200之后，在n-型层200上形成n+型区300。n-型层200可以通过外延生长或者n-离子注入形成。n+型区300也可以通过外延生长或者n-离子注入形成。
参考图8，蚀刻n+型区300和n-型层200以形成第一沟槽210和第二沟槽220。在该情况下，第一沟槽210和第二沟槽220同时形成。
参考图9，p型离子注入第二沟槽220的侧面以在第二沟槽220的侧面与n-型层200之间形成p型区400。因此，p型区400包围第二沟槽220的拐角并且延伸至第二沟槽220的拐角的底部。另一方面，p型区400没有形成在第二沟槽的下表面的下方。
在该情况下，p型区400的部分定位在n+型区300下方(参考图2)，并且p型区400的另一部分定位在n+型区300与第二沟槽220之间(参考图3)。在此，p型离子通过倾斜离子注入方法注入。倾斜离子注入方法是离子注入角度小于相对于水平面的直角的离子注入方法。
参考图10，在第一沟槽210内形成栅极绝缘层510，并且在第二沟槽220内形成源极绝缘层520。
栅极绝缘层510和源极绝缘层520的材料可以相同，并且源极绝缘层520的厚度可以薄于栅极绝缘层510的厚度。然而，不限于此，源极绝缘层520的厚度可以与栅极绝缘层510的厚度相同。
参考图11，在栅极绝缘层510上形成栅极600，并且在源极绝缘层520上形成第一源极710。
栅极600填充在第一沟槽210内并且可以突出至第一沟槽210的上侧。栅极600可以由多晶硅或者金属形成。
第一源极710填充在第二沟槽220内并且可以由多晶硅形成。
接下来，在栅极600上形成氧化层530。氧化层530形成为覆盖栅极600的从第一沟槽210突出的侧面。
参考图2和图3，在n+型区300、p型区400的部分、氧化层530、及第一源极710上形成第二源极720，并且在n+型碳化硅衬底100的第二表面处形成漏极800。在此，第二源极720和漏极800可以由金属形成。在该情况下，金属可以是欧姆金属。
在本示例性实施方式中，第一源极710和第二源极720在半导体器件的制造方法中由不同的材料形成，但是不限于此，并且第一源极710和第二源极720可以由相同的金属材料形成。在该情况下，金属可以是欧姆金属。在该情况下，在栅极绝缘层510上形成栅极600并且在栅极600上形成氧化层530之后，可以在n+型区300、p型区400的部分、氧化层530、及源极绝缘层520上形成源极700。
在根据本示例性实施方式的半导体器件的制造方法中，在同时形成第一沟槽210和第二沟槽220之后形成p型区400，但是本公开内容不限于此，并且可以形成p型区400然后可以在首先形成第二沟槽220之后形成第一沟槽210。
根据本示例性实施方式的半导体器件包含p型区400，但是本公开内容不限于此，并且p型区400可以省去。
接下来，将参考图12描述根据本公开内容的另一示例性实施方式的半导体器件。
图12是根据本公开内容的另一示例性实施方式的半导体器件的一个实例的截面图。
参考图12，根据本示例性实施方式的半导体器件除省去p型区之外具有与图1中示出的半导体器件相同的结构。因此，省去相同结构的描述。
根据本示例性实施方式的半导体器件包含彼此相邻的MOSFET区A和二极管区B。
源极700、栅极600、n+型区300、n-型层200、n+型碳化硅衬底100、及漏极800形成MOSFET区A，并且源极700、n+型区300、n-型层200、n+型碳化硅衬底100、及漏极800形成二极管区B。
在根据本示例性实施方式的半导体器件中，与根据图1的半导体器件相比较，省去p型区使得n-型层200布置在第二沟槽220的两个侧面上。n+型区300布置在第一沟槽210和第二沟槽220之间，并且布置在n-型层200上。源极700布置在n+型区300、氧化层530、及源极绝缘层520上。
布置在第一沟槽210内的栅极绝缘层510的厚度可以与布置在第二沟槽220内的源极绝缘层520的厚度相同。
根据本示例性实施方式的半导体器件执行类似图1的半导体器件的MOSFET(金属氧化物半导体场效应晶体管)运行和二极管运行。
根据本示例性实施方式的半导体器件的断开状态、MOSFET运行状态、及二极管运行状态的条件与根据图1的半导体器件的条件相同。
然而，与图1的半导体器件相比较，省去p型区，使得耗尽层50在半导体器件的断开状态期间形成在第一沟槽210与第二沟槽220之间并且在第二沟槽220下方。
在半导体器件的MOSFET的运行期间，耗尽层50形成在第一沟槽210与第二沟槽220之间并且在第二沟槽220下方，但是没有形成在侧面和第一沟槽210的下方。因此，电子(e-)通过第一沟槽210的侧面的n-型层200从源极700迁移到漏极800中。
在半导体器件的二极管运行期间，耗尽层50形成在第一沟槽210与第二沟槽220之间并且在第一沟槽210下方，但是没有形成在第二沟槽220的侧面和第二沟槽220的下方。因此，电子(e-)通过第二沟槽220的侧面的n-型层200从漏极800迁移到源极700中。即，与根据图1的半导体器件的二极管运行不同，电子(e-)通过没有耗尽层的n-型层200而不是形成在p型区400中的沟道迁移。
尽管已经结合目前被视为实际的示例性实施方式描述了本发明，然而，应当理解的是，本发明并不局限于所公开的实施方式，而是，相反，本发明旨在覆盖所附权利要求的精神和范围内包含的各种变形和等同布置。

Claims (20)

1.一种半导体器件，包括：
n-型层，布置在n+型碳化硅衬底的第一表面上；
第一沟槽和第二沟槽，形成在所述n-型层中并且所述第一沟槽和第二沟槽彼此分离；
n+型区，布置在所述第一沟槽的侧面与所述第二沟槽的侧面之间，并且所述n+型区布置在所述n-型层上；
栅极绝缘层，布置在所述第一沟槽内；
源极绝缘层，布置在所述第二沟槽内；
栅极，布置在所述栅极绝缘层上；
氧化层，布置在所述栅极上；
源极，布置在所述氧化层、所述n+型区及所述源极绝缘层上；以及
漏极，布置在所述n+型碳化硅衬底的第二表面上。
2.根据权利要求1所述的半导体器件，进一步包括：
p型区，布置在所述第二沟槽的两个侧面上。
3.根据权利要求2所述的半导体器件，其中，
所述p型区布置在所述第二沟槽的侧面与所述n-型层之间。
4.根据权利要求3所述的半导体器件，其中，
所述p型区包围所述第二沟槽的拐角并且在所述第二沟槽的所述拐角下方延伸。
5.根据权利要求4所述的半导体器件，其中，
所述n+型区布置在所述p型区的第一部分和所述n-型层上。
6.根据权利要求5所述的半导体器件，其中，
所述p型区的第二部分布置在所述第二沟槽的侧面与所述n+型区之间。
7.根据权利要求6所述的半导体器件，其中，
所述源极绝缘层和所述栅极绝缘层包含相同的材料，并且
所述源极绝缘层的厚度薄于所述栅极绝缘层的厚度。
8.根据权利要求7所述的半导体器件，其中，
所述源极包括第一源极和第二源极，
所述第一源极布置在所述源极绝缘层上，并且
所述第二源极布置在所述n+型区、所述p型区的一部分、所述氧化层及所述第一源极上。
9.根据权利要求8所述的半导体器件，其中，
所述第一源极和所述栅极包含多晶硅，并且
所述第二源极和所述漏极包含欧姆金属。
10.根据权利要求8所述的半导体器件，其中，
所述栅极包含多晶硅，并且
所述第一源极、所述第二源极及所述漏极包含欧姆金属。
11.根据权利要求1所述的半导体器件，其中，
所述栅极绝缘层和所述源极绝缘层包含相同的材料，并且
所述栅极绝缘层和所述源极绝缘层的厚度相同。
12.一种用于制造半导体器件的方法，包含以下步骤：
在n+型碳化硅衬底的第一表面上形成n-型层；
在所述n-型层上形成n+型区；
蚀刻所述n+型区和所述n-型层以形成彼此分离的第一沟槽和第二沟槽；
在所述第一沟槽内形成栅极绝缘层；
在所述第二沟槽内形成源极绝缘层；
在所述栅极绝缘层上形成栅极；
在所述栅极上形成氧化层；
在所述氧化层、所述n+型区及所述源极绝缘层上形成源极；并且
在所述n+型碳化硅衬底的第二表面上形成漏极。
13.根据权利要求12所述的方法，在形成所述源极绝缘层的步骤之前，进一步包括以下步骤：
注入p型离子至所述第二沟槽的侧面以在所述第二沟槽的所述侧面与所述n-型层之间形成p型区。
14.根据权利要求13所述的方法，其中，
所述p型区包围所述第二沟槽的拐角并且在所述第二沟槽的所述拐角下方延伸。
15.根据权利要求14所述的方法，其中，
在所述n+型区下方形成所述p型区的第一部分，并且
在所述n+型区与所述第二沟槽的所述侧面之间形成所述p型区的第二部分。
16.根据权利要求15所述的方法，其中，
在形成所述p型区的步骤中，
通过倾斜离子注入方法注入所述p型离子。
17.根据权利要求16所述的方法，其中，
所述源极绝缘层和所述栅极绝缘层包含相同的材料，并且
所述源极绝缘层的厚度薄于所述栅极绝缘层的厚度。
18.根据权利要求17所述的方法，其中，
所述源极包括第一源极和第二源极，
所述第一源极布置在所述源极绝缘层上，并且
所述第二源极布置在所述n+型区、所述p型区的一部分、所述氧化层及所述第一源极上。
19.根据权利要求18所述的方法，其中，
所述第一源极和所述栅极包含多晶硅，并且
所述第二源极和所述漏极包含欧姆金属。
20.根据权利要求18所述的方法，其中，
所述栅极包含多晶硅，并且
所述第一源极、所述第二源极及所述漏极包含欧姆金属。
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