CN107452636A - The encapsulating structure and method for packing of face recognition chip - Google Patents
The encapsulating structure and method for packing of face recognition chip Download PDFInfo
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- CN107452636A CN107452636A CN201710631902.9A CN201710631902A CN107452636A CN 107452636 A CN107452636 A CN 107452636A CN 201710631902 A CN201710631902 A CN 201710631902A CN 107452636 A CN107452636 A CN 107452636A
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- face recognition
- recognition chip
- face
- wiring layer
- metal
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- 238000000034 method Methods 0.000 title claims abstract description 57
- 238000012856 packing Methods 0.000 title claims abstract description 25
- 229910052751 metal Inorganic materials 0.000 claims abstract description 85
- 239000002184 metal Substances 0.000 claims abstract description 85
- 239000011521 glass Substances 0.000 claims abstract description 71
- 239000000463 material Substances 0.000 claims abstract description 59
- 230000008878 coupling Effects 0.000 claims abstract description 16
- 238000010168 coupling process Methods 0.000 claims abstract description 16
- 238000005859 coupling reaction Methods 0.000 claims abstract description 16
- 239000010410 layer Substances 0.000 claims description 134
- 239000000758 substrate Substances 0.000 claims description 46
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 40
- 229910000679 solder Inorganic materials 0.000 claims description 27
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 26
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 24
- 229910052802 copper Inorganic materials 0.000 claims description 24
- 239000010949 copper Substances 0.000 claims description 24
- 229910052759 nickel Inorganic materials 0.000 claims description 20
- 230000004888 barrier function Effects 0.000 claims description 18
- 238000005516 engineering process Methods 0.000 claims description 17
- 230000008569 process Effects 0.000 claims description 14
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 12
- 239000003822 epoxy resin Substances 0.000 claims description 12
- 229920000647 polyepoxide Polymers 0.000 claims description 12
- 239000000741 silica gel Substances 0.000 claims description 12
- 229910002027 silica gel Inorganic materials 0.000 claims description 12
- 229910052709 silver Inorganic materials 0.000 claims description 12
- 239000004332 silver Substances 0.000 claims description 12
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 10
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 10
- 229910052737 gold Inorganic materials 0.000 claims description 10
- 239000010931 gold Substances 0.000 claims description 10
- 238000001723 curing Methods 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 238000004528 spin coating Methods 0.000 claims description 7
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 6
- 239000004642 Polyimide Substances 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 6
- 229910045601 alloy Inorganic materials 0.000 claims description 6
- 239000000956 alloy Substances 0.000 claims description 6
- 239000004411 aluminium Substances 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 229910052731 fluorine Inorganic materials 0.000 claims description 6
- 239000011737 fluorine Substances 0.000 claims description 6
- 229920001721 polyimide Polymers 0.000 claims description 6
- 239000013047 polymeric layer Substances 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- 238000013007 heat curing Methods 0.000 claims description 4
- 238000000465 moulding Methods 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 239000002390 adhesive tape Substances 0.000 claims description 3
- 239000000919 ceramic Substances 0.000 claims description 3
- 230000008859 change Effects 0.000 claims description 3
- 230000006835 compression Effects 0.000 claims description 3
- 238000007906 compression Methods 0.000 claims description 3
- 238000009713 electroplating Methods 0.000 claims description 3
- 238000001704 evaporation Methods 0.000 claims description 3
- 230000008020 evaporation Effects 0.000 claims description 3
- 238000003475 lamination Methods 0.000 claims description 3
- 238000007747 plating Methods 0.000 claims description 3
- 229920000307 polymer substrate Polymers 0.000 claims description 3
- 238000007493 shaping process Methods 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims description 2
- 238000000926 separation method Methods 0.000 claims description 2
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical group [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 claims 2
- 238000001721 transfer moulding Methods 0.000 claims 1
- 238000005538 encapsulation Methods 0.000 abstract description 15
- 230000008901 benefit Effects 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- OINMNSFDYTYXEQ-UHFFFAOYSA-M 2-bromoethyl(trimethyl)azanium;bromide Chemical compound [Br-].C[N+](C)(C)CCBr OINMNSFDYTYXEQ-UHFFFAOYSA-M 0.000 description 2
- HIVGXUNKSAJJDN-UHFFFAOYSA-N [Si].[P] Chemical compound [Si].[P] HIVGXUNKSAJJDN-UHFFFAOYSA-N 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000012790 confirmation Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
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- 238000009792 diffusion process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
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- 238000012536 packaging technology Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
- G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
- G06V40/16—Human faces, e.g. facial parts, sketches or expressions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02379—Fan-out arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Human Computer Interaction (AREA)
- Oral & Maxillofacial Surgery (AREA)
- General Health & Medical Sciences (AREA)
- Multimedia (AREA)
- Theoretical Computer Science (AREA)
- Health & Medical Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The present invention provides a kind of encapsulating structure and method for packing of face recognition chip, including：Re-wiring layer, its first face have metal and metal coupling under salient point；Face recognition chip, its side wall, which makes, has wire so that front-side circuit is led into side wall；It is installed on the second face of the re-wiring layer by ACF out-phase conducting resinls, realizes the electric connection of wire and re-wiring layer；Glass cover-plate, it is packaged in the face recognition chip；Encapsulating material, the face recognition chip and the glass cover-plate surrounding are surrounded on, and expose the glass cover-plate.The present invention uses the encapsulation face recognition chip of encapsulating material enclosed, has stronger mechanical performance；Structure is simpler, can effectively reduce the cost of encapsulation；The face recognition chip uses lateral conduction, and pin configuration is simple, and wire is protected using encapsulating material, improves the stability of wire.
Description
Technical field
The present invention relates to a kind of semiconductor package and method for packing, more particularly to a kind of envelope of face recognition chip
Assembling structure and method for packing.
Background technology
As the function of integrated circuit is increasingly stronger, performance and integrated level more and more higher, and new integrated circuit goes out
Existing, encapsulation technology plays more and more important role in IC products, shared in the value of whole electronic system
Ratio it is increasing.Meanwhile as integrated circuit feature size reaches nanoscale, transistor to more high density, it is higher when
Clock frequency develops, and encapsulation also develops to more highdensity direction.
Because fan-out wafer level encapsulates (fowlp) technology due to having the advantages that miniaturization, low cost and high integration, with
And the energy efficiency with better performance and Geng Gao, fan-out wafer level encapsulation (fowlp) technology as high request movement/
The important method for packing of the electronic equipments such as wireless network, it is one of encapsulation technology most with prospects at present.
Recognition of face, refer in particular to carry out the computer technology of identity discriminating using com-parison and analysis face visual signature information.People
Face identification is to gather image or video flowing containing face, and automatic detect and track people in the picture with video camera or camera
Face, and then the face to detecting carries out a series of correlation techniques of face.The advantage of recognition of face is its naturality and not
The characteristics of being discovered by tested individual.So-called naturality, refer to that the same mankind of the identification method (or even other biological) carry out individual knowledge
The biological characteristic utilized when other is identical.Such as recognition of face, the mankind are also to compare face by observation to distinguish and confirm identity
, the identification with naturality also has speech recognition, bodily form identification etc. in addition, and fingerprint recognition, iris recognition etc. all do not have
Naturality, because the mankind or other biological distinguish individual not by such biological characteristic.The characteristics of not detectable, is for one
Kind of recognition methods is also critically important, and this can make the recognition methods not offensive, and because be not easy to arouse people's attention without
Easily it is spoofed.Recognition of face has the characteristics of this respect, and it is fully utilized visible ray and obtains human face image information, and is different from
Fingerprint recognition either iris recognition, it is necessary to utilize electronic pressure transmitter collection fingerprint or utilize infrared collection iris figure
Picture, these special acquisition modes are easy to be therefore easily perceived by humans, so as to more likely by impersonation.
Recognition of face is mainly used in identification.Because video monitoring is quickly being popularized, numerous video surveillance applications
There is an urgent need to the quick identity recognizing technology under a kind of remote, non-mated condition of user, in the hope of remote quick confirmation personnel
Identity, realize intelligent early-warning.Face recognition technology is undoubtedly optimal selection, can be from monitoring using fast face detection technique
Real-time searching face in video image, and compared in real time with face database, so as to realize quick identification.
A kind of encapsulating structure of existing face recognition chip is as shown in figure 1, it mainly includes the first glass plate 101, tool
There is the face recognition chip 104 of identification region 110, the face recognition chip 104 forms package cavity by the encapsulation of bonded layer 102
103, the second glass plate 109 is packaged with the face recognition chip 104, and the recognition of face side wall is sequentially formed with polymer
105th, conductive structure 106 and insulation system 107, the conductive structure are electrically drawn the face recognition chip 104
To the surface of the second glass plate 109, formed with the ball structure being electrically connected with the conductive structure on second glass plate,
To realize the extraction of the face recognition chip 104.
Above-mentioned face recognition chip encapsulating structure has the disadvantages that：
First, it is packaged using upper and lower layer glass cover plate, the mechanical performance of encapsulating structure is poor, the durability of chip
Can be bad；
Second, encapsulating structure is complex, and the cost of encapsulation is higher；
3rd, it is necessary to be repeatedly processed to glass during processing procedure, such as corrosion of the second glass cover-plate 109, and
, it is necessary to be cut to the glass cover-plate of the first glass cover-plate 101 and second, glass processing simultaneously in follow-up cutting technique
Difficulty is high, causes process costs very high.
4th, the protection to the conductive structure of face recognition chip side is more weak, easily causes chip failure.
Based on described above, there is provided a kind of technique is simple, the envelope of the face recognition chip of low cost and high mechanical properties
Assembling structure and method for packing are necessary.
The content of the invention
In view of the above the shortcomings that prior art, it is an object of the invention to provide a kind of encapsulation of face recognition chip
Structure and method for packing, for solve in the prior art that face recognition chip packaging technology is complicated, cost is high and mechanical strength compared with
The problem of poor.
In order to achieve the above objects and other related objects, the present invention provides a kind of encapsulating structure of face recognition chip, institute
Stating encapsulating structure includes：Re-wiring layer, including the first face and second face relative with first face, the rewiring
First face of layer, which makes, metal and metal coupling under salient point；Face recognition chip, the side wall of the face recognition chip make
There is wire so that the front-side circuit of the face recognition chip to be led to the side wall of the face recognition chip；The face identifies core
Piece is installed on the second face of the re-wiring layer by ACF out-phase conducting resinls, realizes the face recognition chip side wall
The electric connection of wire and the re-wiring layer, wherein, the back side of the face recognition chip is toward the rewiring
Layer；Glass cover-plate, it is packaged in the face recognition chip, forms package cavity；And encapsulating material, it is surrounded on the face and knows
Other chip and the glass cover-plate surrounding, and the glass cover-plate is exposed to the encapsulating material.
Preferably, the re-wiring layer includes patterned dielectric layer and patterned metal wiring layer；
Preferably, the material of the dielectric layer includes epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass,
One or both of fluorine-containing glass combination of the above, the material of the metal wiring layer are included in copper, aluminium, nickel, gold, silver, titanium
One or more combination.
Preferably, the metal coupling includes copper post, the nickel dam positioned at the copper post upper surface and positioned at the nickel dam
On solder bump.
Preferably, the metal barrier includes nickel dam, and the material of the solder bump includes one kind in lead, tin and silver
Or include the alloy of any one above-mentioned solder metal.
Preferably, the face recognition chip includes substrate, recognition of face region and the shape being formed in the substrate
The pad in basal edge region described in Cheng Yu, the pad and the recognition of face region are electrically connected with, the wire producing in
The side wall of the face recognition chip simultaneously extends to the pad to realize electric connection.
Preferably, the side wall of the face recognition chip is arranged to sloped sidewall, wherein, the sloped sidewall and the people
The front of face identification chip is in that angle is that 100~150 ° of wires lead to the front-side circuit of the face recognition chip
The side wall of the face recognition chip.
Preferably, the top surface of the top surface of the encapsulating material and the glass cover-plate maintains an equal level.
Preferably, the glass cover-plate is packaged in the face recognition chip based on golden tin bonded layer, forms package cavity.
Preferably, the encapsulating material includes one kind in polyimides, silica gel and epoxy resin.
The present invention also provides a kind of method for packing of face recognition chip, including：1) support substrate is provided, in the lining
Basal surface forms separating layer；2) in forming re-wiring layer in the separating layer, the re-wiring layer is included towards described point
First face of absciss layer and second face relative with first face；3) face recognition chip is provided, in the recognition of face
The side wall of chip makes wire so that the front-side circuit of the face recognition chip to be led to the side wall of the face recognition chip；
4) face recognition chip is installed on the re-wiring layer by ACF out-phase conducting resinl, realizes the recognition of face
The electric connection of the wire of chip side wall and the re-wiring layer, wherein, the back side of the face recognition chip is toward institute
State re-wiring layer；5) in packaged glass cover plate in the face recognition chip, package cavity is formed；6) carried out using encapsulating material
Encapsulation, the glass cover-plate are exposed to the encapsulating material；7) based on the separating layer separate the support substrate with it is described heavy
New route layer, expose the first face of the re-wiring layer；And 8) made in the first face of the re-wiring layer under salient point
Metal and metal coupling.
Preferably, the support substrate includes glass substrate, metal substrate, Semiconductor substrate, polymer substrate and ceramics
One kind in substrate；The separating layer includes one kind in adhesive tape and polymeric layer, and the polymeric layer uses spin coating work first
Skill is coated on the support substrate surface, then makes its curing molding using ultra-violet curing or heat curing process.
Preferably, step 2), which makes the re-wiring layer, includes step：2-1) use chemical vapor deposition method or thing
Physical vapor deposition technique forms dielectric layer in the separation layer surface, and the dielectric layer is performed etching to form patterned Jie
Matter layer；2-2) using chemical vapor deposition method, evaporation process, sputtering technology, electroplating technology or chemical plating process in the figure
Shape dielectric layer surface forms metal level, and the metal level is performed etching to form patterned metal wiring layer.
Preferably, the material of the dielectric layer includes epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass,
One or both of fluorine-containing glass combination of the above, the material of the metal wiring layer are included in copper, aluminium, nickel, gold, silver, titanium
One or more combination.
Preferably, the face recognition chip includes substrate, recognition of face region and the shape being formed in the substrate
The pad in basal edge region described in Cheng Yu, the pad and the recognition of face region are electrically connected with, the wire producing in
The side wall of the face recognition chip simultaneously extends to the pad to realize electric connection.
Preferably, step 3) includes：The side wall of the face recognition chip 3-1) is arranged to sloped sidewall, wherein, institute
It is in that angle is 100~150 ° to state sloped sidewall and the front of the face recognition chip；3-2) in the face recognition chip
Sloped sidewall make wire so that the front-side circuit of the face recognition chip to be led to the inclination of the face recognition chip
Side wall.
Preferably, step 8) includes：8-1) metal under salient point is made in the first face of the re-wiring layer；8-2) use
Galvanoplastic metal surface under the salient point forms copper post；8-3) metal barrier is formed using galvanoplastic in the copper post surface
Layer；Solder metal 8-4) is formed in the metal barrier layer surface using galvanoplastic, and using high temperature reflow processes in the gold
Belong to barrier layer surface and form solder bump；Wherein, the metal barrier includes nickel dam, and the material of the solder bump includes
One kind in lead, tin and silver or the alloy for including any one above-mentioned solder metal.
Preferably, using encapsulating material encapsulate the face recognition chip method include compression forming, transfer modling into
One kind in type, fluid-tight shaping, vacuum lamination and spin coating, the encapsulating material include polyimides, silica gel and epoxy resin
In one kind.
Preferably, the encapsulating material is surrounded on the face recognition chip and the glass cover-plate surrounding, and described
The top surface of the top surface of encapsulating material and the glass cover-plate maintains an equal level.
Preferably, in step 5), based on golden tin bonded layer in packaged glass cover plate in the face recognition chip, envelope is formed
It behave affectedly.
As described above, the encapsulating structure and method for packing of the face recognition chip of the present invention, have the advantages that：
First, the present invention uses the encapsulation face recognition chip and glass cover-plate of encapsulating material enclosed, encapsulating structure
Mechanical performance is stronger, substantially increases durable performance and the life-span of chip；
Second, method for packing of the invention and structure are simpler, can effectively reduce the cost of encapsulation；
3rd, the present invention encapsulates face recognition chip only with a glass cover-plate, greatly reduces the difficult processing of glass
Degree and processing cost；
4th, face recognition chip of the invention uses lateral conduction, and pin configuration is simple, and using encapsulating material to people
The wire of face identification chip side is packaged protection, substantially increases the stability of wire, can effectively improve yield.
Brief description of the drawings
Fig. 1 is shown as the structural representation of the encapsulating structure of face recognition chip of the prior art.
Fig. 2~Figure 11 is shown as the structural representation that each step of method for packing of the face recognition chip of the present invention is presented
Figure, wherein, Figure 11 is shown as the structural representation of the encapsulating structure of the face recognition chip of the present invention.
Component label instructions
201 support substrates
202 separating layers
203 re-wiring layers
30 face recognition chips
301 substrates
302 recognition of face regions
303 pads
204 ACF out-phase conducting resinls
205 wires
206 glass cover-plates
207 gold medal tin bonded layers
208 encapsulating materials
Metal under 209 salient points
210 metal couplings
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Refer to Fig. 2~Figure 11.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, the component relevant with the present invention is only shown in illustrating then rather than according to package count during actual implement
Mesh, shape and size are drawn, and kenel, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its
Assembly layout kenel may also be increasingly complex.
As shown in Fig. 2~Figure 11, the present embodiment provides a kind of method for packing of face recognition chip 30, including：
As shown in Figure 2 to 3, step 1) is carried out first, there is provided a support substrate 201, is formed and divided in the substrate surface
Absciss layer 202.
As an example, the support substrate 201 include glass substrate, metal substrate, Semiconductor substrate, polymer substrate and
One kind in ceramic substrate.In the present embodiment, the support substrate 201 is from being glass substrate, the glass substrate cost
It is relatively low, separating layer 202 easily is formed on its surface, and the difficulty of follow-up stripping technology can be reduced.
As an example, the separating layer 202 includes one kind in adhesive tape and polymeric layer, the polymeric layer uses first
Spin coating proceeding is coated on the surface of support substrate 201, then makes its curing molding using ultra-violet curing or heat curing process.
In the present embodiment, the separating layer 202 is formed at the support by spin coating proceeding and served as a contrast from being heat-curable glue
After on bottom 201, its curing molding is made by heat curing process.Heat-curable glue stable performance, surface is more smooth, is advantageous to follow-up
The making of re-wiring layer 203, also, in follow-up stripping technology, the difficulty of stripping is relatively low, can be obtained after stripping complete
And re-wiring layer 203 of good performance.
As shown in figure 4, then carry out step 2), in the separating layer 202 formed re-wiring layer 203, it is described again
Wiring layer 203 is included towards the first face of the separating layer 202 and second face relative with first face.
As an example, step 2), which makes the re-wiring layer 203, includes step：
Step 2-1), using chemical vapor deposition method or physical gas-phase deposition in the surface shape of separating layer 202
Perform etching to form patterned dielectric layer into dielectric layer, and to the dielectric layer.
As an example, the material of the dielectric layer includes epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorus silicon glass
One or both of glass, fluorine-containing glass combination of the above.In the present embodiment, it is silica that the dielectric layer, which is selected,.
Step 2-2), using chemical vapor deposition method, evaporation process, sputtering technology, electroplating technology or chemical plating process
Metal level is formed in the patterned media layer surface, and the metal level is performed etching to form patterned metal line
Layer.
As an example, the material of the metal wiring layer is included more than one or both of copper, aluminium, nickel, gold, silver, titanium
Combination.In the present embodiment, the material selection of the metal wiring layer is copper.
It should be noted that the re-wiring layer 203 can include the multiple dielectric layers stacked gradually and multiple gold
Belong to wiring layer, according to line demand, each layer metal wiring layer is realized by each dielectric layer being patterned or being made through hole
Between interconnection, to realize the line demand of difference in functionality.
As shown in figure 5, then carry out step 3), there is provided a face recognition chip 30, in the face recognition chip 30
Side wall makes wire 205 so that the front-side circuit of the face recognition chip 30 to be led to the side of the face recognition chip 30
Wall.
As an example, as shown in figure 5, the face recognition chip 30 includes substrate 301, it is formed in the substrate 301
Recognition of face region 302 and be formed at the pad 303 of the fringe region of substrate 301, the pad 303 and the face
Identification region 302 is electrically connected with, and the wire 205 is made in the side wall of the face recognition chip 30 and extends to the pad
303 are electrically connected with realizing.
Specifically, step 3) includes：
Step 3-1), there is provided a face recognition chip 30, the side wall of the face recognition chip 30 is arranged to inclined side
Wall, wherein, the front of the sloped sidewall and the face recognition chip 30 is in that angle is 100~150 °, preferably 110~
130°。
Step 3-2), wire 205 is made with by the recognition of face core in the sloped sidewall of the face recognition chip 30
The front-side circuit of piece 30 leads to the sloped sidewall of the face recognition chip 30.
The side wall of the face recognition chip 30 is arranged to sloped sidewall, the wire 205 and institute can be effectively improved
The difficulty of front-side circuit connection is stated, and improves the mechanical performance of the wire 205.
As shown in fig. 6, then carrying out step 4), the face recognition chip 30 is installed by ACF out-phase conducting resinl 204
In the wire 205 and the re-wiring layer 203 of on the re-wiring layer 203, realizing the side wall of face recognition chip 30
Electric connection, wherein, the back side of the face recognition chip 30 is toward the re-wiring layer 203.
The present invention uses anisotropic conductive adhesive paste (anisotropicconductivefilm, acf), by the recognition of face
Chip 30 is installed on the re-wiring layer 203, realize the wire 205 of the side wall of face recognition chip 30 with it is described again
The electric connection of wiring layer 203 so that electric current can only be propagated by the direction of the vertical re-wiring layer 203, and can not carry out
Horizontal current spread, have unilateal conduction and glued fixed function, the metal level being avoided that in the re-wiring layer 203 concurrently
Between short circuit, while the short circuit between the wire 205 of the recognition of face can be avoided.
As shown in fig. 7, then carrying out step 5), in packaged glass cover plate 206 in the face recognition chip 30, envelope is formed
It behave affectedly.
As an example, formed based on golden tin bonded layer 207 in packaged glass cover plate 206 in the face recognition chip 30
Package cavity.
As shown in figure 8, then carrying out step 6), it is packaged using encapsulating material 208, the glass cover-plate 206 exposes
In the encapsulating material 208.
As an example, the method for the face recognition chip 30 is encapsulated using encapsulating material 208 includes compression forming, transmission
One kind in molded, fluid-tight shaping, vacuum lamination and spin coating, the encapsulating material 208 include polyimides, silica gel and
One kind in epoxy resin.After encapsulation, the glass cover-plate 206 is exposed to the encapsulating material 208, as detection window, with
The function of recognition of face is realized beneficial to it.
As an example, the encapsulating material 208 is surrounded on the face recognition chip 30 and the glass cover-plate 206 4
Week, and the top surface of the top surface of the encapsulating material 208 and the glass cover-plate 206 maintains an equal level.The encapsulating material 208 can be to institute
State face recognition chip 30 and the glass cover-plate 206 carries out structural defence, improve mechanical performance, again can be to recognition of face
The wire 205 of the side wall of chip 30 is protected, and improves stability and the life-span of wire 205.
As shown in figure 9, then carry out step 7), based on the separating layer 202 separate the support substrate with it is described again
Wiring layer 203, expose the first face of the re-wiring layer 203.
As an example, the attribute according to the separating layer 202, can use such as mechanical stripping, laser lift-off, chemical stripping
The methods of (such as wet etching), separates the support substrate 201 and the re-wiring layer 203.
As shown in Figure 10~Figure 11, step 8) is finally carried out, is made in the first face of the re-wiring layer 203 under salient point
Metal 209 and metal coupling 210.
As an example, the metal coupling 210 can select for copper post, nickel post, solder metal (such as tin ball), copper post and
The combination of the combination of solder metal, nickel post and solder metal, or the combination etc. of copper post, metal barrier and solder metal.
In the present embodiment, the metal coupling 210 is from the combination for copper post, metal barrier and solder metal, institute
Stating the preparation method of metal coupling 210 includes step：
Step 8-1) metal 209 under the first face of the re-wiring layer 203 making salient point；
Step 8-2) using galvanoplastic, the surface of metal 209 forms copper post under the salient point；
Step 8-3) use galvanoplastic to form metal barrier in the copper post surface；
Step 8-4) use galvanoplastic to form solder metal in the metal barrier layer surface, and use high temperature reflow processes
Solder bump is formed in the metal barrier layer surface.
As an example, the metal barrier includes nickel dam, the material of the solder bump includes one in lead, tin and silver
Kind or the alloy for including any one above-mentioned solder metal.
The copper post of high quality can be prepared using galvanoplastic, improves the quality of metal coupling 210.The metal barrier
The diffusion of solder metal can be stopped, improve the electrical property of metal coupling 210.
As shown in figure 11, the present embodiment also provides a kind of encapsulating structure of face recognition chip 30, the encapsulating structure bag
Include：Re-wiring layer 203, including the first face and second face relative with first face, the of the re-wiring layer 203
Simultaneously making has metal 209 and metal coupling 210 under salient point；Face recognition chip 30, the side wall of the face recognition chip 30
Making has wire 205 so that the front-side circuit of the face recognition chip 30 to be led to the side wall of the face recognition chip 30；
The face identification chip is installed in by ACF out-phase conducting resinl 204 on second face of the re-wiring layer 203, described in realization
The electric connection of the wire 205 of the side wall of face recognition chip 30 and the re-wiring layer 203, wherein, the recognition of face core
The back side of piece 30 is toward the re-wiring layer 203；Glass cover-plate 206, it is packaged in the face recognition chip 30, is formed
Package cavity；And encapsulating material 208, the face recognition chip 30 and the surrounding of the glass cover-plate 206 are surrounded on, and it is described
Glass cover-plate 206 is exposed to the encapsulating material 208.
As an example, the re-wiring layer 203 includes patterned dielectric layer and patterned metal wiring layer；
As an example, the material of the dielectric layer includes epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorus silicon glass
One or both of glass, fluorine-containing glass combination of the above, the material of the metal wiring layer are included in copper, aluminium, nickel, gold, silver, titanium
One or more kinds of combinations.
As an example, the metal coupling 210 includes copper post, the nickel dam positioned at the copper post upper surface and positioned at institute
State the solder bump on nickel dam.
As an example, the metal barrier includes nickel dam, the material of the solder bump includes one in lead, tin and silver
Kind or the alloy for including any one above-mentioned solder metal.
As an example, the face recognition chip 30 includes substrate 301, the recognition of face being formed in the substrate 301
Region 302 and the pad 303 for being formed at the fringe region of substrate 301, the pad 303 and the recognition of face region
302 are electrically connected with, and the wire 205 is made in the side wall of the face recognition chip 30 and extends to the pad 303 with reality
Now it is electrically connected with.
As an example, the side wall of the face recognition chip 30 is arranged to sloped sidewall, wherein, the sloped sidewall and institute
The front for stating face recognition chip 30 be in angle be 100~150 ° of wires 205 by the face recognition chip 30 just
Face circuit leads to the side wall of the face recognition chip 30.
As an example, the top surface of the top surface of the encapsulating material 208 and the glass cover-plate 206 maintains an equal level.
As an example, the glass cover-plate 206 is packaged in the face recognition chip 30 based on golden tin bonded layer 207,
Form package cavity.
As an example, the encapsulating material 208 includes one kind in polyimides, silica gel and epoxy resin.
As described above, the encapsulating structure and method for packing of the face recognition chip 30 of the present invention, have the advantages that：
First, the present invention uses the encapsulation face recognition chip 30 and glass cover-plate 206 of the enclosed of encapsulating material 208, envelope
The mechanical performance of assembling structure is stronger, substantially increases durable performance and the life-span of chip；
Second, method for packing of the invention and structure are simpler, can effectively reduce the cost of encapsulation；
3rd, the present invention encapsulates face recognition chip 30 only with a glass cover-plate 206, greatly reduces adding for glass
Work difficulty and processing cost；
4th, face recognition chip 30 of the invention uses lateral conduction, and pin configuration is simple, and uses encapsulating material
The wire 205 of 208 pairs of sides of face recognition chip 30 is packaged protection, substantially increases the stability of wire 205, can be effective
Improve yield.
So the present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (20)
1. a kind of encapsulating structure of face recognition chip, it is characterised in that the encapsulating structure includes：
Re-wiring layer, including the first face and second face relative with first face, the first face of the re-wiring layer
Making has metal and metal coupling under salient point；
Face recognition chip, the side wall of the face recognition chip, which makes, has wire so that the front of the face recognition chip is electric
Road leads to the side wall of the face recognition chip；The face identification chip by ACF out-phase conducting resinls be installed in it is described again
On second face of wiring layer, the wire of the face recognition chip side wall and the electric connection of the re-wiring layer are realized, its
In, the back side of the face recognition chip is toward the re-wiring layer；
Glass cover-plate, it is packaged in the face recognition chip, forms package cavity；
Encapsulating material, the face recognition chip and the glass cover-plate surrounding are surrounded on, and the glass cover-plate is exposed to
The encapsulating material.
2. the encapsulating structure of face recognition chip according to claim 1, it is characterised in that：The re-wiring layer includes
Patterned dielectric layer and patterned metal wiring layer.
3. the encapsulating structure of face recognition chip according to claim 2, it is characterised in that：The material bag of the dielectric layer
Include one or both of epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass, fluorine-containing glass combination of the above, institute
Stating the material of metal wiring layer includes one or both of copper, aluminium, nickel, gold, silver, titanium combination of the above.
4. the encapsulating structure of face recognition chip according to claim 1, it is characterised in that：The metal coupling includes copper
Post, the nickel dam positioned at the copper post upper surface and the solder bump on the nickel dam.
5. the encapsulating structure of face recognition chip according to claim 4, it is characterised in that：The metal barrier includes
Nickel dam, the material of the solder bump include one kind in lead, tin and silver or include the alloy of any one above-mentioned solder metal.
6. the encapsulating structure of face recognition chip according to claim 1, it is characterised in that：The face recognition chip bag
Substrate is included, the recognition of face region that is formed in the substrate and the pad for being formed at the basal edge region, the weldering
Disk and the recognition of face region are electrically connected with, the wire producing in the face recognition chip side wall and extend to described
Pad is electrically connected with realizing.
7. the encapsulating structure of face recognition chip according to claim 1, it is characterised in that：The face recognition chip
Side wall is arranged to sloped sidewall, wherein, the front of the sloped sidewall and the face recognition chip be in angle be 100~
150 ° of wires lead to the front-side circuit of the face recognition chip side wall of the face recognition chip.
8. the encapsulating structure of face recognition chip according to claim 1, it is characterised in that：The top surface of the encapsulating material
Maintain an equal level with the top surface of the glass cover-plate.
9. the encapsulating structure of face recognition chip according to claim 1, it is characterised in that：The glass cover-plate is based on gold
Tin bonded layer is packaged in the face recognition chip, forms package cavity.
10. the encapsulating structure of face recognition chip according to claim 1, it is characterised in that：The encapsulating material includes
One kind in polyimides, silica gel and epoxy resin.
A kind of 11. method for packing of face recognition chip, it is characterised in that including：
1) support substrate is provided, separating layer is formed in the substrate surface；
2) in forming re-wiring layer in the separating layer, the re-wiring layer include towards the first face of the separating layer with
And second face relative with first face；
3) face recognition chip is provided, wire is made with by the face recognition chip in the side wall of the face recognition chip
Front-side circuit lead to the side wall of the face recognition chip；
4) face recognition chip is installed on the re-wiring layer by ACF out-phase conducting resinl, realizes the face
The electric connection of the wire of identification chip side wall and the re-wiring layer, wherein, the back side direction of the face recognition chip
In the re-wiring layer；
5) in packaged glass cover plate in the face recognition chip, package cavity is formed；
6) it is packaged using encapsulating material, the glass cover-plate is exposed to the encapsulating material；
7) support substrate and the re-wiring layer are separated based on the separating layer, exposes the first of the re-wiring layer
Face；
8) metal and metal coupling under salient point are made in the first face of the re-wiring layer.
12. the method for packing of face recognition chip according to claim 11, it is characterised in that：The support substrate includes
One kind in glass substrate, metal substrate, Semiconductor substrate, polymer substrate and ceramic substrate；The separating layer includes adhesive tape
And one kind in polymeric layer, the polymeric layer are coated on the support substrate surface using spin coating proceeding first, then adopted
Make its curing molding with ultra-violet curing or heat curing process.
13. the method for packing of face recognition chip according to claim 11, it is characterised in that：Step 2) makes described heavy
New route layer includes step：
Dielectric layer 2-1) is formed in the separation layer surface using chemical vapor deposition method or physical gas-phase deposition, and it is right
The dielectric layer performs etching to form patterned dielectric layer；
2-2) using chemical vapor deposition method, evaporation process, sputtering technology, electroplating technology or chemical plating process in the figure
Change dielectric layer surface and form metal level, and the metal level is performed etching to form patterned metal wiring layer.
14. the method for packing of face recognition chip according to claim 13, it is characterised in that：The material of the dielectric layer
Including epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass, one or both of fluorine-containing glass combination of the above,
The material of the metal wiring layer includes one or both of copper, aluminium, nickel, gold, silver, titanium combination of the above.
15. the method for packing of face recognition chip according to claim 11, it is characterised in that：The face recognition chip
Including substrate, the recognition of face region being formed in the substrate and the pad for being formed at the basal edge region are described
Pad and the recognition of face region are electrically connected with, the wire producing in the face recognition chip side wall and extend to institute
State pad and be electrically connected with realizing.
16. the method for packing of face recognition chip according to claim 11, it is characterised in that：Step 3) includes：
The side wall of the face recognition chip 3-1) is arranged to sloped sidewall, wherein, the sloped sidewall is known with the face
The front of other chip is in that angle is 100~150 °；
3-2) wire is made so that the front-side circuit of the face recognition chip to be drawn in the sloped sidewall of the face recognition chip
Go out to the sloped sidewall of the face recognition chip.
17. the method for packing of face recognition chip according to claim 11, it is characterised in that：Step 8) includes：
8-1) metal under salient point is made in the first face of the re-wiring layer；
8-2) using galvanoplastic, metal surface forms copper post under the salient point；
8-3) metal barrier is formed using galvanoplastic in the copper post surface；
Solder metal 8-4) is formed in the metal barrier layer surface using galvanoplastic, and using high temperature reflow processes in the gold
Belong to barrier layer surface and form solder bump；
Wherein, the metal barrier includes nickel dam, the material of the solder bump include one kind in lead, tin and silver or comprising
The alloy of any one above-mentioned solder metal.
18. the method for packing of face recognition chip according to claim 11, it is characterised in that：Encapsulated using encapsulating material
The method of the face recognition chip includes one in compression forming, Transfer molding, fluid-tight shaping, vacuum lamination and spin coating
Kind, the encapsulating material includes one kind in polyimides, silica gel and epoxy resin.
19. the method for packing of face recognition chip according to claim 11, it is characterised in that：The encapsulating material surrounds
In the face recognition chip and the glass cover-plate surrounding, and the top of the top surface of the encapsulating material and the glass cover-plate
Face maintains an equal level.
20. the method for packing of face recognition chip according to claim 11, it is characterised in that：In step 5), based on gold
Tin bonded layer forms package cavity in packaged glass cover plate in the face recognition chip.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104659049A (en) * | 2015-02-15 | 2015-05-27 | 苏州科阳光电科技有限公司 | Novel semiconductor package structure |
| CN105185798A (en) * | 2015-07-14 | 2015-12-23 | 华进半导体封装先导技术研发中心有限公司 | Wafer-level packaging method of back-illuminated image sensor and packaging structure |
| CN106229325A (en) * | 2016-09-21 | 2016-12-14 | 苏州科阳光电科技有限公司 | Sensor module and preparation method thereof |
| CN207009401U (en) * | 2017-07-28 | 2018-02-13 | 中芯长电半导体（江阴）有限公司 | The encapsulating structure of face recognition chip |
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2017
- 2017-07-28 CN CN201710631902.9A patent/CN107452636B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104659049A (en) * | 2015-02-15 | 2015-05-27 | 苏州科阳光电科技有限公司 | Novel semiconductor package structure |
| CN105185798A (en) * | 2015-07-14 | 2015-12-23 | 华进半导体封装先导技术研发中心有限公司 | Wafer-level packaging method of back-illuminated image sensor and packaging structure |
| CN106229325A (en) * | 2016-09-21 | 2016-12-14 | 苏州科阳光电科技有限公司 | Sensor module and preparation method thereof |
| CN207009401U (en) * | 2017-07-28 | 2018-02-13 | 中芯长电半导体（江阴）有限公司 | The encapsulating structure of face recognition chip |
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