CN107431047A - 布线基板、电子装置以及电子模块 - Google Patents

布线基板、电子装置以及电子模块 Download PDF

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Publication number
CN107431047A
CN107431047A CN201680017683.9A CN201680017683A CN107431047A CN 107431047 A CN107431047 A CN 107431047A CN 201680017683 A CN201680017683 A CN 201680017683A CN 107431047 A CN107431047 A CN 107431047A
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China
Prior art keywords
electrode
circuit board
insulated substrate
carrying
terminal
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CN107431047B (zh
Inventor
村上健策
川崎晃
川崎晃一
森山阳介
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Kyocera Corp
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Kyocera Corp
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Abstract

本发明的布线基板(1)具有：绝缘基板(11)；在绝缘基板(11)的一个主面，设置为在俯视下沿着绝缘基板(11)的对置的一组边而对置的搭载用电极(12)；和在绝缘基板(11)的另一个主面，设置为在俯视透视下沿着绝缘基板(11)的对置的另一组边而对置的端子用电极(13)。

Description

布线基板、电子装置以及电子模块
技术领域
本发明涉及布线基板、电子装置以及电子模块。
背景技术
以往，布线基板具有：搭载用电极，其设置于绝缘基板的一个主面，搭载电子部件；端子用电极，其设置于绝缘基板的另一个主面；和布线导体，其与搭载用电极以及端子用电极连接，设置于绝缘基板的主面或内部。在将包含电子部件以及布线基板的电子装置通过焊料等接合材料例如接合于模块用基板的情况下，经由焊料等接合材料将端子用电极接合于模块用基板(参照JP特开2009-267041号公报)。
发明内容
发明要解决的课题
近年来，谋求电子装置的高功能化以及薄型化，随着布线基板的厚度不断变薄，由于电子装置使用时的绝缘基板与搭载用电极以及端子用电极的热膨胀率之差所引起的热应力从而布线基板的变形、翘曲容易变大，令人担忧在长期间使用时在电子部件与布线基板之间或者在布线基板与模块用基板之间会发生连接不良。
用于解决课题的手段
根据本发明的一个方式，布线基板具有：绝缘基板；搭载用电极，其在该绝缘基板的一个主面，设置为在俯视下沿着所述绝缘基板的对置的一组边而对置；和端子用电极，其在所述绝缘基板的另一个主面，设置为在俯视透视下沿着所述绝缘基板的对置的另一组边而对置。
根据本发明的另一方式，电子装置具有上述结构的布线基板、和搭载于该布线基板的电子部件。
根据本发明的另一方式，电子模块具有：上述结构的电子装置；和模块用基板，其具有连接焊盘，并经由接合材料将所述电子装置连接于所述连接焊盘。
发明效果
本发明的一个方式所涉及的布线基板具有：绝缘基板；搭载用电极，其在绝缘基板的一个主面，设置为在俯视下沿着绝缘基板的对置的一组边而对置；和端子用电极，其在绝缘基板的另一个主面，设置为在俯视透视下沿着绝缘基板的对置的另一组边而对置。根据该结构，因为将搭载用电极和端子用电极配置为在彼此不同的方向上延伸，所以即使在电子装置使用时从电子部件对布线基板施加了较高的热，也能够抑制绝缘基板与搭载用电极以及绝缘基板与端子用电极的热膨胀率之差所引起的热应力向同一方向的集中，能够抑制布线基板的变形、翘曲，能够使电子部件与布线基板之间或者布线基板与模块用基板之间的连接良好，能够成为可靠性优异的布线基板。
本发明的另一方式所涉及的电子装置通过具有上述结构的布线基板和搭载于布线基板的电子部件，从而能够成为长期可靠性优异的电子装置。
本发明的另一方式所涉及的电子模块通过具有上述结构的电子装置、和具有连接焊盘并经由接合材料将电子装置连接于连接焊盘的模块用基板，从而能够成为长期可靠性优异的电子模块。
附图说明
图1(a)是表示本发明的第1实施方式中的电子装置的俯视图，(b)是(a)的仰视图。
图2(a)是图1(a)所示的电子装置的A-A线处的纵剖面图，(b)是图1(a)所示的电子装置的B-B线处的纵剖面图。
图3(a)以及(b)是表示使用了图1中的电子装置的安装于模块用基板的电子模块的纵剖面图。
图4(a)是表示本发明的第1实施方式的另一例中的电子装置的俯视图，(b)是(a)的仰视图。
图5(a)是表示本发明的第1实施方式的另一例中的电子装置的俯视图，(b)是(a)的仰视图。
图6(a)是表示本发明的第2实施方式中的电子装置的俯视图，(b)是(a)的仰视图。
图7是图6所示的电子装置中的布线基板的内部俯视图。
图8(a)是图6(a)所示的电子装置的A-A线处的纵剖面图，(b)是图1(a)所示的电子装置的B-B线处的纵剖面图。
图9是表示本发明的第2实施方式的另一例中的布线基板的俯视透视图。
图10(a)是表示本发明的第3实施方式中的电子装置的俯视图，(b)是(a)的仰视图。
图11是图10所示的电子装置中的布线基板的内部仰视图。
图12(a)是图10(a)所示的电子装置的A-A线处的纵剖面图，(b)是图1(a)所示的电子装置的B-B线处的纵剖面图。
图13是表示本发明的第3实施方式的另一例中的布线基板的仰视透视图。
具体实施方式
参照附图对本发明的几个例示性的实施方式进行说明。
(第1实施方式)
本发明的第1实施方式中的发光装置如图1以及图2所示的例子那样，包含布线基板1和设置于布线基板1的上表面的电子部件2。电子装置如图3所示的例子那样，例如使用接合材料6连接于构成电子模块的模块用基板5上的连接焊盘51。
本实施方式中的布线基板1具有：绝缘基板11；搭载用电极12，其设置于绝缘基板11的一个主面；端子用电极13，其设置于绝缘基板11的另一个主面；和布线导体14，其与搭载用电极12以及端子用电极13连接，设置于绝缘基板11的表面或内部。搭载用电极12设置为在俯视下沿着绝缘基板11的对置的一组边而对置。端子用电极13设置为在俯视透视(perspective plan view)下沿着绝缘基板11的对置的另一组边而对置。在图1～图3中，电子装置安装于虚拟的xyz空间中的xy平面。在图1～图3中，所谓上方向，是指虚拟的z轴的正方向。另外，以下的说明中的上下的区别是为了方便起见，并非对实际使用布线基板1等时的上下进行限定。
在图1(a)中，搭载用电极12的外缘与电子部件2重叠的部分用虚线表示，此外，在图1中，布线导体14(贯通导体)用虚线表示。在图1(b)中，电子部件2用双点划线表示。
绝缘基板11具有一个主面(图1以及图2中为上表面)以及另一个主面(图1以及图2中为下表面)。绝缘基板11在俯视下，具有针对一个主面以及另一个主面分别具有两组对置的边(4边)的矩形的板状的形状。绝缘基板11作为用于支承电子部件2的支承体而发挥功能，在设置于绝缘基板11的一个主面的搭载用电极12上经由焊料凸点等连接构件3对电子部件2进行粘接并固定。
绝缘基板11例如能够使用氧化铝质烧结体(氧化铝陶瓷)、氮化铝质烧结体、莫来石质烧结体或玻璃陶瓷烧结体等陶瓷。绝缘基板11例如若是氧化铝质烧结体的情况，则向氧化铝(Al2O3)、氧化硅(SiO2)、氧化镁(MgO)、氧化钙(CaO)等的原料粉末中添加混合适当的有机粘合剂以及溶剂等来制作泥浆物。通过采用现有公知的刮刀法或压延辊法等将该泥浆物成型为片状来制作陶瓷生片。接下来，对该陶瓷生片实施适当的冲裁加工，并且根据需要将陶瓷生片层叠多片来形成生成型体，在高温(约1600℃)下对该生成型体进行烧成，由此制作绝缘基板11。
搭载用电极12在绝缘基板11的一个主面设置为在俯视下沿着绝缘基板11的对置的一组边而对置。端子用电极13在绝缘基板11的另一个主面设置为在俯视透视下沿着绝缘基板11的对置的另一组边而对置。例如，在图1以及图2所示的例子中，2个搭载用电极12沿着对置的一组边与Y方向分别平行地设置，搭载用电极12的长度是Y方向的长度比X方向的长度长。2个端子用电极13沿着另一组边与X方向分别平行地设置，端子用电极13的长度是X方向的长度比Y方向的长度长。搭载用电极12用于将搭载于布线基板1的电子部件2与模块用基板5进行电连接、或者将布线基板1与电子部件2进行接合。端子用电极13用于将搭载于布线基板1的电子部件2与模块用基板5进行电连接、或者将布线基板1与模块用基板5进行接合。布线导体14用于将搭载用电极12与端子用电极13进行电连接，并将搭载于布线基板1的电子部件2与模块用基板5进行电连接。布线导体14包含：设置于绝缘基板11的表面或内部的布线层、和贯通绝缘基板11将位于上下的布线层彼此进行电连接的贯通导体。
搭载用电极12、端子用电极13、布线导体14的材料，例如是以钨(W)、钼(Mo)、锰(Mn)、银(Ag)或铜(Cu)等为主要成分的金属粉末金属化物。搭载用电极12、端子用电极13、布线导体14例如通过利用丝网印刷法等印刷手段在绝缘基板11用的陶瓷生片上对搭载用电极12、端子用电极13、布线导体14用的金属化膏剂进行印刷涂敷，并与绝缘基板11用的陶瓷生片一起进行烧成，从而形成。此外，贯通导体例如通过利用基于模具或冲孔(punching)的冲裁加工或激光加工等加工方法在绝缘基板11用的陶瓷生片上形成贯通导体用的贯通孔，利用上述印刷手段向该贯通孔中填充贯通导体用的金属化膏剂，并与绝缘基板11用的陶瓷生片一起进行烧成，从而形成。金属化膏剂通过在上述的金属粉末中添加适当的溶剂以及粘合剂并进行混炼，从而调整为适当的粘度来制作。另外，为了提高与绝缘基板11的接合强度，也可以包含玻璃粉末、陶瓷粉末。
在搭载用电极12、端子用电极13、布线导体14的从绝缘基板11露出的表面，粘附镍、金等耐蚀性优异的金属镀覆层。能够降低搭载用电极12、端子用电极13、布线导体14的腐蚀，并且能够使搭载用电极12与电子部件2的接合、搭载用电极12与连接构件3的连接、或模块用基板5与端子用电极13牢固地接合。例如，在搭载用电极12、端子用电极13、布线导体14的从绝缘基板11露出的表面，依次粘附厚度1～10μm左右的镍镀覆层和厚度0.1～3μm左右的金镀覆层。
此外，镀覆层并不限于镍镀覆层/金镀覆层，也可以是包含镍镀覆层/金镀覆层/银镀覆层、或者镍镀覆层/钯镀覆层/金镀覆层等的其他的镀覆层。
在设置于布线基板1的一个主面的搭载用电极12上，通过搭载电子部件2而能够制作电子装置。搭载于布线基板1的电子部件2是IC芯片或LSI芯片等半导体元件、发光元件、水晶振子或压电振子等压电元件以及各种传感器等。例如，在电子部件2是倒装片型的半导体元件的情况下，半导体元件通过经由焊料凸点、金凸点或导电性树脂(各向异性导电树脂等)等连接构件3，将半导体元件的电极与搭载用电极12电连接以及机械连接，从而搭载于布线基板1。此外，例如，在电子部件2是引线键合型的半导体元件的情况下，半导体元件通过低熔点钎料或导电性树脂等接合构件而被固定在搭载电子部件2的一个搭载用电极12上后，经由键合线等连接构件3将半导体元件的电极与另一个搭载用电极12进行电连接，从而搭载于布线基板1。此外，在布线基板1上，既可以搭载多个电子部件2，也可以根据需要，搭载电阻元件、电容元件、齐纳二极管等其他的电子部件。此外，电子部件2根据需要，通过由树脂、玻璃等构成的密封件4、由树脂、玻璃、陶瓷、金属等构成的盖体等来进行密封。
本实施方式的电子装置如图5所示的例子那样，经由焊料等接合材料6而连接于模块用基板5的连接焊盘51，从而成为电子模块。
根据本实施方式的布线基板1，通过具有绝缘基板11、在绝缘基板11的一个主面设置为在俯视下沿着绝缘基板11的对置的一组边而对置的搭载用电极12、和在绝缘基板11的另一个主面设置为在俯视透视下沿着绝缘基板11的对置的另一组边而对置的端子用电极13，从而搭载用电极12和端子用电极13配置为在彼此不同的方向上延伸，所以即使在电子装置使用时从电子部件2对布线基板1施加了较高的热，也能够抑制绝缘基板11与搭载用电极12以及绝缘基板11与端子用电极13的热膨胀率之差所引起的热应力向同一方向的集中，能够抑制布线基板1的变形、翘曲，能够使电子部件2与布线基板1之间或者布线基板1与模块用基板5之间的连接良好，能够成为可靠性优异的布线基板1。
本实施方式中的布线基板1能够在薄型且高输出的电子装置中适宜地使用，能够提高布线基板1的可靠性。例如，在作为电子部件2而搭载发光元件的情况下，能够作为薄型且高亮度的发光装置用的布线基板1来适宜地使用。
若搭载用电极12和端子用电极13如图1以及图2所示的例子那样，在俯视透视下正交，则即使在电子装置使用时从电子部件2对布线基板1施加了较高的热，也能够有效地抑制搭载用电极12以及端子用电极13的膨胀向同一方向的集中，能够抑制在布线基板1发生变形、翘曲，能够使电子部件2与布线基板1之间或者布线基板1与模块用基板5之间的连接更加良好，能够成为可靠性优异的布线基板1。在此，所谓在俯视透视下正交，是表示在一个方向(图1中Y方向)较长的搭载用电极12和在另一个方向(图1中X方向)上较长的端子用电极13各自的长边方向彼此正交。
此外，通过搭载用电极12和端子用电极13彼此正交地重叠，从而在俯视透视下，未设置搭载用电极12或端子用电极13的只有绝缘基板11的部分减少，能够有效地抑制光向外部的泄露。
此外，若如图1以及图2所示的例子那样，2个搭载用电极12配置为在俯视透视下均与2个端子用电极13重叠，则即使在电子装置使用时从电子部件2对布线基板1施加了较高的热，也能够更有效地抑制绝缘基板11与搭载用电极12以及绝缘基板11与端子用电极13的热膨胀率之差所引起的热应力向同一方向的集中，能够抑制在布线基板1发生变形、翘曲，此外在俯视透视下搭载用电极12和端子用电极13重叠的部分较大，能够提高布线基板1的机械强度，能够降低在绝缘基板11产生裂纹等的可能性。
在俯视下，设置为对置的搭载用电极12的总面积设置于绝缘基板11的一个主面的面积的30％以上的区域，优选设置于50％以上的区域。此外，在俯视下，设置为对置的端子用电极13的总面积设置于绝缘基板11的另一个主面的面积的30％以上的区域，优选设置于50％以上的区域。
此外，在搭载用电极12和端子用电极13正交的结构中，搭载用电极12和端子用电极13重叠的区域在俯视透视下，优选在搭载用电极12的面积的20％以上的区域中与端子用电极13重叠，更优选在搭载用电极12的面积的50％以上的区域中与端子用电极13重叠。进而，对于端子用电极13，在俯视透视下，也优选在端子用电极13的面积的20％以上的区域中与搭载用电极12重叠，更优选在端子用电极13的面积的50％以上的区域中与搭载用电极12重叠。像这样，在搭载用电极12和端子用电极13正交的结构中，若搭载用电极12和端子用电极13遍及较大的区域而重叠，则能够进一步提高上述效果。此外，若对置设置的搭载用电极12的总面积设置为对置设置的端子用电极13的总面积的0.5倍以上且1.5倍以下，则能够使上述效果更加有效，故优选。此外，若对置设置的搭载用电极12的厚度设置为对置设置的端子用电极13的厚度的0.8倍以上且1.2倍以下，则能够更加有效，故优选。
此外，搭载用电极12以及端子用电极13也可以如图4所示的例子那样，在绝缘基板11的主面设置有3个以上。在该情况下，也与上述同样地，对置设置的搭载用电极12的总面积优选设置为对置设置的端子用电极13的总面积的0.8倍以上且1.2倍以下。
在图4(a)所示的例子中，3个搭载用电极12在绝缘基板11的一个主面，设置为沿着绝缘基板11的一组边分别对置。如图4(b)所示的例子那样，3个端子用电极13在绝缘基板11的另一个主面，设置为沿着绝缘基板11的另一组边分别相互对置。
在图4所示的例子中，搭载用电极12或端子用电极13也优选配置为彼此正交并且在俯视透视下与多个电极重叠。
此外，也可以如图5所示的例子那样，搭载用电极12彼此、或端子用电极13彼此的大小、形状不同。
另外，在图4以及图5所示的例子中，也与图1以及图2所示的例子同样地，搭载用电极12和端子用电极13优选配置为在俯视透视下彼此正交、或者与多个电极交叉。
根据本实施方式的电子装置，通过具有上述结构的布线基板1，从而关于电可靠性得到了提高。
根据本发明的另一方式所涉及的电子模块，因为上述结构的电子装置经由接合材料6而连接于模块用基板5的连接焊盘51，所以能够实现长期可靠性优异的电子模块。
(第2实施方式)
接下来，参照图6～图8对本发明的第2实施方式所涉及的电子装置进行说明。
在本发明的第2实施方式中的电子装置中，与上述的实施方式的电子装置的不同之处在于，如图6～图8所示的例子那样，绝缘基板11在绝缘基板11的一个主面侧，具有在俯视下被搭载用电极12夹着的凹部15。
在图6(a)中，搭载用电极12的外缘以及凹部15的内壁和电子部件2重叠的部分与第1实施方式同样地用虚线表示，此外，在图6以及图7中，布线导体14(贯通导体)与第1实施方式同样地用虚线表示。图6(a)中的其他的电子部件7和图6(b)中的电子部件2用双点划线表示。
根据本发明的第2实施方式的布线基板1，因为与第1实施方式同样地，将搭载用电极12和端子用电极13配置为在彼此不同的方向上延伸，所以即使在电子装置使用时从电子部件2对布线基板1施加了较高的热，也能够抑制绝缘基板11与搭载用电极12以及绝缘基板11与端子用电极13的热膨胀率之差所引起的热应力向同一方向的集中，能够抑制布线基板1的变形、翘曲，能够使电子部件2与布线基板1之间或者布线基板1与模块用基板5之间的连接良好，能够成为可靠性优异的布线基板1。
此外，通过具有凹部15，例如，在作为电子部件2而使用发光元件的情况下，若将齐纳二极管等其他的电子部件7收纳在凹部15内，则与将其他的电子部件7配置于绝缘基板11的一个主面的情况相比，无需在平面方向上较大地设置用于搭载其他的电子部件7的区域，并且来自发光元件的朝向横向的光不会被阻断，因此能够成为小型且高亮度的发光装置。此外，在凹部15内，也可以封入含有荧光剂或者反射剂的树脂等，由此使发光装置的亮度良好。
如图6～图8所示的例子那样，凹部15能够作为用于搭载其他的电子部件7的区域来使用。在凹部15的底面，导出有用于与其他的电子部件7电连接的布线导体14。这样的凹部15能够通过如下方式来形成，即，对绝缘基板11用的陶瓷生片通过激光加工、基于模具的冲裁加工等，在多个陶瓷生片形成成为凹部15的贯通孔，将这些陶瓷生片层叠于未形成贯通孔的陶瓷生片。
如图6～图8所示的例子那样，凹部15设置为沿着搭载用电极12进行延伸。此时，若在俯视透视下，凹部15与设置于绝缘基板11的另一个主面的多个端子用电极13重叠，则在绝缘基板11的厚度较薄的凹部15处，能够提高机械强度，能够降低在绝缘基板11产生裂纹等的可能性。此外，如图6～图8所示的例子那样，更优选设置于绝缘基板11的内部且在凹部15的底面导出的布线导体14和多个搭载用电极12设置为各自的长边方向彼此正交地重叠。在该情况下，在搭载用电极12和布线导体14彼此正交的结构中，搭载用电极12和布线导体14重叠的区域在俯视透视下，若在搭载用电极12的面积的20％以上的区域中与布线导体14重叠，则能够使上述效果更加有效，故优选。进而，对于布线导体14，也优选在俯视透视下，在布线导体14的面积的20％以上的区域中与搭载用电极12重叠。
此外，凹部15的形状也可以在俯视下不是矩形。如图9所示的例子那样，若在俯视下，凹部15中的两端部的宽度小于中央部的宽度，例如使搭载其他的电子部件7的区域以外的凹部15的宽度比搭载其他的电子部件7的区域的凹部15的宽度小，则能够抑制布线基板1的变形、翘曲。优选配置为缩短俯视下的长边方向的长度，并且向搭载用电极12对置的一侧扩宽，若使该区域与电子部件2以及设置于另一个主面的端子用电极13重叠，则能够抑制布线基板1的变形、翘曲，并且能够提高从电子部件2向布线基板1的散热性。
此外，如图9所示的例子那样，若在俯视下，搭载用电极12从两端部沿着绝缘基板11的对置的一组边延伸设置，使得包围凹部15，则在绝缘基板11的厚度较薄的凹部15处，能够提高机械强度，能够降低在绝缘基板11产生裂纹等的可能性。
第2实施方式的布线基板1能够使用与上述的第1实施方式的布线基板1同样的制造方法来制作。
(第3实施方式)
接下来，参照图10～图12对本发明的第3实施方式所涉及的电子装置进行说明。
在本发明的第3实施方式中的电子装置中，与上述的实施方式的电子装置的不同之处在于，如图10～图12所示的例子那样，绝缘基板11在绝缘基板11的另一个主面侧，具有在俯视透视下被端子用电极13夹着的凹部15。在图10(a)中，搭载用电极12的外缘和电子部件2重叠的部分与第1实施方式同样地用虚线表示，此外，在图10以及图11中，布线导体14(贯通导体)与第1实施方式同样地用虚线表示。在图10(b)中，电子部件2用双点划线表示。
根据本发明的第3实施方式的布线基板1，因为与第1实施方式同样地，将搭载用电极12和端子用电极13配置为在彼此不同的方向上延伸，所以即使在电子装置使用时从电子部件2对布线基板1施加了较高的热，也能够抑制绝缘基板11与搭载用电极12以及绝缘基板11与端子用电极13的热膨胀率之差所引起的热应力向同一方向的集中，能够抑制布线基板1的变形、翘曲，能够使电子部件2与布线基板1之间或者布线基板1与模块用基板5之间的连接良好，能够成为可靠性优异的布线基板1。
在本发明的第3实施方式的布线基板1中，如图10～图12所示的例子那样，凹部15与第2实施方式同样地，能够作为用于搭载其他的电子部件7的区域来使用。此外，在凹部15的底面，为了与其他的电子部件7进行电连接而导出有布线导体14。
如图10～图12所示的例子那样，凹部15设置为在端子用电极13之间，沿着端子用电极13在一个方向上较长地延伸。此时，若在俯视透视下，凹部15与设置于绝缘基板11的一个主面的多个搭载用电极12重叠，则在绝缘基板11的厚度较薄的凹部15处，能够提高机械强度，能够降低在绝缘基板11产生裂纹等的可能性。此外，如图10～图12所示的例子那样，更优选设置于绝缘基板11内部且在凹部15的底面导出的布线导体14和多个端子用电极13设置为各自的长边方向彼此正交地重叠。在该情况下，在端子用电极13和布线导体14正交的结构中，搭载用电极12和布线导体14重叠的区域在俯视透视下，若在端子用电极13的面积的20％以上的区域中相互重叠，则能够进一步提高上述效果，故优选。此外，进而，对于布线导体14，也优选在俯视下，在布线导体14的面积的20％以上的区域中与端子用电极13重叠。此外，与第2实施方式同样地，若在俯视下，凹部15中的两端部的宽度小于中央部的宽度，则能够抑制布线基板1的变形、翘曲。
第3实施方式的布线基板1能够使用与上述的第1实施方式或第2实施方式的布线基板1同样的制造方法来制作。
本发明并不限定于上述的实施方式例，能够进行各种变更。例如，也可以是在绝缘基板11的角部，在绝缘基板11的厚度方向上形成有倒角部或者圆弧状的缺口部的布线基板1。
此外，端子用电极13设置于绝缘基板11的另一个主面，但也可以在绝缘基板11的侧面与另一个主面之间设置孔，具有端子用电极13在孔的内面延伸的所谓凹形导体(castellation conductor)。此外，搭载用电极12也同样地，可以在设置于绝缘基板11的侧面的孔的内面延伸。
此外，也可以对第1～第3实施方式的布线基板1的方式进行组合。例如，也可以在第2实施方式的布线基板1中，将设置于绝缘基板11的另一个主面侧的端子用电极13设置3个以上，还可以在第3实施方式的布线基板1中，将设置于绝缘基板11的一个主面的搭载用电极12设置3个以上。
此外，在第1～第3实施方式的布线基板1中，搭载用电极12以及端子用电极13在俯视下，设为了矩形的形状，但例如，在俯视下，为了确认布线基板1或电子装置的朝向等，也可以是在俯视下部分地在电极的缘部设置了凸状部等的搭载用电极12或端子用电极13、或者电极的缘部被部分地去掉的搭载用电极12或端子用电极13。
此外，搭载用电极12以及端子用电极13在上述示例中，示出了通过共烧法来形成的示例，但也可以是通过后烧法或薄膜形成法等形成方法而形成的金属层。

Claims (11)

1.一种布线基板，其特征在于，具有：
绝缘基板；
搭载用电极，其在该绝缘基板的一个主面，设置为在俯视下沿着所述绝缘基板的对置的一组边而对置；和
端子用电极，其在所述绝缘基板的另一个主面，设置为在俯视透视下沿着所述绝缘基板的对置的另一组边而对置。
2.根据权利要求1所述的布线基板，其特征在于，
在俯视透视下，所述搭载用电极和所述端子用电极正交。
3.根据权利要求2所述的布线基板，其特征在于，
在俯视透视下，所述搭载用电极和所述端子用电极重叠。
4.根据权利要求1至3中任一项所述的布线基板，其特征在于，
在所述绝缘基板的一个主面，具有在俯视下被所述搭载用电极夹着的凹部。
5.根据权利要求4所述的布线基板，其特征在于，
所述凹部设置为沿着所述搭载用电极延伸，并在俯视透视下与所述端子用电极重叠。
6.根据权利要求4或5所述的布线基板，其特征在于，
在俯视下，所述搭载用电极从两端部起沿着所述绝缘基板的对置的一组边延伸设置，使得包围所述凹部。
7.根据权利要求1至3中任一项所述的布线基板，其特征在于，
在所述绝缘基板的另一个主面，具有在俯视透视下被所述端子用电极夹着的凹部。
8.根据权利要求7所述的布线基板，其特征在于，
所述凹部设置为沿着所述端子用电极延伸，并在俯视透视下与所述搭载用电极重叠。
9.根据权利要求5、6、8中任一项所述的布线基板，其特征在于，
在俯视下，所述凹部的两端部的宽度比中央部的宽度小。
10.一种电子装置，其特征在于，具有：
权利要求1至9中任一项所述的布线基板；和
电子部件，其搭载于该布线基板。
11.一种电子模块，其特征在于，具有：
权利要求10所述的电子装置；和
模块用基板，其具有连接焊盘，并经由接合材料将所述电子装置连接至所述连接焊盘。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111566806A (zh) * 2018-01-24 2020-08-21 京瓷株式会社 布线基板、电子装置以及电子模块

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007318076A (ja) * 2006-05-25 2007-12-06 Samsung Electro Mech Co Ltd Ｓｉｐモジュール
JP2008085296A (ja) * 2006-09-01 2008-04-10 Nichia Chem Ind Ltd 発光装置
CN101351399A (zh) * 2005-11-16 2009-01-21 京瓷株式会社 电子部件密封用基板、可取多个形态的电子部件密封用基板、及使用了电子部件密封用基板的电子装置及其制法
JP2013106008A (ja) * 2011-11-16 2013-05-30 Sharp Corp 半導体装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3642688B2 (ja) 1998-10-30 2005-04-27 京セラ株式会社 電子部品
JP2001358367A (ja) * 2000-06-13 2001-12-26 Rohm Co Ltd チップ型発光素子
JP5269468B2 (ja) 2008-04-24 2013-08-21 スタンレー電気株式会社 半導体発光装置
JP2011199228A (ja) 2010-03-24 2011-10-06 Daishinku Corp 電子部品用パッケージのベース、電子部品用パッケージ
JP5649878B2 (ja) * 2010-08-30 2015-01-07 シャープ株式会社 半導体装置およびその検査方法、並びに電気機器
CN102456805B (zh) * 2010-10-22 2015-01-07 展晶科技(深圳)有限公司 发光二极管
JP2013070224A (ja) * 2011-09-22 2013-04-18 Seiko Epson Corp 容器、振動デバイス及び電子機器
JP2013106054A (ja) 2011-11-10 2013-05-30 Daishinku Corp 圧電デバイス
JP6046421B2 (ja) * 2012-08-31 2016-12-14 京セラ株式会社 配線基板および電子装置
US9543465B2 (en) * 2014-05-20 2017-01-10 Nichia Corporation Method for manufacturing light emitting device
JP6582382B2 (ja) * 2014-09-26 2019-10-02 日亜化学工業株式会社 発光装置の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101351399A (zh) * 2005-11-16 2009-01-21 京瓷株式会社 电子部件密封用基板、可取多个形态的电子部件密封用基板、及使用了电子部件密封用基板的电子装置及其制法
JP2007318076A (ja) * 2006-05-25 2007-12-06 Samsung Electro Mech Co Ltd Ｓｉｐモジュール
JP2008085296A (ja) * 2006-09-01 2008-04-10 Nichia Chem Ind Ltd 発光装置
JP2013106008A (ja) * 2011-11-16 2013-05-30 Sharp Corp 半導体装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111566806A (zh) * 2018-01-24 2020-08-21 京瓷株式会社 布线基板、电子装置以及电子模块
CN111566806B (zh) * 2018-01-24 2024-04-30 京瓷株式会社 布线基板、电子装置以及电子模块

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