CN107424919A - A kind of low Damage Medium grid and preparation method thereof - Google Patents
A kind of low Damage Medium grid and preparation method thereof Download PDFInfo
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- CN107424919A CN107424919A CN201710335407.3A CN201710335407A CN107424919A CN 107424919 A CN107424919 A CN 107424919A CN 201710335407 A CN201710335407 A CN 201710335407A CN 107424919 A CN107424919 A CN 107424919A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 21
- 230000004888 barrier function Effects 0.000 claims abstract description 102
- 238000002161 passivation Methods 0.000 claims abstract description 77
- 229910052751 metal Inorganic materials 0.000 claims abstract description 58
- 239000002184 metal Substances 0.000 claims abstract description 58
- 238000005530 etching Methods 0.000 claims abstract description 26
- 238000001312 dry etching Methods 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 21
- 229910018503 SF6 Inorganic materials 0.000 claims description 12
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 12
- 229910052593 corundum Inorganic materials 0.000 claims description 12
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 12
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 claims description 7
- 229960000909 sulfur hexafluoride Drugs 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 230000007797 corrosion Effects 0.000 claims description 6
- 238000005260 corrosion Methods 0.000 claims description 6
- 238000005566 electron beam evaporation Methods 0.000 claims description 6
- 238000000231 atomic layer deposition Methods 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims description 4
- 230000002708 enhancing effect Effects 0.000 claims description 3
- 238000004151 rapid thermal annealing Methods 0.000 claims description 3
- 230000008878 coupling Effects 0.000 claims description 2
- 238000010168 coupling process Methods 0.000 claims description 2
- 238000005859 coupling reaction Methods 0.000 claims description 2
- 230000005611 electricity Effects 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000009616 inductively coupled plasma Methods 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 5
- 239000013256 coordination polymer Substances 0.000 description 5
- 230000008020 evaporation Effects 0.000 description 5
- 238000001704 evaporation Methods 0.000 description 5
- 238000007373 indentation Methods 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 4
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 3
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000686 essence Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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Abstract
The invention discloses a kind of low Damage Medium grid and preparation method thereof, it is related to semiconductor high-frequency power device and high tension apparatus technical field；Including being followed successively by substrate, channel layer, barrier layer and passivation layer from top to bottom, source metal and leakage metal are located at device both sides, grid metal is located between source metal and leakage metal, dry etching passivation layer is until barrier layer first, then in etching position deposit grid metal, barrier layer is provided between barrier layer and passivation layer, as etch stop layer；Etching technics damage device surface is avoided, reduces grid leak electricity, improves the yield rate of Dielectric.
Description
Technical field
The present invention relates to semiconductor high-frequency power device and high tension apparatus technical field.
Background technology
Dielectric combination field plate can effectively improve device electric breakdown strength, be widely used in microwave power and high pressure field.
Document：The performance comparision of 0.25 μm of Dielectric and non-Dielectric PHEMT is analyzed, device manufacture and application, and 2009,36（7）：
658-660 compared for Dielectric and non-Dielectric PHEMT device electric breakdown strengths, as shown in Figure 1.As can be seen from Figure 1：Dielectric
PHEMT ON states breakdown voltage is apparently higher than non-medium gate device.
Dielectric group III-nitride HEMT（HEMT）Structure is as shown in Fig. 2 conventional preparation method
For：One layer of passivation layer is deposited first, and then ICP etches grid position passivation layer, finally evaporates grid metal, forms Dielectric.
Typical media grid preparation method etching grid position passivation layer can damage potential barrier layer surface, cause grid leak electricity increase etc. no
Good influence.
The content of the invention
The technical problem to be solved in the present invention is to be directed to above-mentioned the deficiencies in the prior art, there is provided a kind of low Damage Medium grid and
Its preparation method, etching technics damage device surface is avoided, grid leak will not be caused electric, improve the yield rate of Dielectric.
In order to solve the above technical problems, the technical solution used in the present invention is：Including being followed successively by substrate, ditch from top to bottom
Channel layer, barrier layer and passivation layer, source metal and leakage metal are located at device both sides, and grid metal is located between source metal and leakage metal,
Dry etching passivation layer is until barrier layer, then deposits grid metal in etching position first.It is characterized in that：The barrier layer with
Barrier layer is provided between passivation layer）, as etch stop layer.
Preferably, barrier layer is one layer.
Preferably, barrier layer is two layers, respectively the first barrier layer and the second barrier layer.
Preferably, grid metal runs through cut-off passivation layer through cut-off passivation layer, or grid metal（6）With barrier layer or pass through
Wear cut-off passivation layer and the first barrier layer.
Preferably, passivation layer is Si3N4, barrier layer Al2O3。
Preferably, the first barrier layer thickness d1 scopes are：1nm≤d1≤10μm.
Preferably, the second barrier layer thickness d2 scopes are：1nm≤d2≤10μm.
A kind of preparation method of low Damage Medium grid, it is characterised in that：Step includes：
（1）, obtain substrate, channel layer and barrier layer successively with metal organic chemical vapor deposition；
（2）, deposited by electron beam evaporation obtain source metal and leakage metal, and carry out high temperature rapid thermal annealing；
（2）, on barrier layer obtain barrier layer with atomic layer deposition strategy；
（3）, over the barrier layer with gas ions enhancing chemical vapour deposition technique obtain passivation layer；
（4）, with dry etching passivation layer, and the condition of dry etching passivation layer can not etching barrier layer（8）；Or dry etching
After passivation layer, rewetting method corrosion barrier layer；
（5）, deposited by electron beam evaporation obtain grid metal, that is, be made low Damage Medium grid.
Preferably, step（4）The method of middle dry etching passivation layer is：Set using sense coupling
Standby, the plasma dry formed using sulfur hexafluoride gas carves passivation layer Si3N4。
It is using beneficial effect caused by above-mentioned technical proposal：The present invention is simple in construction, passivation layer and barrier layer it
Between increase barrier layer, avoid etching technics damage device surface, grid leak will not be caused electric, reduce grid leak electricity and grid metal/partly lead
Body interface state, improve device electric breakdown strength and reliability；Improve the yield rate of Dielectric.
Brief description of the drawings
Fig. 1 is that Dielectric and non-Dielectric ON state breakdown voltage compare；
Fig. 2 is the structural representation of prior art；
Fig. 3 is the structural representation of one embodiment of the invention；
Fig. 4 is the structural representation of another embodiment of the present invention；
Fig. 5 is the inventive method step（2）- step（3）Schematic diagram；
Fig. 6 is the inventive method step（4）The schematic diagram of Etch Passivation；
Fig. 7 is the inventive method step（4）The schematic diagram of corrosion barrier layer.
In figure：1st, substrate；2nd, channel layer；3rd, barrier layer；4th, source metal；5th, metal is leaked；6th, passivation layer；7th, grid metal；8、
Barrier layer；8.1st, the first barrier layer；8.2nd, the second barrier layer.
Embodiment
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description.
With Dielectric group III-nitride HEMT (（High Electron Mobility Transistor）, high electronics moves
Shifting rate transistor) exemplified by illustrate.
Embodiment 1：
As shown in figure 3, be a kind of one embodiment of low Damage Medium grid of the present invention and preparation method thereof,
Including being followed successively by substrate 1 and channel layer 2 from top to bottom；Both ends on channel layer 2 are respectively equipped with source metal 4 and leakage metal 5；
Barrier layer 3 and passivation layer 6 are sequentially provided with from top to bottom on channel layer 2 and between source metal 4 and leakage metal 5, are set on passivation layer 6
There is grid metal 7, and grid metal 7 is through cut-off passivation layer 6；It is characterized in that：Resistance is provided between the barrier layer 3 and passivation layer 6
Barrier 8.
Barrier layer 8 is provided between barrier layer 3 and passivation layer 6, barrier layer 8 can make will not be to resistance in Etch Passivation 6
Barrier 8 is performed etching, and then device surface is protected, and grid leak will not be caused electric, improve the yield rate of Dielectric.
As illustrated in figs. 5-7, a kind of preparation method of low Damage Medium grid, it is characterised in that：Step includes：
（1）, obtain substrate, channel layer and barrier layer successively with metal organic chemical vapor deposition；
（2）, deposited by electron beam evaporation obtain source metal and leakage metal, and carry out high temperature rapid thermal annealing；
（2）, on barrier layer obtain barrier layer with atomic layer deposition strategy；
（3）, over the barrier layer with gas ions enhancing chemical vapour deposition technique obtain passivation layer；
（4）, with dry etching passivation layer, and the condition of dry etching passivation layer can not etching barrier layer（8）；Or dry etching
After passivation layer, rewetting method corrosion barrier layer；
（5）, deposited by electron beam evaporation obtain grid metal, that is, be made low Damage Medium grid.
Embodiment 2：
As the Dielectric structure in embodiment 1 is identical with preparation method, barrier layer 8 is one layer.The thickness d scope of barrier layer 8 is：
1nm≤d≤10 μm, optimum range are 1nm≤d≤20nm.
Embodiment 3：
As the Dielectric structure in embodiment 1 is identical with preparation method.
As shown in figure 4, barrier layer 8 is two layers, respectively the first barrier layer 8.1 and the second barrier layer 8.2.
The scope of first barrier layer, 8.1 thickness d 1 is：1nm≤d1≤10 μm, optimum range are 1nm≤d1≤20nm.
The scope of second barrier layer, 8.2 thickness d 2 is：1nm≤d2≤10 μm, optimum range are 1nm≤d2≤20nm.
The safer Etch Passivation 6 of two layers of energy of barrier layer 8.
Embodiment 4：
As the Dielectric structure in embodiment 1 is identical with preparation method.
Grid metal 7 is through cut-off passivation layer 6.
Embodiment 5：
As the Dielectric structure in embodiment 1 is identical with preparation method.
Grid metal 7 is through cut-off passivation layer 6 and barrier layer 8.
Embodiment 6：
As the Dielectric structure in embodiment 1 is identical with preparation method.
Through cut-off passivation layer 6 and first barrier layer 8.1.
Whether grid metal 7 does not influence through use of the barrier layer 8 on Dielectric.
Embodiment 7：
As the Dielectric structure in embodiment 1 is identical with preparation method.
Passivation layer 6 is Si3N4, barrier layer 8 is Al2O3。
Step（4）The method of middle dry etching passivation layer 6 is：Using inductively coupled plasma etching equipment I CP, use
Sulfur hexafluoride SF6The Si for the plasma dry etch passivation layer 6 that gas is formed3N4, the condition can not etching barrier layer 8
Al2O3。
Evaporation obtains grid metal 7 on passivation layer 6, and grid metal 7 fills up the indentation, there of the passivation layer 6 of etching.
Embodiment 8：
As the Dielectric structure in embodiment 1 is identical with preparation method.There is two layers of barrier layer 8.
Passivation layer 6 is SiO2, the first barrier layer 8.1 is Al2O3, the second barrier layer 8.2 is hafnium oxide HfO2。
Step（4）The method of middle dry etching passivation layer 6 is：Using inductively coupled plasma etching equipment I CP, use
Sulfur hexafluoride SF6The plasma dry that gas is formed carves the SiO of passivation layer 62, the condition can not etching barrier layer 8 Al2O3。
Barrier layer 8 retains as medium under grid.
Evaporation obtains grid metal 7 on passivation layer 6, and grid metal 7 fills up the indentation, there of the passivation layer 6 of etching.
The scope of first barrier layer, 8.1 thickness d 1 is：1nm≤d1≤10 μm, optimum range are 1nm≤d1≤20nm.
The scope of second barrier layer, 8.2 thickness d 2 is：1nm≤d2≤10 μm, optimum range are 1nm≤d2≤20nm.
Embodiment 9：
As the Dielectric structure in embodiment 1 is identical with preparation method.
Passivation layer 6 is Si3N4, barrier layer 8 is Al2O3。
Step（4）The method of middle dry etching passivation layer 6 is：Using inductively coupled plasma etching equipment I CP, use
Sulfur hexafluoride SF6The plasma dry that gas is formed carves the Si of passivation layer 63N4, the condition can not etching barrier layer 8 Al2O3。
Then wet etching barrier layer Al is utilized2O3。
Evaporation obtains grid metal 7 on passivation layer 6, and grid metal 7 fills up passivation layer 6 and the barrier layer 8 of corrosion of etching
Indentation, there.
Embodiment 10：
As the Dielectric structure in embodiment 1 is identical with preparation method.There is two layers of barrier layer 8.
Passivation layer 6 is SiO2, the first barrier layer 8.1 is Al2O3, the second barrier layer 8.2 is hafnium oxide HfO2。
Step（4）The method of middle dry etching passivation layer 6 is：Using inductively coupled plasma etching equipment I CP, use
Sulfur hexafluoride SF6The plasma dry that gas is formed carves the SiO of passivation layer 62, the condition can not etching barrier layer 8 Al2O3。
The first barrier layer of wet etching 8.1.
Evaporation obtains grid metal 7 on passivation layer 6, and grid metal 7 fills up the barrier layer 8.1 of passivation layer 6 and first of etching
Indentation, there.
Embodiment 11：
As the Dielectric structure in embodiment 1 is identical with preparation method.There is two layers of barrier layer 8.
Passivation layer 6 is SiO2, the first barrier layer 8.1 is Al2O3, the second barrier layer 8.2 is hafnium oxide HfO2。
Step（4）The method of middle dry etching passivation layer 6 is：Using inductively coupled plasma etching equipment I CP, use
Sulfur hexafluoride SF6The plasma dry that gas is formed carves the SiO of passivation layer 62, the condition can not etching barrier layer 8 Al2O3。
Wet etching the first barrier layer 8.1 and the second barrier layer 8.2.
Evaporation obtains grid metal 7 on passivation layer 6, and grid metal 7 fills up the passivation layer 6 of etching, the first barrier layer 8.1 and the
The indentation, there on two barrier layers 8.2.
Passivation layer 6 and barrier layer 8 are the medium beyond present invention description, or passivation layer 6 and the choosing of the growth technique of barrier layer 8
Prepared with the method beyond PECVD, LPCVD either present invention such as ALD description or the dry etching of passivation layer 6 is from the present invention
Condition and equipment beyond description, the either corrosion of barrier layer 8 are stopped from the condition beyond present invention description or wet etching
The corrodible either not corrodible or device architecture of condition of layer 8 is from the device junction beyond the present invention description such as Si bases MOS
Structure, or change the pattern of grid, but these changes all should be fallen within the scope of the hereto appended claims.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
All any modification, equivalent and improvement made within refreshing and principle etc., should be included in the scope of the protection.
Claims (9)
1. a kind of low Damage Medium grid, including substrate is followed successively by from top to bottom（1）, channel layer（2）, barrier layer（3）And passivation layer
（6）, source metal（4）With leakage metal（5）Positioned at device both sides, grid metal（7）Positioned at source metal（4）With leakage metal（5）Between, it is first
First dry etching passivation layer（6）Until barrier layer（3）, then in etching position deposit grid metal（7）；It is characterized in that：It is described
Barrier layer（3）With passivation layer（6）Between be provided with barrier layer（8）, as etch stop layer.
A kind of 2. low Damage Medium grid according to claim 1, it is characterised in that the barrier layer（8）For one layer.
A kind of 3. low Damage Medium grid according to claim 1, it is characterised in that the barrier layer（8）For two layers, respectively
For the first barrier layer（8.1）With the second barrier layer（8.2）.
A kind of 4. low Damage Medium grid according to claim 1 or 3, it is characterised in that the grid metal（7）Through cut-off
Passivation layer（6）, or grid metal（7）Through cut-off passivation layer（6）And barrier layer（8）Or through cut-off passivation layer（6）With first
Barrier layer（8.1）.
A kind of 5. low Damage Medium grid according to claim 1, it is characterised in that the passivation layer（6）For Si3N4, stop
Layer（8）For Al2O3。
A kind of 6. low Damage Medium grid according to claim 3, it is characterised in that first barrier layer（8.1）Thickness d 1
Scope is：1nm≤d1≤10μm.
A kind of 7. low Damage Medium grid according to claim 3, it is characterised in that second barrier layer（8.2）Thickness d 2
Scope is：1nm≤d2≤10μm.
A kind of 8. preparation method of low Damage Medium grid according to any one of claim 1-7, it is characterised in that：Step
Including：
（1）, with metal organic chemical vapor deposition obtain substrate successively（1）, channel layer（2）And barrier layer（3）；
（2）, deposited by electron beam evaporation obtain source metal（4）With leakage metal（5）, and carry out high temperature rapid thermal annealing；
（2）, in barrier layer（3）On with atomic layer deposition strategy obtain barrier layer（8）；
（3）, on barrier layer（8）On with gas ions enhancing chemical vapour deposition technique obtain passivation layer（6）；
（4）, with dry etching passivation layer（6）, and dry etching passivation layer（6）Condition can not etching barrier layer（8）；It is or dry
Method Etch Passivation（6）Afterwards, rewetting method corrosion barrier layer（8）；
（5）, deposited by electron beam evaporation obtain grid metal（7）, that is, low Damage Medium grid are made.
A kind of 9. preparation method of low Damage Medium grid according to claim 8, it is characterised in that the step（4）In do
Method Etch Passivation（6）Method be：Using sense coupling equipment, using sulfur hexafluoride gas formed etc.
Gas ions dry method carves passivation layer（6）Si3N4。
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| CN108376706A (en) * | 2018-01-11 | 2018-08-07 | 北京华碳科技有限责任公司 | A kind of GaN base HEMT device and its manufacturing method |
| WO2022052001A1 (en) * | 2020-09-10 | 2022-03-17 | 苏州晶湛半导体有限公司 | Enhanced semiconductor structure and manufacturing method therefor |
| US20220208992A1 (en) * | 2020-12-29 | 2022-06-30 | Vanguard International Semiconductor Corporation | Semiconductor device and method of forming the same |
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| CN108376706A (en) * | 2018-01-11 | 2018-08-07 | 北京华碳科技有限责任公司 | A kind of GaN base HEMT device and its manufacturing method |
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Application publication date: 20171201 |