CN108376706A - A kind of GaN base HEMT device and its manufacturing method - Google Patents

A kind of GaN base HEMT device and its manufacturing method Download PDF

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Publication number
CN108376706A
CN108376706A CN201810025898.6A CN201810025898A CN108376706A CN 108376706 A CN108376706 A CN 108376706A CN 201810025898 A CN201810025898 A CN 201810025898A CN 108376706 A CN108376706 A CN 108376706A
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layer
layers
dielectric layer
gan
grown
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梁世博
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Beijing China Carbon Science And Technology Co Ltd
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Beijing China Carbon Science And Technology Co Ltd
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Priority to CN201810025898.6A priority Critical patent/CN108376706A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66446Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

A kind of GaN base HEMT device of present invention proposition and its manufacturing method, the device architecture include substrate, GaN layer, AlxGa1‑xN layers, AlN layers, Al2O3Dielectric layer, SiO2Dielectric layer, SiN side walls, barrier metal layer, grid metal electrode and source and drain metal electrodes, wherein use Al2O3/ AlN materials are as etching etch stop layers, using SiN as side wall, coordinate Al2O3Medium at grid metal, realizes the GaN grid slot techniques that etching is combined with corrosion jointly, reduces influence of the etching to grid slot, improves the reliability of device.

Description

A kind of GaN base HEMT device and its manufacturing method
Technical field
The invention belongs to technical field of semiconductors, and in particular to a kind of GaN (gallium nitride) based hemts (high electron mobility crystalline substance Body pipe) device and its manufacturing method.
Background technology
Wide bandgap semiconductor gallium nitride material is big with energy gap with it, critical breakdown electric field is high, electron saturation velocities The features such as high, becomes the ideal material of new generation of semiconductor power device.In recent years, using AlGaN/GaN as the GaN base of representative HEMT device structure generates high two-dimensional electron gas by piezoelectricity and spontaneous polarization, becomes the GaN base HEMT device of mainstream Material structure.
During the realization of GaN device, the method for generally use etching etches away dielectric layer to AlGaN layer, then makes again Grid metal is made, is especially that very, grid are groove etched to become highly important element manufacturing work to manufacture enhanced GaN-HEMT devices Skill.But this concave grid groove technology is relatively high to etching apparatus requirement, and the groove etched meeting of grid is so that etching ion implanting grid slot Under AlGaN layer in, to influence device stability and reliability.It is improved from there through process and structure, can will improve device Part performance and technological level.
Invention content
The purpose of the present invention is be directed to disadvantage present in current GaN base HEMT device preparation process, it is proposed that a kind of GaN Base HEMT device and its manufacturing method, the technique that manufacture GaN base HEMT device is optimized using this manufacturing method, improve device Stability.
In order to achieve the above objectives, the present invention adopts the following technical scheme that:
A kind of GaN base HEMT device, including:
One substrate;
The GaN layer being epitaxially grown on the substrate;
The Al grown into GaN layerxGa1-xN layers;
In AlxGa1-xAn AlN layers grown on N layers;
The Al grown on AlN layers2O3Dielectric layer;
In Al2O3The SiO grown on dielectric layer2Dielectric layer;
In SiO2The grid slot being fabricated on dielectric layer and the two SiN side walls formed in the grid slot;
The barrier metal layer formed between the two SiN side walls in the grid slot;
The grid metal electrode made on the gate metal layer;
In AlxGa1-xTwo source and drain metal electrodes made on N layers.
In the above scheme, the GaN layer is channel layer, thickness 150-2000nm.
In the above scheme, the AlxGa1-xN layers are barrier layer, thickness 6-30nm.
In the above scheme, described AlN layers is barrier layer, act as etch stop layers, thickness 2-10nm.
In the above scheme, the Al2O3Dielectric layer act as etching cutoff layer, thickness 2-10nm.
In the above scheme, the SiO2Dielectric layer act as the molding of grid slot structure, thickness 300-400nm.
In the above scheme, the SiN lateral wall widths are 50-150nm.
In the above scheme, the barrier metal layer thickness is 50-150nm, can be W metals, can also be WSi alloy gold Belong to;The grid metal electrode is Ti/Au double layer of metal, and thickness is respectively 10-30nm/100-500nm.
A kind of manufacturing method of GaN base HEMT device, step include:
(1) prepare a substrate;
(2) epitaxial growth GaN layer over the substrate;
(3) Al is grown in GaN layerxGa1-xN layers;
(4) in AlxGa1-xGrowing AIN layer on N layers;
(5) Al is grown on AlN layers2O3Dielectric layer;
(6) in Al2O3SiO is grown on dielectric layer2Dielectric layer;
(7) in SiO2Grid slot is made on dielectric layer;
(8) SiN matter, and the method for using plasma etching are grown in grid slot, and SiN side walls are formed in grid slot;
(9) method for using chemical attack, erodes Al2O3Dielectric layer and AlN layers;
(10) barrier metal layer is sputtered, and makes grid metal electrode;
(11) extra barrier metal layer is etched away;
(12) in AlxGa1-xSource and drain metal electrodes are made on N layers.
The above-mentioned production method the step of in (9), to ensure the uniformity of corrosion, corrosion is first using the side of number corrosion Method, that is, use ozone treatment 5 to 30 minutes, the method for then using dilute hydrochloric acid corrosion, by Al2O3Dielectric layer and AlN layers of corrosion Fall.
The above-mentioned production method the step of in (10), barrier metal layer material is W metals or WSi alloying metals.
The beneficial effects of the invention are as follows:
Method provided by the invention, by using Al2O3/ AlN materials are as etching etch stop layers, using SiN as side wall, Coordinate Al2O3Medium at grid metal, utilizes Al jointly2O3The wet etching characteristic of/AlN, by GaN at original GaN device grid slot With the etch step of AlGaN material layer, etching SiO is changed into2With SiN dielectric layers and corrosion AlN/Al2O3Layer, realize etching with Corrode the grid slot technique for the GaN base HEMT device being combined, reduces influence of the etching to grid slot.It can will be relied in existing invention Designed GaN material etching technics saves in the enhancement device production process of etching technics, reduces etching ion pair grid The influence of slot reduces the dependence to GaN material etching machine bench, improves the reliability of device.
Description of the drawings
Fig. 1 is GaN base HEMT device structural schematic diagram in embodiment.
Fig. 2 is GaN base HEMT device manufacturing method flow chart in embodiment;
Reference sign:
101:Substrate;102:GaN layer;103:AlxGa1-xN layers;104:AlN layers;105:Al2O3Dielectric layer;106:SiO2It is situated between Matter layer;107:SiN side walls;108:Barrier metal layer;109:Grid metal electrode;110:Source and drain metal electrodes.
Specific implementation mode
Features described above and advantage to enable the present invention are clearer and more comprehensible, special embodiment below, and institute's attached drawing is coordinated to make Detailed description are as follows.
The present embodiment provides a kind of GaN base HEMT devices, and structure is as shown in Figure 1, include:
One substrate 101;
The GaN layer 102 being epitaxially grown on substrate 101;
The Al grown into GaN layer 102xGa1-xN layers 103;
In AlxGa1-xThe AlN layers 104 grown on N layers 103;
The Al grown on AlN layers 1042O3Dielectric layer 105;
In Al2O3The SiO grown on dielectric layer 1052Dielectric layer 106;
In SiO2The grid slot made on dielectric layer 106 and the two SiN side walls 107 formed in the grid slot;
The barrier metal layer 108 formed between the two SiN side walls 107 in the grid slot;
The grid metal electrode 109 being fabricated in barrier metal layer 108;
In AlxGa1-xTwo source and drain metal electrodes made on N layers.
The GaN layer 102 is channel layer, and thickness can be 150-2000nm.
The AlxGa1-xN layers 103 are barrier layer, and thickness can be 6-30nm.
The AlN layers 104 are barrier layer, act as etch stop layers, thickness can be 2-10nm.
The Al2O3Dielectric layer 105 act as etching cutoff layer, and thickness can be 2-10nm.
The SiO2Dielectric layer 106 act as the molding of grid slot structure, and thickness can be 300-400nm.
107 width of SiN side walls can be 50-150nm.
108 thickness of the barrier metal layer can be 50-150nm, can be W metals, can also be WSi alloying metals;Grid gold Category electrode 109 is Ti/Au, and thickness can be respectively 10-30nm/100-500nm.
The present embodiment also provides a kind of manufacturing method of GaN base HEMT device, flow chart as shown in Figure 2, and step includes:
(1) prepare a substrate;
(2) epitaxial growth GaN layer over the substrate;
(3) AlxGa1-xN layers are grown in GaN layer;
(4) in AlxGa1-xGrowing AIN layer on N layers;
(5) Al is grown on AlN layers2O3Medium, row is at Al2O3Dielectric layer;
(6) in Al2O3SiO is grown on dielectric layer2Medium forms SiO2Dielectric layer;
(7) in SiO2Grid slot is made on dielectric layer;
(8) SiNx media, and the method for using plasma etching are grown in grid slot, and SiN side walls are formed in grid slot;
(9) method for using chemical attack, erodes Al2O3Dielectric layer and AlN layers;
(10) barrier metal layer is sputtered, and makes grid metal electrode;
(11) extra barrier metal layer is etched away;
(12) in AlxGa1-xSource and drain metal electrodes are made on N layers.
In step (9), for ensure corrosion uniformity, corrosion first using number corrosion method, with ozone treatment 5 to 30 minutes, the method for then using dilute hydrochloric acid corrosion, by Al2O3Dielectric layer and AlN layers erode.
In step (10), the barrier metal layer material of sputtering is selected as W metals or WSi metals.
By above-described embodiment it is found that this method uses Al2O3/ AlN materials are as etching etch stop layers, using SiN as side Wall coordinates Al2O3Medium at grid metal, realizes the GaN grid slot techniques that etching is combined with corrosion jointly, reduces etching to grid The influence of slot.It can be by GaN material designed in the enhancement device production process for depending on etching technics in existing invention Etching technics saves, and reduces influence of the etching technics to device channel, reduces the defects of raceway groove and barrier layer, improve device Reliability.
The above embodiments are merely illustrative of the technical solutions of the present invention rather than is limited, the ordinary skill of this field Personnel can be modified or replaced equivalently technical scheme of the present invention, without departing from the spirit and scope of the present invention, this The protection domain of invention should be subject to described in claims.

Claims (10)

1. a kind of GaN base HEMT device, including:
One substrate;
The GaN layer being epitaxially grown on the substrate;
The Al grown into GaN layerxGa1-xN layers;
In AlxGa1-xAn AlN layers grown on N layers;
The Al grown on AlN layers2O3Dielectric layer;
In Al2O3The SiO grown on dielectric layer2Dielectric layer;
In SiO2The grid slot being fabricated on dielectric layer and the two SiN side walls formed in the grid slot;
The barrier metal layer formed between the two SiN side walls in the grid slot;
The grid metal electrode made on the gate metal layer;
In AlxGa1-xTwo source and drain metal electrodes made on N layers.
2. a kind of GaN base HEMT device according to claim 1, which is characterized in that the GaN layer is channel layer, thickness For 150-2000nm.
3. a kind of GaN base HEMT device according to claim 1, which is characterized in that the AlxGa1-xN layers are barrier layer, Thickness is 6-30nm.
4. a kind of GaN base HEMT device according to claim 1, which is characterized in that described AlN layers is barrier layer, effect For etch stop layers, thickness 2-10nm.
5. a kind of GaN base HEMT device according to claim 1, which is characterized in that the Al2O3Dielectric layer act as carving Lose cutoff layer, thickness 2-10nm.
6. a kind of GaN base HEMT device according to claim 1, which is characterized in that the SiO2Dielectric layer act as grid slot Shaping structures, thickness 300-400nm.
7. a kind of GaN base HEMT device according to claim 1, which is characterized in that the SiN lateral wall widths are 50- 150nm。
8. a kind of GaN base HEMT device according to claim 1, which is characterized in that the barrier metal layer thickness is 50- 150nm, material are W metals or WSi alloying metals;The grid metal electrode is Ti/Au double layer of metal, and thickness is respectively 10- 30nm/100-500nm。
9. a kind of manufacturing method of GaN base HEMT device, step include:
The epitaxial growth GaN layer on a substrate;
Al is grown in GaN layerxGa1-xN layers;
In AlxGa1-xGrowing AIN layer on N layers;
Al is grown on AlN layers2O3Dielectric layer;
In Al2O3SiO is grown on dielectric layer2Dielectric layer;
In SiO2Grid slot is made on dielectric layer;
SiNx media, and the method for using plasma etching are grown in grid slot, and SiN side walls are formed in grid slot;
Using the method for chemical attack, Al is eroded2O3Dielectric layer and AlN layers;
Barrier metal layer is sputtered, and makes grid metal electrode;
Etch away extra barrier metal layer;
In AlxGa1-xSource and drain metal electrodes are made on N layers.
10. according to the method described in claim 9, it is characterized in that, to ensure that the uniformity of chemical attack, chemical attack are first adopted With the method for number corrosion, with ozone treatment 5 to 30 minutes, the method for then using dilute hydrochloric acid corrosion, by Al2O3Dielectric layer and AlN layers erode.
CN201810025898.6A 2018-01-11 2018-01-11 A kind of GaN base HEMT device and its manufacturing method Pending CN108376706A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110534421A (en) * 2019-08-26 2019-12-03 深圳市汇芯通信技术有限公司 Grid production method and Related product

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130252386A1 (en) * 2005-07-20 2013-09-26 Cree, Inc. Methods of fabricating nitride-based transistors with an etch stop layer
US20150243773A1 (en) * 2014-02-24 2015-08-27 International Business Machines Corporation Iii-v semiconductor device having self-aligned contacts
CN107424919A (en) * 2017-05-12 2017-12-01 中国电子科技集团公司第十三研究所 A kind of low Damage Medium grid and preparation method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130252386A1 (en) * 2005-07-20 2013-09-26 Cree, Inc. Methods of fabricating nitride-based transistors with an etch stop layer
US20150243773A1 (en) * 2014-02-24 2015-08-27 International Business Machines Corporation Iii-v semiconductor device having self-aligned contacts
CN107424919A (en) * 2017-05-12 2017-12-01 中国电子科技集团公司第十三研究所 A kind of low Damage Medium grid and preparation method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110534421A (en) * 2019-08-26 2019-12-03 深圳市汇芯通信技术有限公司 Grid production method and Related product

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