WO2017036025A1

WO2017036025A1 - Iii-group nitride enhanced type hemt and preparation method therefor

Info

Publication number: WO2017036025A1
Application number: PCT/CN2015/099175
Authority: WO
Inventors: 孙钱; 周宇; 李水明; 陈小雪; 戴淑君; 高宏伟; 冯美鑫; 杨辉
Original assignee: 中国科学院苏州纳米技术与纳米仿生研究所
Priority date: 2015-09-01
Filing date: 2015-12-28
Publication date: 2017-03-09

Abstract

Provided are a III-group nitride enhanced type high electron mobility transistor (HEMT) and preparation method therefor. The HEMT comprises a heterojunction mainly composed of a first semiconductor as a channel layer and a second semiconductor as a barrier layer, and an electrode connected to the heterojunction; the HEMT has a first or a second structure based on an etch stop layer; in the first structure, an etch stop layer is formed between the second and first semiconductors or within the second semiconductor at a set depth; in the second structure, a third semiconductor is provided between the gate electrode and the barrier layer, an etch stop layer being formed in the region between the third and the second semiconductor or in the region in the second semiconductor close to the third semiconductor; the etch stop layer comprises a material having a comparatively high etching selection ratio. Providing the etch stop layer in the HEMT, and in combination with the etching technique, can reliably and precisely realize the etching termination of a specific semiconductor structure layer, ensuring that the electrical characteristics of an apparatus are not affected by the etching process, and ensuring the repeatability and reliability of the apparatus electrical chip process.

Description

Group III nitride enhanced HEMT and preparation method thereof

Technical field

The invention relates to a preparation process of a HEMT device, in particular to a preparation method of a III-nitride reinforced HEMT based on an etch stop layer.

Background technique

Compared to conventional silicon-based MOSFETs, AGaN/GaN heterojunction-based High Electron Mobility Transistors (HEMTs) have advantages such as low on-resistance, high breakdown voltage, and high switching frequency. As a core device in various types of power conversion systems, it has important application prospects in terms of energy saving and consumption reduction. However, due to the polarization effect of the III-nitride material system, in general, the AlGaN/GaN heterojunction-based HEMTs are depleted (normally open), and this type of device is required for use in circuit-level systems. The negative polarity gate drive circuit is designed to achieve switching control of the device, which greatly increases the complexity and cost of the circuit. In addition, depletion devices have drawbacks in terms of fail-safe capabilities and, therefore, cannot be truly commercialized.

To solve these problems, the researchers tried a variety of options. For example, one of the solutions is implemented based on a p-gate technology. Referring to FIG. 1a, a p-type layer is epitaxially grown on an AlGaN barrier layer (unintentionally doped n-type) based on a conventional HEMT epitaxial structure. A pn junction is formed over the entire epitaxial wafer, and selective etching is performed to realize p-type gate fabrication, thereby depleting the two-dimensional electron gas under the p-type gate. In the etching process of the selection, it is necessary to etch a large area of the non-gate. However, if the etching uniformity cannot be effectively controlled, the p-type layer in the local region may be over-etched and partially In the region, under-etching may occur, and both of them may eventually cause a decrease in the two-dimensional electron gas concentration in the region between the gate source and the gate drain of the device, and generate a large number of surface defect states, thereby seriously affecting the device at work. On-resistance and dynamic characteristics. Therefore, the p-gate technology based on the selective etch requires precise controllable etch depth of the p-type layer in the non-gate region, which greatly increases the difficulty of the p-gate technology, making the repeatability of the technology (slices and slices) Between), uniformity (between different areas within the sheet), and stability (between different round processes) are difficult to guarantee. For another example, another relatively simple solution is implemented based on a trench gate technology, in which a portion of the AlGaN barrier layer under the gate is etched away in the device process based on the conventional HEMT epitaxial structure. When thinning to a certain extent, the gate area is two-dimensional electronic gas It is exhausted; the two-dimensional electron gas concentration in the region between the gate source and the gate drain is maintained at the original level, as shown in Fig. 1b. In the trench gate etching process, due to the small etching depth, accurate control of the etching depth is difficult, and the process repeatability is poor. The key parameter in the enhanced HEMT, the threshold voltage, is closely related to the thickness of the unetched barrier layer, so the direct consequence is that the threshold voltage is less controllable. In addition, during the etching process, the surface of the barrier layer of the trench gate region is inevitably damaged, and a large number of surface states are generated, which causes an increase in gate leakage, thereby causing a decrease in gate regulation capability. Therefore, trench gate technology to prepare enhanced HEMT requires precise controllable etching depth of the barrier layer, which greatly increases the difficulty of trench gate technology, making the technology repeatable (between slices and slices) and uniformity ( Stability between different areas of the film (between different round processes) is difficult to guarantee. In response to these problems, the researchers proposed a digital oxidation/wet etching technique, which is to etch the barrier layer and the acid solution to oxidize the layer and achieve high-precision etching of the barrier layer. The etching depth of each cycle is almost a single atomic layer, which requires many cycles to complete the entire etching process, so the efficiency is very low. Another simple solution is to control the trench gate etch depth by slow etching, such as reducing RF Power, reducing Source Power, etc., combined with etch time control, but at the expense of long etch time. In addition, in order to weaken the influence of the poor controllability of the trench gate etch depth, some special improvements are usually made on the structure of the device. One of the important types of trench gate enhancement devices is the MIS channel HEMT. The basic feature is to etch the trench gate to the GaN channel layer and form the enhanced MIS field effect transistor with a metal-dielectric-semiconductor structure. The metal extends over the dielectric layer above the barrier/channel layer heterojunction outside the trench gate to form a depletion HEMT integrated with the enhanced MIS field effect transistor to increase the device output current. However, this technique also inevitably has the difficulty of precisely etching the barrier layer, and the etching-induced surface damage of the channel layer deteriorates the channel electron mobility, thereby affecting the on-state resistance characteristics of the device.

Summary of the invention

The main object of the present invention is to provide a Group III nitride-enhanced HEMT and a preparation method thereof to overcome the deficiencies of the prior art.

In order to achieve the foregoing object, the technical solution adopted by the present invention includes:

Embodiments of the present invention provide a Group III nitride-enhanced HEMT including a heterojunction mainly composed of a first semiconductor as a channel layer and a second semiconductor as a barrier layer (the second semiconductor has a width wider than a band gap of the first semiconductor) and a source, a gate, and a drain connected to the heterojunction;

Further, the HEMT has a first structure or a second structure based on an etch stop layer;

In the first structure, an etch stop layer is distributed between the second semiconductor and the first semiconductor, and a constituent material of the etch stop layer is compared with the second semiconductor for the selected etchant Composition materials have higher etch resistance Alternatively, or the second semiconductor is formed with an etch stop layer at a set depth, and for the selected etchant, the constituent material of the etch stop layer is compared with the composition of the remaining portion of the second semiconductor The material has higher etch resistance.

In the second structure, a third semiconductor is further disposed between the gate and the barrier layer, and the second semiconductor and the third semiconductor have different conductivity types; wherein the third semiconductor and the second semiconductor An etch stop layer is also disposed therebetween, or an etch stop layer is formed in a region adjacent to the third semiconductor in the second semiconductor, and a constituent material of the etch stop layer is selected for the selected etchant The constituent material of the third semiconductor has higher etching resistance.

An embodiment of the present invention further provides a method for preparing the group III nitride-enhanced HEMT, comprising: sequentially growing a first semiconductor as a channel layer and a second semiconductor as a barrier layer on a substrate, thereby Forming a heterojunction mainly composed of the first semiconductor and the second semiconductor;

Further, the preparation method further includes:

Forming a first structure based on an etch stop layer, comprising: forming an etch stop layer at a set depth within the second semiconductor, wherein a constituent material of the etch stop layer is selected for a selected etchant Forming material with the rest of the second semiconductor has higher etching resistance, or forming an etch stop layer between the first semiconductor and the second semiconductor, wherein the etching is terminated for the selected etching material The constituent material of the layer has higher etching resistance than the constituent material of the second semiconductor;

Alternatively, preparing a second structure based on an etch stop layer includes: forming a third semiconductor having a different conductivity type from the second semiconductor on the second semiconductor, and adjacent to the third semiconductor in the second semiconductor Forming an etch stop layer in the region, or forming an etch stop layer between the second semiconductor and the third semiconductor, wherein the constituent material of the etch stop layer is compared to the selected etchant The constituent material of the third semiconductor has higher etching resistance.

Compared with the prior art, the advantages of the present invention are at least: by epitaxially growing an etch stop layer during the preparation process of the HEMT device, that is, by epitaxially growing a higher etching selectivity material, and combining the etching technology, Reliably realize the etch termination of a specific semiconductor structure layer (such as a p-type layer, a barrier layer, etc.), thereby accurately controlling the etching depth of the specific semiconductor structure, and maximally ensuring electrical characteristics of the device including threshold voltage, output current, and the like. It is not affected by the etching process, and ensures the repeatability, uniformity and stability of the device's electrical chip process, and is suitable for mass production. Particularly preferably, the semiconductor surface can naturally form an in-situ passivation layer under the action of an etching process, and the passivation layer can play a key protective role. Particularly preferably, under the action of the etching process, the surface of the semiconductor, especially the etch stop layer, can naturally form a passivation layer, thereby avoiding a series of device reliability problems caused by the gate dielectric layer, the passivation layer deposition process, and the like. .

DRAWINGS

FIG. 1a is a schematic diagram of a prior art fabrication of a p-type gate enhanced HEMT based on a selective etch technique.

FIG. 1b is a schematic diagram of preparing an enhanced HEMT based on a trench gate technology in the prior art.

2 is a schematic diagram showing an epitaxial structure of a HEMT in Embodiment 1 of the present invention.

3 is a schematic view showing the formation of an etch stop layer on the epitaxial structure shown in FIG. 2.

4 is a schematic view showing the formation of a p-GaN layer on the etch stop layer shown in FIG.

Figure 5 is a schematic illustration of active region isolation of the device of Figure 4.

Figure 6 is a schematic illustration of the formation of a gate electrode metal layer on the device of Figure 5.

7 is a schematic view of the device of FIG. 6 after etching through a gate electrode metal layer and a p-GaN layer.

Figure 8 is a schematic illustration of the formation of a passivation layer on the device of Figure 7.

Figure 9 is a schematic illustration of the passivation layer of the device of Figure 8 after fenestration.

Figure 10 is a schematic illustration of the formation of source and drain electrodes and field plates on the device of Figure 9.

11 is a schematic structural diagram of a HEMT obtained in Embodiment 1.

Figure 12a is a schematic diagram showing the epitaxial structure of a HEMT in Embodiment 2 of the present invention.

Fig. 12b is a schematic view showing the change of the Al composition in the barrier layer in the epitaxial structure shown in Fig. 12a.

Figure 13 is a schematic illustration of the formation of a p-GaN layer on the device of Figure 12a.

FIG. 14 is a schematic structural diagram of a HEMT obtained in Embodiment 2.

Figure 15a is a schematic diagram showing the epitaxial structure of a HEMT in Embodiment 3 of the present invention.

Fig. 15b is a schematic view showing the change of the Al composition in the barrier layer in the epitaxial structure shown in Fig. 15a.

Figure 16 is a schematic illustration of the formation of a p-GaN layer on the device of Figure 15a.

17 is a schematic structural view of a HEMT obtained in Embodiment 3.

FIG. 18a is a schematic diagram showing an epitaxial structure of a HEMT according to Embodiment 4 of the present invention.

Fig. 18b is a schematic view showing the change of the Al composition in the barrier layer in the epitaxial structure shown in Fig. 18a.

Figure 19 is a schematic illustration of the formation of a p-GaN layer on the device of Figure 18a.

20 is a schematic structural diagram of a HEMT obtained in Embodiment 4.

21a is a schematic diagram showing the epitaxial structure of a HEMT in Embodiment 5 of the present invention.

Figure 21b is a schematic illustration of the change in Al composition in the barrier layer of the epitaxial structure of Figure 2a.

Fig. 22 is a schematic view showing the formation of a groove-type source and a drain electrode on the epitaxial structure shown in Figs. 21a to 21b.

Figure 23 is a schematic illustration of oxide layer etching of the device of Figure 22.

Figure 24 is a schematic illustration of the formation of source and drain ohmic contacts on the device of Figure 23.

Figure 25 is a schematic illustration of active region isolation of the device of Figure 24.

Figure 26 is a schematic illustration of the formation of a passivation layer on the device of Figure 25.

Figure 27 is a schematic illustration of the formation of a gate opening on the device of Figure 26.

Figure 28 is a schematic illustration of etching a trench gate on the device of Figure 27.

Figure 29 is a schematic illustration of the formation of a gate dielectric layer on the device of Figure 28.

Figure 30 is a schematic illustration of the formation of a gate electrode metal layer on the device of Figure 29.

Figure 31 is a schematic illustration of source and drain ohmic contact opening on the device of Figure 30.

Figure 32 is a schematic view showing the formation of a lead electrode on the device shown in Figure 31.

Figure 33a is a schematic diagram showing the epitaxial structure of a HEMT in Embodiment 6 of the present invention.

Figure 33b is a diagram showing the change of the Al composition in the barrier layer in the epitaxial structure shown in Figure 33a.

Figure 34 is a block diagram showing the structure of a HEMT device in Embodiment 6 of the present invention.

Figure 35a is a schematic diagram showing the epitaxial structure of a HEMT in Embodiment 7 of the present invention.

Figure 35b is a diagram showing the change of the Al composition in the barrier layer in the epitaxial structure shown in Figure 35a.

Figure 36 is a block diagram showing the structure of a HEMT device in Embodiment 7 of the present invention.

37a is a schematic diagram showing the epitaxial structure of a HEMT in Embodiment 8 of the present invention.

Fig. 37b is a schematic view showing the change of the Al composition in the barrier layer in the epitaxial structure shown in Fig. 37a.

Figure 38 is a block diagram showing the structure of a HEMT device in Embodiment 8 of the present invention.

detailed description

A first embodiment of the present invention provides a p-type layer-based group III nitride-enhanced HEMT including a heterojunction mainly composed of a first semiconductor as a channel layer and a second semiconductor as a barrier layer, and A source electrode, a gate electrode, and a drain electrode connected to the heterojunction, and a third semiconductor capable of forming a heterojunction with the second semiconductor is further disposed between the gate electrode and the barrier layer. In a preferred embodiment, an etch stop layer is further disposed between the third semiconductor and the second semiconductor, and a high etching between the constituent material of the etch stop layer and the third semiconductor Choose ratio.

That is, for the selected etchant, the constituent material of the etch stop layer has higher etching resistance than the constituent material of the third semiconductor.

A constituent material of a region adjacent to the third semiconductor in the second semiconductor has a higher etching selectivity ratio with a constituent material of the third semiconductor.

That is, for the selected etchant, the constituent material of the region adjacent to the third semiconductor in the second semiconductor has higher etching resistance than the constituent material of the third semiconductor.

In some embodiments, the third semiconductor is distributed under the gate electrode and is located within an orthographic projection of the gate electrode on the barrier layer.

In some preferred embodiments, the etch stop layer or the second semiconductor is further provided with a passivation layer, and the passivation layer includes at least a partial region of the surface layer of the etch stop layer or a second semiconductor surface layer The local region is a natural passivation layer formed in situ by reacting with the etching material, for example, a natural passivation layer of alumina material.

Wherein, the constituent material of the barrier layer may be at least limited to, but not limited to, Al _x In _y Ga _z N (0<x≤1, 0≤y≤1, x+y+z=1).

In some embodiments, the barrier layer may be adjacent to a portion of the third semiconductor as an etch stop layer, and the Al composition may also be epitaxially grown under the premise that the two-dimensional electron gas has excellent electrical properties. Various functions in the z direction.

In some preferred embodiments, the constituent material of the barrier layer is selected from the group consisting of Al _x In _y Ga _z N (0<x≤1, 0≤y≤1, (x+y+z)=1), Wherein along the direction from the first semiconductor to the third semiconductor, x generally increases (some of which may remain unchanged or slightly decrease). The increase can be linear growth, step growth, super crystal format growth, multi-layer superlattice structural growth, and the like.

Wherein, the constituent material of the channel layer can be at least selected from, but not limited to, GaN, InGaN, AlGaN, AlInN or AlInGaN.

The constituent material of the third semiconductor may be at least selected from the group consisting of, but not limited to, p-GaN, p-AlGaN, p-AlInN, p-InGaN, and p-AlInGaN.

Wherein, the constituent material of the etch stop layer may be at least selected from the group consisting of AlN, SiN _x (0<x≤3), Al _x Ga _1-x N (0<x<1), etc., but may also be selected from other A material having a higher etching selectivity ratio between the third semiconductors (eg, p-type layers).

In some embodiments, the heterojunction further includes an intervening layer distributed between the first semiconductor and the second semiconductor.

Wherein, the constituent material of the interposer layer is at least optional but not limited to AlN, AlInN or AlInGaN.

In some embodiments, the passivation layer further includes a SiN _x layer (0<x≤3) formed on the natural passivation layer.

The selected etching material may be various materials commonly used in dry etching or wet etching, preferably by a dry etching process, such as IBE (Ion Beam Etch), ICP. (Inductive Coupled Plasma).

More preferably, the selected etchant may be selected from an etch gas containing oxygen.

In some embodiments, the HEMT further includes a substrate, and a buffer layer is further disposed between the substrate and the heterojunction.

The substrate may be a substrate such as sapphire, silicon carbide, gallium nitride, aluminum nitride, or the like, but is not limited thereto.

The material of the buffer layer may be used in the industry, for example, GaN, AlGaN, etc.

The source electrode and the drain electrode form an ohmic contact with an epitaxial structure of the HEMT.

In addition, the HEMT also has a field plate structure.

The materials of the source, the drain, the gate electrode and the like may be used in the industry, and may be, for example, W, Ni, Au or the like.

A first embodiment of the present invention also provides a method of preparing the p-type layer-based Group III nitride-enhanced HEMT, comprising:

Forming, on the substrate, a first semiconductor layer as a channel layer, a second semiconductor as a barrier layer, and a third semiconductor capable of forming a heterojunction with the second semiconductor, wherein the selective etching is performed a substance, a constituent material of a region adjacent to the third semiconductor in the second semiconductor has higher etching resistance than a constituent material of the third semiconductor,

Alternatively, a first semiconductor layer as a channel layer, a second semiconductor as a barrier layer, an etch stop layer, and a third semiconductor capable of forming a heterojunction with the second semiconductor are sequentially grown on the substrate, wherein The constituent material of the etch stop layer has higher etching resistance than the constituent material of the third semiconductor with respect to the selected etchant;

Forming a gate electrode material layer on the third semiconductor, further providing a patterned mask on the gate electrode material layer, etching the gate electrode material layer and the third semiconductor, thereby forming a gate electrode, and making the Two semiconductor or etch stop layers are exposed;

And, a source electrode and a drain electrode are provided on the device formed by the foregoing steps, thereby obtaining the HEMT.

In some embodiments, the preparation method may further include: providing a patterned mask on the gate electrode material layer, and etching the third semiconductor with the selected etching material until the etching material and the etching material The partial region of the second semiconductor skin layer or the local region of the surface layer of the etch stop layer reacts to form the natural passivation layer in situ and then stops etching.

The constituent materials of the barrier layer, the channel layer, and the etch stop layer may be as described above.

Preferably, the preparation method may further include: after forming the gate electrode, providing a passivation layer on the surface of the obtained device, and processing a window region on the passivation layer, and then setting a source in the window region. The electrode and the drain electrode, thereby obtaining the HEMT.

Preferably, the preparation method may further include: after growing the third semiconductor, performing isolation processing on the active region of the obtained device, and then providing a gate electrode material layer on the third semiconductor.

In some embodiments, the preparation method may further include: growing an intervening layer between the first semiconductor and the second semiconductor.

In some embodiments, the preparation method may further include: growing a buffer layer between the substrate and the heterojunction.

The following is a detailed description of some of the exemplary embodiments of the first embodiment of the present invention.

Embodiment 1: The structure of the HEMT is as shown in FIG. 11, which includes a buffer layer formed on a substrate, an Al _x Ga _1-x N/GaN heterojunction (x = 0.1 to 0.35), and an AlN etch stop layer. a passivation layer, a source electrode (referred to as a source), a drain electrode (abbreviated as a drain), a gate electrode (referred to as a gate), and the like. The substrate may be a substrate such as sapphire, silicon carbide, gallium nitride, or aluminum nitride, but is not limited thereto. The material of the buffer layer may be used in the industry, and may be, for example, GaN, AlGaN, or the like.

A method for preparing the HEMT provided by this embodiment may include the following steps:

S1: MOCVD epitaxial growth of HEMT based on AlGaN/GaN heterojunction. The AlGaN barrier layer has an Al composition x of 10% to 35%, a thickness of 5 to 25 nm, an AlN insertion layer of about 1 nm, and a GaN channel layer of 50 to 200 nm. The HEMT epitaxial structure is as shown in FIG.

S2: MOCVD is grown to form an AlN etch stop layer having a thickness of 0.5 to 5 nm, as shown in FIG.

S3: MOCVD epitaxially grown p-GaN, having a thickness of 5 to 300 nm, and a magnesium doping concentration ranging from 10 ¹⁸ to 10 ²¹ /cm ³ , as shown in FIG. 4 . However, it should be noted that the magnesium doping concentration is not limited to a single doping concentration, and may be a function of the z-direction of epitaxial growth.

S4: Active area isolation. Ion implantation is carried out by N ion implantation technique, and the ion implantation energy is 150-400 KeV ion implantation, and the implantation ion dose is 10 ¹² to 10 ¹⁴ /cm ² , and the implantation depth is about 50 to 250 nm beyond the buffer layer, as shown in FIG. 5 .

S5: Gate metal deposition. The tungsten (W) metal is deposited by magnetron sputtering to a thickness of 50 to 200 nm, as shown in FIG.

S6: gate metal and p-GaN etching. Plasma etching is performed on the non-gate region by using the photoresist AZ5214 as a mask: first, the tungsten metal is etched by IBE (Ion Beam Etch); secondly, ICP (Inductive Coupled Plasma, ICP) is used. Inductively coupled plasma) etching etches p-GaN. In the etching gas Cl ₂ /BCl ₃ /N ₂ /O ₂ , the oxygen content volume ratio accounts for 2% to 70%, and the etching rate is controlled at 5~. 40 nm/min. The etching depth of the p-GaN is controlled by the AlN etch stop layer, and the range in which the AlN etch stop layer can be etched is controlled to be 0 to 5 nm, and the oxide layer Al ₂ O _{3 is formed to have a} thickness of about 0.5 to 5 nm. As shown in Figure 7.

S7: Passivation layer deposition. A SiN _x (0 < _x ≤ 3) passivation layer is deposited by a dielectric layer deposition technique such as PECVD, ICP-CVD, or LPCVD, and has a thickness of 50 to 500 nm as shown in FIG.

S8: Passivation layer etching window. The SiN _x is etched by RIE (Reactive Ion Etch) to realize ohmic contact opening, as shown in FIG.

S9: source and drain ohmic contact, source field plate preparation. Preparation conditions: metal Ti / Al / Ni / Au, thickness of 20nm / 130nm / 50nm / 150nm, annealing conditions of 890 ° C, 30s, nitrogen atmosphere, as shown in Figure 10.

S10: lead electrode. Preparation conditions: Metal Ni/Au, thickness 50 nm / 400 nm, as shown in FIG.

Embodiment 2: The structure of the HEMT is as shown in FIG. 14, which includes a buffer layer formed on a substrate, an Al _x Ga _1-x N/GaN heterojunction (x = 0.1 to 0.4), a passivation layer, and a source. Electrode (referred to as source), drain electrode (referred to as drain), gate electrode (referred to as gate), and the like. In the barrier layer, the Al composition has a step change barrier layer in the growth z direction, and the high Al composition AlGaN serves as an etch stop layer (Al _0.4 Ga _0.6 N).

S1: MOCVD epitaxial growth of HEMT based on AlGaN/GaN heterojunction. The Al composition barrier layer Al composition x is 10%, 20%, 30%, 40% in the z direction of the epitaxial growth, the barrier layer thickness is 5 to 25 nm, the AlN insertion layer is about 1 nm, and the GaN channel layer is 50 to 200 nm, the HEMT epitaxial structure is shown in Figures 12a - 12b.

S2: MOCVD epitaxially grown p-GaN, having a thickness of 5 to 300 nm, and a magnesium doping concentration ranging from 10 ¹⁸ to 10 ²¹ /cm ³ , as shown in FIG.

S3 to S9: S4 to S10 in the same manner as in the first embodiment. In "gate metal and p-GaN etching", the high Al composition AlGaN in the barrier layer, that is, Al _0.4 Ga _0.6 N is an etch stop layer, and a higher etching selectivity ratio between it and p-GaN is utilized. Control the p-GaN etch depth. At the same time, by an oxygen-containing etching gas _{_{_{Cl 2 / BCl 3 / N 2}}} / O 2 ICP etching, an oxygen content of 2% by volume to 70%, the resulting oxide layer thickness of the Al ₂ O ₃ Control 0.5 ~ 5nm. The device after completing the entire chip process is shown in Figure 14.

Embodiment 3: Structure of HEMT As shown in FIG. 17, it includes a buffer layer formed on a substrate, an Al _x Ga _1-x N/GaN heterojunction (x = 0.1 to 0.4), a passivation layer, and a source electrode. (referred to as source), drain electrode (referred to as drain), gate electrode (referred to as gate) and so on. In the barrier layer, the Al composition changes linearly and stepwise with the growth z direction, and the high Al composition AlGaN acts as an etch stop layer (Al _0.4 Ga _0.6 N).

S1: MOCVD epitaxial growth of HEMT based on AlGaN/GaN heterojunction. Among them, the Al composition barrier layer Al composition x first linearly changes along the epitaxial growth z direction, and the Al composition varies from 10% to 30%; then, the Al composition x remains at 40%. The thickness of the barrier layer is 5 to 25 nm; the AlN insertion layer is about 1 nm; the GaN channel layer is 50 to 200 nm, and the HEMT epitaxial structure is as shown in FIGS. 15a to 15b.

S2: MOCVD epitaxially grown p-GaN with a thickness of 5 to 300 nm and a magnesium doping concentration range of 10 ¹⁸ to 10 ²¹ /cm ³ as shown in FIG.

S3: S4 to S10 in the same manner as in the first embodiment. In "gate metal and p-GaN etching", the high Al composition AlGaN in the barrier layer, that is, Al _0.4 Ga _0.6 N is an etch stop layer, and a higher etching selectivity ratio between it and p-GaN is utilized. Control the p-GaN etch depth. At the same time, the ICP etching is performed by the oxygen-containing etching gas Cl ₂ /BCl ₃ /N ₂ /O ₂ , and the oxygen content volume ratio accounts for 2% to 70%, and the thickness of the oxide layer Al ₂ O ₃ is controlled to be 0.5 to 5 nm. The device after completing the entire chip process is shown in Figure 17.

Embodiment 4: Structure of HEMT As shown in FIG. 20, it includes a buffer layer formed on a substrate, an Al _x Ga _1-x N/GaN heterojunction (x = 0.1 to 0.5), a passivation layer, and a source electrode. (referred to as source), drain electrode (referred to as drain), gate electrode (referred to as gate) and so on. Wherein, the barrier layer is a multilayer heterojunction structure, and the high Al composition AlGaN is used as an etch stop layer (Al _0.4 Ga _0.6 N/Al _0.5 Ga _0.5 N)

S1: MOCVD epitaxial growth of HEMT based on AlGaN/GaN heterojunction. Among them, the Al composition barrier layer Al composition x changes along the epitaxial growth z direction as shown in FIGS. 18a to 18b. The barrier layer has a thickness of 5 to 25 nm; the AlN insertion layer has a thickness of about 1 nm; and the GaN channel layer has a thickness of 50 to 200 nm.

S3: S4 to S10 in the same manner as in the first embodiment. In "gate metal and p-GaN etching", the high Al composition AlGaN in the barrier layer, that is, Al _0.4 Ga _0.6 N/Al _0.5 Ga _0.5 N is an etch stop layer, which is compared with p-GaN. A high etch selectivity ratio controls the p-GaN etch depth. At the same time, the ICP etching is performed by the oxygen-containing etching gas Cl ₂ /BCl ₃ /N ₂ /O ₂ , and the oxygen content volume ratio accounts for 2% to 70%, and the thickness of the oxide layer Al ₂ O ₃ is controlled to be 0.5 to 5 nm. The device after the completion of the entire chip process is shown in FIG.

A first embodiment of the present invention is directed to an existing p-type gate technology by growing a material having a higher etching selectivity ratio with a constituent material of the third semiconductor before growing a third semiconductor (e.g., a p-type layer), Combined with etching technology, effective, Reliable realization of the third semiconductor etch stop, thereby accurately controlling the third semiconductor etch depth, to ensure that the two-dimensional electron gas in the non-gate region is not affected by the etching process, and ensuring the electrical characteristics of the device including the output current and dynamic characteristics. Etc., greatly reducing the implementation difficulty of the p-gate technology, ensuring the repeatability, uniformity and stability of the device electrical chip process, and is suitable for mass production. Particularly preferably, the surface of the semiconductor can naturally form an in-situ passivation layer under the action of the etching process, and the passivation layer can play a key protective role, thereby effectively reducing the surface caused by the subsequent passivation layer deposition process. Problems such as damage and the resulting deterioration in the electrical properties of the material (for example, large square resistance and significant current collapse effect).

A second embodiment of the present invention provides a Group III nitride enhanced HEMT based on trench gate technology.

In some embodiments, the trench gate technology-based III-nitride-enhanced HEMT includes a heterojunction mainly composed of a first semiconductor as a channel layer and a second semiconductor as a barrier layer, and the different a source electrode, a gate electrode, and a drain electrode (which may also be referred to simply as a source, a gate, and a drain) connected to the junction, wherein the barrier layer is distributed with a groove-like structure mated with the gate electrode, and at least the gate electrode The lower portion is disposed in the groove structure.

In some embodiments, an etch stop layer is further disposed between the second semiconductor and the first semiconductor, and a constituent material of the etch stop layer is compared to the second material with respect to the selected etchant. The constituent materials of the semiconductor have higher etching resistance.

That is, for the selected etchant, the constituent material of the etch stop layer has higher etching resistance than the constituent material of the second semiconductor.

In some embodiments, the second semiconductor is directly stacked on the etch stop layer.

In some embodiments, the etch stop layer may also be disposed at a set depth within the second semiconductor, and the constituent material of the etch stop layer is compared to the second with respect to the selected etchant. The constituent materials of the rest of the semiconductor have higher etching resistance.

In some embodiments, the etch stop layer may also be distributed in a region of the second semiconductor that is relatively close to the first semiconductor, particularly in a region of the second semiconductor that is closest to the first semiconductor.

In other words, in some embodiments, a portion of the second semiconductor, particularly a region adjacent to the first semiconductor, directly serves as an etch stop layer, while ensuring excellent electrical characteristics of the two-dimensional electron gas. The Al component contained therein may also be various functions of epitaxial growth in the z direction.

That is, for the selected etchant, the constituent material of the region adjacent to the first semiconductor in the second semiconductor has higher etching resistance than the constituent material of the remaining portion of the second semiconductor.

In some embodiments, a groove structure mated with the source electrode and/or the drain electrode may also be disposed in the second semiconductor.

In some preferred embodiments, a local region of the surface layer of the etch stop layer and a selected etchant are further distributed between the gate electrode and/or the source electrode and/or the drain electrode and the etch stop layer. A natural passivation layer formed in situ by reaction, for example, a natural passivation layer of alumina.

In some embodiments, the selected etchant may be at least preferably selected from an etch gas containing oxygen, but is not limited thereto.

Wherein, the constituent material of the barrier layer may be at least selected from the group consisting of Al _x In _y Ga _z N, 0 < x ≤ 1, 0 ≤ y ≤ 1, (x + y + z) = 1, but is not limited thereto.

The constituent material of the channel layer may include any one of GaN, InGaN, AlGaN, AlInN, and AlInGaN, or a combination of two or more thereof, but is not limited thereto.

Wherein, the constituent material of the etch stop layer includes any one of AlN, SiN _x (0<x≤3), Al _x Ga _1-x N (0<x<1), or a combination of two or more. But it is not limited to this.

In some preferred embodiments, the constituent material of the barrier layer is selected from the group consisting of Al _x In _y Ga _z N, 0 < x ≤ 1, 0 ≤ y ≤ 1, (x + y + z) = 1, wherein Along the direction away from the first semiconductor, x generally decreases (some of which may remain unchanged or increase slightly). The reduction may be linear reduction, nonlinear reduction, step reduction, super crystal format reduction, multilayer superlattice structural reduction, and the like.

The constituent material of the interposer may include any one of AlN, AlInN, and AlInGaN, or a combination of two or more thereof, but is not limited thereto.

In some embodiments, an ohmic contact is formed between the source electrode, the gate electrode, and the heterojunction, and a gate dielectric layer and/or a passivation layer are further disposed between the gate electrode and the heterojunction.

The constituent material of the gate dielectric layer and the passivation layer may be selected from the group consisting of aluminum oxide (Al ₂ O ₃ ), SiN _x (0<x≤3), and the like.

The material of the source electrode, the drain electrode, the gate electrode, and the like may be used in the industry, and may be, for example, W, Ni, Au, or the like.

A second embodiment of the present invention also provides a method of preparing the Group III nitride-enhanced HEMT based on a trench gate technique.

In some embodiments, the method of preparation comprises:

Forming a first semiconductor layer as a channel layer and a second semiconductor as a barrier layer on the substrate, and providing an etch stop layer at a set depth in the second semiconductor, wherein The etchant is selected, and the constituent material of the etch stop layer has higher etching resistance than the constituent materials of the rest of the second semiconductor.

Alternatively, a first semiconductor layer as a channel layer, an etch stop layer, and a second semiconductor as a barrier layer are sequentially grown on the substrate, wherein the etching is terminated with respect to the selected etchant The constituent material of the layer has higher etching resistance than the constituent material of the second semiconductor;

Forming a patterned mask on the second semiconductor, and etching the second semiconductor to form a groove-like structure mated with the gate electrode, and exposing the etch stop layer;

And, a gate electrode is provided on the device formed by the foregoing steps.

In some embodiments, the preparation method may further include: providing a patterned mask on the second semiconductor, and etching the second semiconductor to form a trench structure matching the gate electrode, and engraving The etching is stopped when the etch stop layer is exposed, and the etching is automatically stopped after the etching material reacts with a local region of the surface layer of the etch stop layer to form a natural passivation layer in situ.

In some embodiments, the preparation method may further include: providing a patterned mask on the second semiconductor, and etching the second semiconductor to form a groove-like structure in ohmic contact with the source and drain electrodes . Preferably, when etching forms a groove-like structure in ohmic contact with the source and drain electrodes, the etching operation is terminated when the etch stop layer is exposed, particularly in a partial region of the surface layer of the etchant and the etch stop layer. The reaction stops automatically after forming a natural passivation layer in situ.

Among them, by etching the termination layer, the groove type ohmic contact can be accurately prepared, and the low temperature process can be realized without performing a high temperature annealing process of 800 ° C or higher like the conventional ohmic contact preparation technique, so that the high temperature process is not caused. Serious effects on the surface (such as the formation of N vacancies, the formation of an oxide layer, causing cracks in the SiN _x thick layer in the Gate-first process during annealing), thereby maximally avoiding the effects of high temperature processes on the device surface and Related device reliability issues and contribute to the Gate-first process.

In some specific embodiments, the preparation method may further include: sequentially forming a first semiconductor layer and a second semiconductor on the substrate, and then forming source and drain electrodes on the formed device, and performing The source region is isolated, and then a passivation layer covering the source and drain electrodes and the second semiconductor is grown, and a gate window region is formed on the passivation layer, and then a patterned mask covering the passivation layer is disposed. And etching the second semiconductor from the gate window region exposed in the patterned mask to form the trench structure, and then providing a gate dielectric layer on at least the inner wall of the trench structure, and then forming a gate electrode.

In some more specific embodiments, the preparation method may further include: providing a patterned mask on the second semiconductor, and etching the second semiconductor to form a trench mated with the source electrode and/or the drain electrode A structure is formed, and then a source electrode and/or a drain electrode forming a low temperature (for example, 100 to 700 ° C) ohmic contact is formed on the formed device.

In some embodiments, the preparation method may further include an operation of etching a corresponding region of the source and drain electrodes in the passivation layer and/or the dielectric layer to form a window region or the like to subsequently provide a lead electrode or the like.

In the preparation method, the constituent materials of the barrier layer, the channel layer, the etch stop layer, the interposer layer, the gate dielectric layer, the passivation layer, the natural passivation layer, the buffer layer, the substrate, and the like may be As shown above.

In the etching process involved in the preparation method, the mask used is not limited to a photoresist or the like, and other dielectric layers such as SiO ₂ , Si ₃ N ₄ and the like can realize a mask function.

In addition, various epitaxial growth, physical or chemical deposition processes, micromachining processes, and the like involved in the preparation method may be employed in a suitable manner known in the art unless otherwise specified.

The following is a detailed description of some of the exemplary embodiments of the second embodiment of the present invention.

Embodiment 5: The structure of the HEMT includes a buffer layer formed on a substrate, an Al _x Ga _1-x N/GaN heterojunction (x = 0.1 to 0.4), an etch stop layer, a passivation layer, and a source electrode ( Referred to as the source), drain electrode (referred to as the drain), gate electrode (referred to as the gate). The substrate may be a substrate such as sapphire, silicon carbide, gallium nitride, or aluminum nitride, but is not limited thereto. The material of the buffer layer may be used in the industry, and may be, for example, GaN, AlGaN, or the like.

In the barrier layer, the Al composition changes stepwise with the growth direction z, high Al content AlGaN (Al _0.4 Ga _0.6 N) as an etch stop layer.

S1, MOCVD epitaxial growth of HEMT based on AlGaN/GaN heterojunction. The Al composition barrier layer Al composition x is 40%, 30%, 20%, 10% in the z direction of the epitaxial growth, the barrier layer thickness is 5 to 30 nm, and the etching stop layer Al _0.4 Ga _0.6 N is 1 thickness. ～8 nm; AlN insertion layer is about 1 nm; GaN channel layer is 50 to 200 nm. The epitaxial structure of the HEMT is shown in Figures 21a-21b.

S2, etching source, and leakage ohmic contact groove. The photoresist layer AZ5214 is used as a mask, and the barrier layer is etched by an ICP (Inductive Coupled Plasma) etching technique. In the etching gas, the oxygen content volume ratio accounts for 2% to 70%, and the etching rate is controlled at 5 to 200 nm/min. Barrier layer Al _0.4 Ga _0.6 N etch stop layer to control the depth of etching, the remaining thickness of the Al _0.4 Ga _0.6 N etch stop layer can be controlled at 1 ~ 8nm, generates Al ₂ O ₃ oxide layer thickness of about 0.5 ~ 5nm , as shown in Figure 22.

S3, source and drain ohmic contact groove area surface oxide layer corrosion. The oxide layer formed in the etching process is etched by a wet etching process, including BOE, HCl solution, etc., as shown in FIG.

S4, source and drain ohmic contact. The electron beam evaporation technique was used to prepare a metal Ti/Al/Ni/Au having a thickness of 20 nm/130 nm/50 nm/150 nm. The low temperature annealing conditions are 100 to 700 ° C, 30 to 50 s, and a nitrogen atmosphere, as shown in FIG.

S5, active area isolation. Ion implantation is performed by N ion implantation technology, and the ion implantation energy is 150-400 KeV ion implantation, and the implantation ion dose is 10 ¹² to 10 ¹⁴ /cm ² , and the implantation depth is about 50 to 250 nm beyond the buffer layer, as shown in FIG. 25 .

S6, passivation layer deposition. The SiN _x passivation layer is deposited by a dielectric layer deposition technique such as PECVD, ICP-CVD, or LPCVD to a thickness of 50 to 500 nm as shown in FIG.

S7, the window opens. The SiN _x was etched by RIE (Reactive Ion Etch) using the photoresist AZ5214 as a mask (1 to 2 μm) to realize gate opening, as shown in FIG.

S8, etching the trench gate. Based on the "gate window", the photoresist AZ5214 is used as a mask, and the barrier layer is etched by ICP (Inductive Coupled Plasma) etching. In the etching gas, the oxygen content volume ratio accounts for 2% to 70%, and the etching rate is controlled at 5 to 200 nm/min. Barrier layer Al _0.4 Ga _0.6 N etch stop layer to control the depth of etching, the remaining thickness of the Al _0.4 Ga _0.6 N etch stop layer can be controlled at 1 ~ 8nm, the groove width of the gate 1 ~ 4μm, formation of an oxide layer is Al ₂ O _{3 has a} thickness of about 0.5 to 5 nm as shown in FIG.

S9, gate dielectric layer deposition. The photoresist is removed, and the gate dielectric layer Al ₂ O _{3 is} deposited by an ALD (Atom Layer Deposition) technique to a thickness of 2 to 50 nm as shown in FIG.

S10, gate metal deposition. Using electron beam evaporation technique, the preparation conditions were as follows: metal Ni/Au, thickness 50 nm / 250 nm, as shown in FIG.

S11, source and drain ohmic contact open windows. AZ5214 photoresist as a mask (1 ~ 2μm), by plasma etching (in the present embodiment, the chlorine-containing plasma etch Al ₂ O _3, a fluorine-containing plasma etching SiN _x), to achieve The source and drain ohmic contacts open the window as shown in FIG.

S12, lead electrode. Preparation conditions: Metal Ni/Au, thickness 50 nm / 400 nm, as shown in FIG.

Embodiment 6: The structure of the HEMT includes a buffer layer formed on a substrate, an Al _x Ga _1-x N/GaN heterojunction (x = 0.1 to 0.4), an etch stop layer, a passivation layer, and a source electrode ( Referred to as the source), drain electrode (referred to as the drain), gate electrode (referred to as the gate). The substrate may be a substrate such as sapphire, silicon carbide, gallium nitride, or aluminum nitride, but is not limited thereto. The material of the buffer layer may be used in the industry, and may be, for example, GaN, AlGaN, or the like.

In the barrier layer, the Al composition changes stepwise and linearly with the growth z direction, and the high Al composition AlGaN (Al _0.4 Ga _0.6 N) serves as an etch stop layer.

S1, MOCVD epitaxial growth of HEMT based on AlGaN/GaN heterojunction. The Al composition barrier layer Al composition x is first maintained at 40% along the epitaxial growth z direction; then, the Al composition first linearly changes along the epitaxial growth z direction, and the Al composition varies from 40% to 10%. A barrier layer having a thickness of 5 ~ 30nm, the etch stop layer is Al _0.4 Ga _0.6 N having a thickness of 1 ~ 8nm; AlN layer inserted about 1nm; GaN channel layer is 50 ~ 200nm. The epitaxial structure of the HEMT is shown in Figures 33a-33b.

S2 to S12: S2 to S12 in the same manner as in the first embodiment. In the "etching source and drain ohmic contact groove" by Al _0.4 Ga _0.6 N etch depth control layer, etch stop barrier layer, the remaining thickness of the Al _0.4 Ga _0.6 N etch stop layer can be controlled at 1 ~ 8 nm, at the same time, the thickness of the oxide layer Al ₂ O ₃ is controlled to be 0.5 to 5 nm by an etching gas containing oxygen, and the oxide layer is etched by a wet etching process including BOE, HCl solution or the like. In the "etched trench gate" by Al _0.4 Ga _0.6 N etch stop layer to control the etching depth of the barrier layer, the remaining thickness of the Al _0.4 Ga _0.6 N etch stop layer can be controlled at 1 ~ 8nm, the gate width of the groove 1 to 4 μm. At the same time, the thickness of the oxide layer Al ₂ O ₃ formed by the etching gas containing oxygen is controlled to be 0.5 to 5 nm. The device after completing the entire chip process is shown in Figure 34.

Embodiment 7: The structure of the HEMT includes a buffer layer formed on a substrate, an Al _x Ga _1-x N/GaN heterojunction (x = 0.1 to 0.4), an etch stop layer, a passivation layer, and a source electrode ( Referred to as the source), drain electrode (referred to as the drain), gate electrode (referred to as the gate). The substrate may be a substrate such as sapphire, silicon carbide, gallium nitride, or aluminum nitride, but is not limited thereto. The material of the buffer layer may be used in the industry, and may be, for example, GaN, AlGaN, or the like.

In the barrier layer, the Al composition changes stepwise and nonlinearly with the growth z direction, and the high Al composition AlGaN (Al _0.4 Ga _0.6 N) serves as an etch stop layer.

S1, MOCVD epitaxial growth of HEMT based on AlGaN/GaN heterojunction. The Al composition barrier layer Al composition x is first maintained at 40% along the epitaxial growth z direction; then, the Al composition first undergoes a nonlinear change along the epitaxial growth z direction, and the Al composition varies from 40% to 10%. The thickness of the barrier layer is 5 to 30 nm, the thickness of the etch stop layer Al _0.4 Ga _0.6 N is 1 to 8 nm, the AlN insertion layer is about 1 nm, and the GaN channel layer is 50 to 200 nm. The HEMT epitaxial structure is shown in Figures 35a-35b.

S2 to S12: S2 to S12 in the same manner as in the first embodiment. In the "etching source and drain ohmic contact groove" by Al _0.4 Ga _0.6 N etch depth control layer, etch stop barrier layer, the remaining thickness of the Al _0.4 Ga _0.6 N etch stop layer can be controlled at 1 ~ 8nm, at the same time, by the etching gas containing oxygen, formation of an oxide layer thickness of the Al ₂ O ₃ control 0.5 ~ 5nm, and wet etching process, comprising BOE, HCl solutions and the like, the oxide layer etching. In the "etched trench gate" by Al _0.4 Ga _0.6 N etch stop layer to control the etching depth of the barrier layer, the remaining thickness of the Al _0.4 Ga _0.6 N etch stop layer can be controlled at 1 ~ 8nm, the gate width of the groove 1 to 4 μm. At the same time, the thickness of the oxide layer Al ₂ O ₃ formed by the etching gas containing oxygen is controlled to be 0.5 to 5 nm. The device after completing the entire chip process is shown in Figure 36.

Embodiment 8: The structure of the HEMT includes a buffer layer formed on a substrate, an AlGaN/GaN heterojunction, an etch stop layer, a passivation layer, a source electrode (abbreviated as a source), a drain electrode (abbreviated as a drain), Gate electrode (referred to as gate) and the like. The substrate may be a substrate such as sapphire, silicon carbide, gallium nitride, or aluminum nitride, but is not limited thereto. The material of the buffer layer may be used in the industry, and may be, for example, GaN, AlGaN, or the like.

Wherein, the barrier layer is a multilayer heterojunction structure, and the high Al composition AlGaN is used as an etch stop layer (Al _0.4 Ga _0.6 N/Al _0.5 Ga _0.5 N).

S1, MOCVD epitaxial growth of HEGaN based on AlGaN/GaN heterojunction, see Figure 37a. Among them, the Al composition barrier layer Al composition x changes along the epitaxial growth z direction as shown in FIG. 37b. The barrier layer has a thickness of 5 to 30 nm; the AlN insertion layer has a thickness of about 1 nm; and the GaN channel layer has a thickness of 50 to 200 nm.

S2 to S12: S2 to S12 in the same manner as in the first embodiment. In the "etching source, drain ohmic contact groove", the etching depth of the barrier layer is controlled by an Al _0.4 Ga _0.6 N/Al _0.5 Ga _0.5 N etch stop layer, and the remaining Al _0.4 Ga _0.6 N/Al _0.5 Ga _0.5 The thickness of the N etch stop layer can be controlled at 1-8 nm. At the same time, the thickness of the oxide layer Al ₂ O ₃ is controlled to 0.5 to 5 nm by the etching gas containing oxygen, and the wet etching process is adopted, including BOE and HCl solution. Etc., the oxide layer is etched. In the "etched trench gate", the high Al composition AlGaN in the barrier layer controls the etching depth of the barrier layer by Al _0.4 Ga _0.6 N/Al _0.5 Ga _0.5 N, and the remaining Al _0.4 Ga _0.6 N/Al _0.5 Ga _0.5 The thickness of the N etch stop layer can be controlled to be 1 to 8 nm, and the width of the trench gate is 1 to 4 μm. At the same time, the thickness of the oxide layer Al ₂ O ₃ formed by the etching gas containing oxygen is controlled to be 0.5 to 5 nm. The device after completing the entire chip process is shown in Figure 38.

A second embodiment of the present invention epitaxially grows an etch stop layer during the preparation of a HEMT device, that is, by epitaxially growing a material having a higher etching selectivity ratio, and combining etching techniques to precisely control the etching of the barrier layer. Depth, reduce interface etch damage, ensure process stability in the gate region, and ensure that the electrical characteristics of the device, including threshold voltage and output current, are not affected by the etching process, greatly reducing the trench gate technology during process implementation. The difficulty is also advantageous for accurately preparing the groove type ohmic contact to realize the low temperature process, thereby avoiding the influence of the high temperature process on the device surface and the related device reliability problem to the utmost extent; especially, under the action of the etching process, The surface of the semiconductor, especially the etch stop layer, can naturally form a passivation layer, thereby avoiding a series of devices such as a dielectric layer/semiconductor layer interface problem caused by the gate dielectric layer deposition process and a threshold voltage drift caused by the interface problem. Reliability issues.

The various product structural parameters, various reaction participants and process conditions used in the foregoing embodiments are typical examples, but after various experiments and verifications by the inventors of the present invention, other different structural parameters listed above. Other types of reaction participants and other process conditions are also applicable, and the claimed technical effects of the present invention can also be achieved.

It is to be understood that the term "comprises", "comprising" or any other variations thereof is intended to encompass a non-exclusive inclusion, such that a process, method, article, or device that comprises a It also includes other elements that are not explicitly listed, or elements that are inherent to such a process, method, item, or device. An element that is defined by the phrase "comprising a ..." does not exclude the presence of additional equivalent elements in the process, method, item, or device that comprises the element.

The above is only a specific embodiment of the present invention, and it should be noted that those skilled in the art can also make several improvements and retouchings without departing from the principles of the present invention. It should be considered as the scope of protection of the present invention.

Claims

A group III nitride-enhanced HEMT comprising a heterojunction mainly composed of a first semiconductor as a channel layer and a second semiconductor as a barrier layer, and a source, a gate and a source connected to the heterojunction The drain is characterized by:

The HEMT has a first structure or a second structure based on an etch stop layer;

In the first structure, an etch stop layer is distributed between the second semiconductor and the first semiconductor, and a constituent material of the etch stop layer is compared with the second semiconductor for the selected etchant The constituent material has higher etching resistance, or an etch stop layer is formed at the set depth in the second semiconductor, and the constituent material of the etch stop layer is compared with the selected etchant The constituent materials of the remaining portion of the second semiconductor have higher etching resistance.

In the second structure, a third semiconductor is further disposed between the gate and the barrier layer, and the second semiconductor and the third semiconductor have different conductivity types; wherein the third semiconductor and the second semiconductor An etch stop layer is also disposed therebetween, or an etch stop layer is formed in a region adjacent to the third semiconductor in the second semiconductor, and a constituent material of the etch stop layer is selected for the selected etchant The constituent material of the third semiconductor has higher etching resistance.
The group III nitride-enhanced HEMT according to claim 1, wherein in the first structure, a trench structure in which a gate is coordinated is disposed in the barrier layer, and at least the gate is The pole lower portion is disposed in the groove-like structure.
The group III nitride-enhanced HEMT according to claim 1, wherein in the first structure, the second semiconductor is directly stacked on the etch stop layer, or the etching is terminated. The layer is formed in a region of the second semiconductor that is relatively close to the first semiconductor.
The group III nitride-enhanced HEMT according to claim 2, wherein a groove-like structure that is coupled to the source and/or the drain is distributed in the barrier layer.
The group III nitride-enhanced HEMT according to claim 1, wherein in the second structure, a passivation layer is further provided on the etch stop layer or the second semiconductor, and the passivation The layer includes a native passivation layer formed in situ by at least a partial region of the surface layer of the etch stop layer or a local region of the second semiconductor skin layer reacting with the etchant.
The group III nitride-enhanced HEMT according to claim 1, wherein in the second structure, the constituent material of the third semiconductor comprises p-GaN, p-AlGaN, p-AlInN, p Any one or a combination of two or more of InGaN and p-AlInGaN.
The group III nitride-enhanced HEMT according to claim 1, wherein the barrier layer has a constituent material selected from at least Al x In y Ga z N (0 < x ≤ 1, 0 ≤ y ≤ 1, (x+y+z)=1), and/or, the constituent material of the channel layer includes any one or a combination of two or more of GaN, InGaN, AlGaN, AlInN, AlInGaN, and/or The constituent material of the etch stop layer includes any one of AlN, SiN x (0 < x ≤ 3), Al x Ga 1-x N (0 < x < 1), or a combination of two or more.
The enhancement mode III-nitride HEMT according to claim 1, wherein: in the second configuration, the constituent material of the barrier layer is selected from Al x In y Ga z N ( 0 <x≤ 1, 0 ≤ y ≤ 1, (x + y + z) = 1), wherein x generally decreases in a direction away from the first semiconductor.
The III-nitride reinforced HEMT of claim 1 wherein said selected etchant is at least selected from the group consisting of etching gases containing oxygen.
The group III nitride-enhanced HEMT according to claim 1, wherein the heterojunction further comprises an intervening layer distributed between the first semiconductor and the second semiconductor, the constituent material of the interposer comprising AlN Any one or a combination of two or more of AlInN and AlInGaN.
The method for producing a group III nitride-enhanced HEMT according to any one of claims 1 to 10, comprising: sequentially growing a first semiconductor as a channel layer and a second semiconductor as a barrier layer on the substrate, Thereby forming a heterojunction mainly composed of the first semiconductor and the second semiconductor; characterized in that it further comprises:

Forming a first structure based on an etch stop layer, comprising: forming an etch stop layer at a set depth within the second semiconductor, wherein a constituent material of the etch stop layer is selected for a selected etchant Forming material with the rest of the second semiconductor has higher etching resistance, or forming an etch stop layer between the first semiconductor and the second semiconductor, wherein the etching is terminated for the selected etching material The constituent material of the layer has higher etching resistance than the constituent material of the second semiconductor;

Alternatively, preparing a second structure based on an etch stop layer includes: forming a third semiconductor having a different conductivity type from the second semiconductor on the second semiconductor, and adjacent to the third semiconductor in the second semiconductor Forming an etch stop layer in the region, or forming an etch stop layer between the second semiconductor and the third semiconductor, wherein the constituent material of the etch stop layer is compared to the selected etchant The constituent material of the third semiconductor has higher etching resistance.
The preparation method according to claim 11, further comprising:

After forming the first structure, a patterned mask is disposed on the second semiconductor, and the second semiconductor is etched to form a trench structure matching the gate, and the etch stop layer is exposed And then providing a gate, a source and a drain on the device formed by the foregoing steps;

Alternatively, after forming the second structure, forming a gate material layer on the third semiconductor, and then providing a patterned mask on the gate material layer, and forming a gate material layer and a third semiconductor Etching is performed to form a gate electrode, and the second semiconductor or etch stop layer is exposed, and then the source and drain electrodes are disposed on the device formed by the foregoing steps.
The preparation method according to claim 12, further comprising:

After forming the first structure, a patterned mask is disposed on the second semiconductor, and the second semiconductor is etched to form a trench structure mated with the gate, and an etching operation is performed in the The etched material reacts with a local region of the surface layer of the etch stop layer to form an automatic passivation layer in situ and then automatically stops;

Or, after forming the second structure, providing a patterned mask on the gate material layer, and etching the third semiconductor with the selected etching material until the etching material and etching The local area reaction of the surface layer of the termination layer is terminated and the etching is stopped after the natural passivation layer is formed in situ.
The preparation method according to claim 12, further comprising:

After forming the first structure, a patterned mask is disposed on the second semiconductor, and the second semiconductor is etched to form a groove-like structure in ohmic contact with the source and the drain, and the etching operation is performed. After the etching material reacts with a local region of the surface layer of the etch stop layer to form a natural passivation layer in situ, and then automatically stops, and then forms a source and/or a drain for forming a low temperature ohmic contact on the formed device;

Alternatively, in the process of preparing the HEMT including the second structure, after forming the gate electrode, a passivation layer is disposed on the surface of the obtained device, and a window region is formed on the passivation layer, after The source and drain are set in the window area.
The method according to claim 12, further comprising: in the process of preparing the HEMT comprising the first structure, performing active region isolation on the device for fabricating the source and the drain, and then growing the overlay a passivation layer of the source, the drain and the second semiconductor, and processing a pass window region on the passivation layer, and then providing a patterned mask covering the passivation layer and exposing from the patterned mask The gate window region etches the second semiconductor to form the trench structure, and at least the gate dielectric layer is disposed on the inner wall of the trench structure, and then the gate is formed.
The method according to claim 11, further comprising: in the first structure, the second semiconductor is directly stacked on the etch stop layer, or the etch stop layer is formed on The second semiconductor is relatively close to the region of the first semiconductor.