CN110459472A - Enhanced GaN field effect transistor and its manufacturing method - Google Patents
Enhanced GaN field effect transistor and its manufacturing method Download PDFInfo
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- CN110459472A CN110459472A CN201910718621.6A CN201910718621A CN110459472A CN 110459472 A CN110459472 A CN 110459472A CN 201910718621 A CN201910718621 A CN 201910718621A CN 110459472 A CN110459472 A CN 110459472A
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- 230000005669 field effect Effects 0.000 title claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 230000004888 barrier function Effects 0.000 claims abstract description 31
- 150000001875 compounds Chemical class 0.000 claims abstract description 31
- 238000005530 etching Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000002161 passivation Methods 0.000 claims abstract description 9
- 239000000463 material Substances 0.000 claims description 47
- 150000004767 nitrides Chemical class 0.000 claims description 24
- 229910002704 AlGaN Inorganic materials 0.000 claims description 16
- 239000012535 impurity Substances 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 238000002360 preparation method Methods 0.000 claims description 4
- 229910052790 beryllium Inorganic materials 0.000 claims description 3
- 229910052793 cadmium Inorganic materials 0.000 claims description 3
- 229910052799 carbon Inorganic materials 0.000 claims description 3
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- 229910052749 magnesium Inorganic materials 0.000 claims description 3
- 229910052753 mercury Inorganic materials 0.000 claims description 3
- 230000010287 polarization Effects 0.000 claims description 3
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- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
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- 208000027418 Wounds and injury Diseases 0.000 abstract description 5
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- 238000005516 engineering process Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000005566 electron beam evaporation Methods 0.000 description 3
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- 239000010980 sapphire Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- -1 AlGaN Chemical class 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
Abstract
The present invention is suitable for technical field of semiconductor device, disclose a kind of enhanced GaN field effect transistor and its manufacturing method, enhanced GaN field effect transistor successively includes substrate, nucleating layer, buffer layer, channel layer, barrier layer, compound cap and source electrode, drain electrode and gate electrode from bottom to top, and passivation layer is equipped between source electrode and gate electrode and between drain electrode and gate electrode；Wherein, compound cap includes multilayer cap, and at least one layer of cap is p-type cap in multilayer cap；Source electrode and drain electrode is respectively on channel layer, and gate electrode is located in p-type cap.The present invention is not necessarily to etch the region cap the grid of source and grid leak, on the one hand can be avoided influence of the etching injury to barrier layer, improves device performance；On the other hand it can be substantially reduced etching area, reduce process costs.
Description
Technical field
The invention belongs to technical field of semiconductor device more particularly to a kind of enhanced GaN field effect transistor and its systems
Make method.
Background technique
GaN HEMT device (including enhanced GaN HEMT device) has high frequency, high-power, high temperature resistant and anti-radiation etc.
Good characteristic is very suitable for the fields such as mobile communication, military radar, aerospace.
Currently, the enhanced GaN field effect transistor of p-type cap technology realization is generallyd use, but p-type cap technology
Implementation method be to etch away the p-type cap on the barrier layer between grid source and between grid leak, this method be easy to cause gesture
The etching injury of barrier layer, and etching area is larger, high process cost.
Summary of the invention
In view of this, the embodiment of the invention provides a kind of enhanced GaN field effect transistor and its manufacturing method, with solution
The problem of certainly prior art be easy to cause the etching injury of barrier layer, and etching area is larger, high process cost.
The first aspect of the embodiment of the present invention provides a kind of enhanced GaN field effect transistor, successively wraps from bottom to top
Include substrate, nucleating layer, buffer layer, channel layer, barrier layer, compound cap and source electrode, drain electrode and gate electrode, source electrode
Passivation layer is equipped between gate electrode and between drain electrode and gate electrode；
Wherein, compound cap includes multilayer cap, and at least one layer of cap is p-type nut cap in multilayer cap
Layer；
Source electrode and drain electrode is respectively on channel layer, and gate electrode is located in p-type cap.
The second aspect of the embodiment of the present invention provides a kind of manufacturing method of enhanced GaN field effect transistor, comprising:
Nucleating layer is grown on substrate；
The grown buffer layer on nucleating layer；
Channel layer is grown on the buffer layer；
Barrier layer is grown on channel layer；
The growing mixed cap on barrier layer, compound cap include multilayer cap, and in multilayer cap at least
One layer of cap is p-type cap；
It at preparation source electrode and drain electrode, performs etching, and be etched to channel layer, forms source electrode and drain electrode；
It is preparing at gate electrode, compound cap is being performed etching, be etched at p-type cap, forming gate electrode；
Deposit passivation layer between source electrode and gate electrode and between gate electrode and drain electrode.
Existing beneficial effect is the embodiment of the present invention compared with prior art: provided in an embodiment of the present invention enhanced
GaN field effect transistor, from bottom to top successively include substrate, nucleating layer, buffer layer, channel layer, barrier layer, compound cap with
And source electrode, drain electrode and gate electrode, passivation layer is equipped between source electrode and gate electrode and between drain electrode and gate electrode；Its
In, compound cap includes multilayer cap, and at least one layer of cap is p-type cap in multilayer cap.The present invention is real
The enhanced GaN field effect transistor that example offer is provided, without being etched between the region cap the grid of source and grid leak, on the one hand
It can be avoided influence of the etching injury to barrier layer, improve device performance；On the other hand it can be substantially reduced etching area, reduced
Process costs.
Detailed description of the invention
It to describe the technical solutions in the embodiments of the present invention more clearly, below will be to embodiment or description of the prior art
Needed in attached drawing be briefly described, it should be apparent that, the accompanying drawings in the following description is only of the invention some
Embodiment for those of ordinary skill in the art without any creative labor, can also be according to these
Attached drawing obtains other attached drawings.
Fig. 1 is the structural schematic diagram for the enhanced GaN field effect transistor that one embodiment of the invention provides；
Fig. 2 be another embodiment of the present invention provides enhanced GaN field effect transistor structural schematic diagram；
Fig. 3 is that the implementation process of the manufacturing method for the enhanced GaN field effect transistor that one embodiment of the invention provides is shown
It is intended to.
Specific embodiment
In being described below, for illustration and not for limitation, the tool of such as particular system structure, technology etc is proposed
Body details, so as to provide a thorough understanding of the present application embodiment.However, it will be clear to one skilled in the art that there is no these specific
The application also may be implemented in the other embodiments of details.In other situations, it omits to well-known system, device, electricity
The detailed description of road and method, so as not to obscure the description of the present application with unnecessary details.
In order to illustrate technical solutions according to the invention, the following is a description of specific embodiments.
Fig. 1 is the structural schematic diagram for the enhanced GaN field effect transistor that one embodiment of the invention provides, for the ease of saying
Bright, only parts related to embodiments of the present invention are shown.
As shown in Figure 1, enhanced GaN field effect transistor can successively include substrate 10, nucleating layer 20, delay from bottom to top
Rush layer 30, channel layer 40, barrier layer 50, compound cap 60 and source electrode 70, drain electrode 80 and gate electrode 90, source electrode 70
Passivation layer 100 is equipped between gate electrode 90 and between drain electrode 80 and gate electrode 90；
Wherein, compound cap 60 includes multilayer cap, and at least one layer of cap is p-type nut cap in multilayer cap
Layer；
Source electrode 70 and drain electrode 80 are respectively on channel layer 40, and gate electrode 90 is located in p-type cap.
In embodiments of the present invention, the forming material of substrate 10 may include sapphire, Si, SiC, AlN, GaN, glass,
Any one in the materials such as PV, PC and diamond.
The enhanced GaN field effect transistor of the embodiment of the present invention, using compound cap, the p that leaves after being etched under grid
Type cap can play the role of exhausting electronics in grid lower channel, realize enhancement device.Compared to traditional single p-type lid
The enhanced GaN field effect transistor of cap layers does not generate electronics in channel and exhausts since compound cap is by rationally designing
Effect, can make the compound cap between grid source and grid leak not need to etch, on the one hand avoid etching injury to barrier layer
It influences, improves device performance；On the other hand it is substantially reduced etching area, reduces process costs.
Fig. 2 be another embodiment of the present invention provides enhanced GaN field effect transistor structural schematic diagram.Such as Fig. 2 institute
Show, compound cap 60 successively includes the first cap 61, p-type cap 62 and the second cap 63 from bottom to top；
The thickness of compound cap 60 is greater than 1nm, and is less than or equal to 1500nm.
In embodiments of the present invention, compound cap 60 may include close to barrier layer 50 the first cap 61, be located at
P-type cap 62 in first cap 61 and the second cap 63 in p-type cap 62.Wherein, compound cap
60 thickness range is 1nm~1500nm.
In one embodiment of the invention, the forming material of the first cap 61 includes III race's nitrogen of p-type of acceptor doping
Compound material, wherein the impurity in III group nitride material of p-type of acceptor doping includes Li, Be, Cd, Hg, Zn, Mg, C and Si
In it is one or more, III group nitride material in III group nitride material of p-type of acceptor doping include GaN, AlGaN, InN,
One of InAlN, InGaN, BN, BAlN, BInN, BGaN, InAlGaN, BAlGaN, BInGaN and BInAlN or a variety of；
The thickness of first cap 61 is greater than or equal to 1nm, and is less than or equal to 500nm.
In embodiments of the present invention, the first cap 61 can be III group nitride material of p-type of acceptor doping, wherein
Impurity includes one of Li, Be, Cd, Hg, Zn, Mg, C and Si or a variety of；III group nitride material include GaN, AlGaN,
In the nitride materials such as InN, InAlN, InGaN, BN, BAlN, BInN, BGaN, InAlGaN, BAlGaN, BInGaN and BInAlN
It is one or more.The thickness range of first cap 61 is 1nm~500nm.
In one embodiment of the invention, the forming material of the second cap 63 includes one or more layers donor doping
III group nitride material of N-shaped, wherein the donor impurity in III group nitride material of N-shaped of donor doping includes Si, donor doping
III group nitride material of N-shaped in III group nitride material include GaN, AlGaN, InN, InAlN, InGaN, BN, BAlN,
One of BInN, BGaN, InAlGaN, BAlGaN, BInGaN and BInAlN or a variety of；
The polarization intensity of second cap 63 is greater than the first cap, and the thickness of the second cap is greater than or equal to 1nm, and
Less than or equal to 1000nm.
In embodiments of the present invention, the second cap 63 can be III group-III nitride of N-shaped of one or more layers donor doping
Material, wherein donor impurity includes that Si etc. commonly uses III group nitride material donor element；III group nitride material include GaN,
The nitride such as AlGaN, InN, InAlN, InGaN, BN, BAlN, BInN, BGaN, InAlGaN, BAlGaN, BInGaN and BInAlN
One of material is a variety of.
The thickness range of second layer cap 63 is 1nm~1000nm；The polarization intensity of second layer cap 63 is greater than the
One layer of cap 61.
In one embodiment of the invention, the forming material of barrier layer 50 includes AlxGa1-xN, wherein 0 < x≤1；
The thickness of barrier layer 50 is greater than or equal to 1nm, and is less than or equal to 100nm.
In embodiments of the present invention, barrier layer 50 can be AlxGa1-xN material.Wherein, x is the component of Al, 1-x Ga
Component, x meets relationship: 0 < x≤1.The thickness range of barrier layer 50 can be 1nm~100nm.
In one embodiment of the invention, the forming material of barrier layer 50 includes InyAlzGa1-y-zN, wherein 0≤y≤
1,0≤z≤1；
The thickness of barrier layer 50 is greater than or equal to 1nm, and is less than or equal to 100nm.
In embodiments of the present invention, barrier layer 50 can be InyAlzGa1-y-zN material.Wherein, y is the component of In, and z is
The component of Al, 1-y-z are the component of Ga, and y and z meet relationship: 0≤y≤1,0≤z≤1.Optionally, 0≤y+z≤1.
The thickness range of barrier layer 50 can be 1nm~100nm.
In one embodiment of the invention, the forming material of channel layer 40 includes any one in GaN and AlGaN；
The thickness of channel layer is greater than or equal to 1nm, and is less than or equal to 1000nm.
In embodiments of the present invention, channel layer 40 can be GaN or low Al component AlGaN.The thickness range of channel layer 40
For 1nm~1000nm.
In one embodiment of the invention, the forming material of buffer layer 30 include BN, AlN, GaN, InN, AlGaN,
Any one in BGaN, InGaN, BAlN, InAlN, InAlGaN and BInN；
The thickness of buffer layer is greater than or equal to 1nm, and is less than or equal to 10000nm.
In embodiments of the present invention, buffer layer 30 can for BN, AlN, GaN, InN, AlGaN, BGaN, InGaN, BAlN,
Any one in the materials such as InAlN, InAlGaN and BInN.The thickness range of buffer layer 30 is 1nm~10000nm.
In one embodiment of the invention, the forming material of nucleating layer 20 include AlN, GaN, AlGaN, BGaN, BAlN,
Any one in InGaN and InAlGaN；
The thickness of nucleating layer is greater than or equal to 1nm, and is less than or equal to 500nm.
In embodiments of the present invention, nucleating layer 20 can be AlN, GaN, AlGaN, BGaN, BAlN, InGaN and InAlGaN
Wait any one in materials.The thickness range of nucleating layer 20 is 1nm~500nm.
Fig. 3 is that the implementation process of the manufacturing method for the enhanced GaN field effect transistor that one embodiment of the invention provides is shown
It is intended to, for ease of description, only parts related to embodiments of the present invention are shown.Wherein, the enhanced GaN field effect transistor
Pipe can be enhanced GaN field effect transistor as above.
As shown in figure 3, the manufacturing method of enhanced GaN field effect transistor may comprise steps of:
S301: nucleating layer is grown on substrate.
Wherein, the thickness range of nucleating layer is 1nm~500nm.
S302: the grown buffer layer on nucleating layer.
Wherein, the thickness range of buffer layer is 1nm~10000nm.
S303: channel layer is grown on the buffer layer.
Wherein, the thickness range of channel layer is 1nm~1000nm.
S304: barrier layer is grown on channel layer.
Wherein, the thickness range of barrier layer can be 1nm~100nm.
S305: the growing mixed cap on barrier layer, compound cap include multilayer cap, and in multilayer cap
At least one layer of cap is p-type cap.
Wherein, the thickness range of compound cap is 1nm~1500nm.
S306: it at preparation source electrode and drain electrode, performs etching, and be etched to channel layer, forms source electrode and electric leakage
Pole.
Specifically, it at preparation source electrode and drain electrode, performs etching, is etched to channel layer, then deposit ohmic contacts
Metal simultaneously carries out high temperature alloy formation source electrode and drain electrode.
S307: preparing at gate electrode, performs etching to compound cap, is etched at p-type cap, forms grid electricity
Pole.
Specifically, it is preparing at gate electrode position, compound cap is subjected to recess etch, is etched at p-type cap,
It contacts metal in groove Schottky and carries out high temperature alloy and form gate electrode.
S308: deposit passivation layer between source electrode and gate electrode and between gate electrode and drain electrode.
Optionally, each layer growth uses nitride epitaxial growth method；Nitride epitaxial growth method selects metallorganic
Learn vapor deposition epitaxial deposition, molecular beam epitaxy deposition, pulse laser deposition, magnetron sputtering deposition, electron beam evaporation deposition and
Any one in nitride epitaxial growth method in chemical vapor deposition.
In a specific application scenarios, using MOCVD (Metal-Organic Chemical Vapor
Deposition, metal organic-matter chemical vapor deposition) technique on a sapphire substrate, at 800 DEG C grow 20nm thickness GaN
Nucleating layer；Then at 1200 DEG C, the GaN buffer layer of 2 μ m-thicks, the GaN channel layer of regrowth 200nm thickness are grown；Then it grows
The Al group of 25nm thickness is divided into 22% AlGaN potential barrier；The compound cap of regrowth 100nm thickness, including growing first
The p-type GaN cap of 50nm thickness, hole concentration 1E18cm-3, then the N-shaped GaN cap of regrowth 50nm thickness, electronics are dense
Degree is 1E18cm-3.Then device isolation uses mesa-isolated technology；It is etched to below source electrode and drain electrode with electron beam
Channel layer, source and drain Ohmic contact uses the Ti/Al/Ni/Au of electron beam evaporation, then in 850 DEG C of annealing 30s.It will be compound under grid
Cap is etched to p-type cap and N-shaped nut cap bed boundary, using the Ni/Au of electron beam evaporation as grid metal.Finally deposit
SiNxAs passivation layer.4 μm of device source and drain spacing, 1 μm of grid length, 40 μm of grid width.
It should be understood that the size of the serial number of each step is not meant that the order of the execution order in above-described embodiment, each process
Execution sequence should be determined by its function and internal logic, the implementation process without coping with the embodiment of the present invention constitutes any limit
It is fixed.
Embodiment described above is only to illustrate the technical solution of the application, rather than its limitations；Although referring to aforementioned reality
Example is applied the application is described in detail, those skilled in the art should understand that: it still can be to aforementioned each
Technical solution documented by embodiment is modified or equivalent replacement of some of the technical features；And these are modified
Or replacement, the spirit and scope of each embodiment technical solution of the application that it does not separate the essence of the corresponding technical solution should all
Comprising within the scope of protection of this application.
Claims (10)
1. a kind of enhanced GaN field effect transistor, which is characterized in that from bottom to top successively include substrate, nucleating layer, buffering
Layer, channel layer, barrier layer, compound cap and source electrode, drain electrode and gate electrode, the source electrode and the gate electrode it
Between and the drain electrode and the gate electrode between be equipped with passivation layer；
Wherein, the compound cap includes multilayer cap, and at least one layer of cap is p-type lid in the multilayer cap
Cap layers；
The source electrode and the drain electrode are respectively on the channel layer, and the gate electrode is located in the p-type cap.
2. enhanced GaN field effect transistor according to claim 1, which is characterized in that the compound cap is under
It successively include the first cap, p-type cap and the second cap on and；
The thickness of the compound cap is greater than 1nm, and is less than or equal to 1500nm.
3. enhanced GaN field effect transistor according to claim 2, which is characterized in that the shape of first cap
It include III group nitride material of p-type of acceptor doping at material, wherein in III group nitride material of p-type of the acceptor doping
Impurity include one or more in Li, Be, Cd, Hg, Zn, Mg, C and Si, III group nitride material of p-type of the acceptor doping
In III group nitride material include GaN, AlGaN, InN, InAlN, InGaN, BN, BAlN, BInN, BGaN, InAlGaN,
One of BAlGaN, BInGaN and BInAlN or a variety of；
The thickness of first cap is greater than or equal to 1nm, and is less than or equal to 500nm.
4. enhanced GaN field effect transistor according to claim 2, which is characterized in that the shape of second cap
It include III group nitride material of N-shaped of one or more layers donor doping at material, wherein III race's nitrogen of N-shaped of the donor doping
Donor impurity in compound material includes Si, III group nitride material in III group nitride material of N-shaped of the donor doping
Including GaN, AlGaN, InN, InAlN, InGaN, BN, BAlN, BInN, BGaN, InAlGaN, BAlGaN, BInGaN and BInAlN
One of or it is a variety of；
The polarization intensity of second cap is greater than first cap, and the thickness of second cap is greater than or equal to
1nm, and it is less than or equal to 1000nm.
5. enhanced GaN field effect transistor according to claim 1, which is characterized in that the formation material of the barrier layer
Material includes AlxGa1-xN, wherein 0 < x≤1；
The thickness of the barrier layer is greater than or equal to 1nm, and is less than or equal to 100nm.
6. enhanced GaN field effect transistor according to claim 1, which is characterized in that the formation material of the barrier layer
Material includes InyAlzGa1-y-zN, wherein 0≤y≤1,0 < z≤1；
The thickness of the barrier layer is greater than or equal to 1nm, and is less than or equal to 100nm.
7. enhanced GaN field effect transistor according to claim 1, which is characterized in that the formation material of the channel layer
Material includes any one in GaN and AlGaN；
The thickness of the channel layer is greater than or equal to 1nm, and is less than or equal to 1000nm.
8. enhanced GaN field effect transistor according to claim 1, which is characterized in that the formation material of the buffer layer
Material includes any one in BN, AlN, GaN, InN, AlGaN, BGaN, InGaN, BAlN, InAlN, InAlGaN and BInN；
The thickness of the buffer layer is greater than or equal to 1nm, and is less than or equal to 10000nm.
9. enhanced GaN field effect transistor according to any one of claims 1 to 8, which is characterized in that the nucleating layer
Forming material include any one in AlN, GaN, AlGaN, BGaN, BAlN, InGaN and InAlGaN；
The thickness of the nucleating layer is greater than or equal to 1nm, and is less than or equal to 500nm.
10. a kind of manufacturing method of enhanced GaN field effect transistor characterized by comprising
Nucleating layer is grown on substrate；
Grown buffer layer on the nucleating layer；
Channel layer is grown on the buffer layer；
Barrier layer is grown on the channel layer；
The growing mixed cap on the barrier layer, the compound cap include multilayer cap, and the multilayer nut cap
At least one layer of cap is p-type cap in layer；
It at preparation source electrode and drain electrode, performs etching, and be etched to the channel layer, forms source electrode and drain electrode；
It is preparing at gate electrode, the compound cap is being performed etching, be etched at the p-type cap, forming gate electrode；
Deposit passivation layer between the source electrode and the gate electrode and between the gate electrode and the drain electrode.
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| WO2022042672A1 (en) * | 2020-08-28 | 2022-03-03 | 华灿光电（浙江）有限公司 | Gallium nitride-based high electron mobility transistor epitaxial wafer and preparation method therefor |
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