CN110459472B - Enhanced GaN field effect transistor and manufacturing method thereof - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
Abstract
The invention is suitable for the technical field of semiconductor devices, and discloses an enhanced GaN field effect transistor and a manufacturing method thereof, wherein the enhanced GaN field effect transistor sequentially comprises a substrate, a nucleating layer, a buffer layer, a channel layer, a barrier layer, a composite cap layer, a source electrode, a drain electrode and a gate electrode from bottom to top, and passivation layers are arranged between the source electrode and the gate electrode and between the drain electrode and the gate electrode; the composite cap layer comprises a plurality of cap layers, and at least one cap layer in the plurality of cap layers is a p-type cap layer; the source electrode and the drain electrode are respectively arranged on the channel layer, and the gate electrode is positioned on the p-type cover cap layer. According to the invention, the cap layer of the area between the source gates and the cap layer of the area between the gate drains are not required to be etched, so that the influence of etching damage on the barrier layer can be avoided, and the performance of the device is improved; on the other hand, the etching area can be greatly reduced, and the process cost is reduced.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to an enhanced GaN field effect transistor and a manufacturing method thereof.
Background
The GaN HEMT device (including an enhanced GaN HEMT device) has the excellent characteristics of high frequency, high power, high temperature resistance, radiation resistance and the like, and is very suitable for the fields of mobile communication, military radars, aviation, aerospace and the like.
At present, a p-type cap layer technology is usually adopted to realize an enhanced GaN field effect transistor, but the p-type cap layer technology is realized by etching the p-type cap layer on a barrier layer between a gate source and a gate drain, the method is easy to cause etching damage of the barrier layer, the etching area is large, and the process cost is high.
Disclosure of Invention
In view of this, embodiments of the present invention provide an enhancement mode GaN field effect transistor and a manufacturing method thereof, so as to solve the problems in the prior art that the barrier layer is easily damaged by etching, the etching area is large, and the process cost is high.
The first aspect of the embodiment of the invention provides an enhanced GaN field effect transistor, which sequentially comprises a substrate, a nucleating layer, a buffer layer, a channel layer, a barrier layer, a composite capping layer, a source electrode, a drain electrode and a gate electrode from bottom to top, wherein passivation layers are arranged between the source electrode and the gate electrode and between the drain electrode and the gate electrode;
the composite cap layer comprises a plurality of cap layers, and at least one cap layer in the plurality of cap layers is a p-type cap layer;
the source electrode and the drain electrode are respectively arranged on the channel layer, and the gate electrode is positioned on the p-type cover cap layer.
A second aspect of an embodiment of the present invention provides a method for manufacturing an enhanced GaN field effect transistor, including:
growing a nucleation layer on a substrate;
growing a buffer layer on the nucleation layer;
growing a channel layer on the buffer layer;
growing a barrier layer on the channel layer;
growing a composite cap layer on the barrier layer, wherein the composite cap layer comprises a plurality of cap layers, and at least one cap layer in the plurality of cap layers is a p-type cap layer;
etching the source electrode and the drain electrode to the channel layer to form a source electrode and a drain electrode;
etching the composite capping layer at the position of the gate electrode preparation position to the p-type capping layer to form a gate electrode;
a passivation layer is deposited between the source electrode and the gate electrode and between the gate electrode and the drain electrode.
Compared with the prior art, the embodiment of the invention has the following beneficial effects: the enhancement type GaN field effect transistor provided by the embodiment of the invention sequentially comprises a substrate, a nucleating layer, a buffer layer, a channel layer, a barrier layer, a composite capping layer, a source electrode, a drain electrode and a gate electrode from bottom to top, wherein passivation layers are arranged between the source electrode and the gate electrode and between the drain electrode and the gate electrode; the composite capping layer comprises a plurality of capping layers, and at least one capping layer in the plurality of capping layers is a p-type capping layer. According to the enhanced GaN field effect transistor provided by the embodiment of the invention, the cap layer of the region between the source gates and the cap layer of the region between the gate drains are not required to be etched, on one hand, the influence of etching damage on the barrier layer can be avoided, and the performance of the device is improved; on the other hand, the etching area can be greatly reduced, and the process cost is reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic structural diagram of an enhancement mode GaN field effect transistor according to an embodiment of the invention;
FIG. 2 is a schematic diagram of an enhancement mode GaN field effect transistor according to another embodiment of the invention;
fig. 3 is a schematic flow chart illustrating a method for manufacturing an enhancement mode GaN field effect transistor according to an embodiment of the invention.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
In order to explain the technical means of the present invention, the following description will be given by way of specific examples.
Fig. 1 is a schematic structural diagram of an enhancement mode GaN field effect transistor according to an embodiment of the present invention, and only the portions related to the embodiment of the present invention are shown for convenience of illustration.
As shown in fig. 1, the enhancement-mode GaN field-effect transistor may include, in order from bottom to top, a substrate 10, a nucleation layer 20, a buffer layer 30, a channel layer 40, a barrier layer 50, a composite cap layer 60, and a source electrode 70, a drain electrode 80, and a gate electrode 90, with passivation layers 100 disposed between the source electrode 70 and the gate electrode 90 and between the drain electrode 80 and the gate electrode 90;
wherein the composite capping layer 60 comprises a plurality of capping layers, and at least one of the plurality of capping layers is a p-type capping layer;
the source electrode 70 and the drain electrode 80 are separated on the channel layer 40, and the gate electrode 90 is located on the p-type cap layer.
In the embodiment of the present invention, the material forming the substrate 10 may include any one of sapphire, si, siC, alN, gaN, glass, PV, PC, and diamond.
According to the enhancement type GaN field effect transistor, the composite cap layer is utilized, and the p-type cap layer left after the etching under the gate can play a role in depleting electrons in a channel under the gate, so that an enhancement type device is realized. Compared with the traditional enhancement type GaN field effect transistor with a single-layer p-type cap layer, the composite cap layer is reasonably designed, so that electrons in a channel are not depleted, the composite cap layer between a gate source and a gate drain does not need to be etched, on one hand, the influence of etching damage on a barrier layer is avoided, and the performance of a device is improved; on the other hand, the etching area is greatly reduced, and the process cost is reduced.
Fig. 2 is a schematic structural diagram of an enhancement mode GaN field effect transistor according to another embodiment of the invention. As shown in fig. 2, the composite capping layer 60 comprises, from bottom to top, a first capping layer 61, a p-type capping layer 62 and a second capping layer 63 in sequence;
the thickness of the composite capping layer 60 is greater than 1nm and less than or equal to 1500nm.
In an embodiment of the present invention, the composite capping layer 60 may include a first capping layer 61 proximate to the barrier layer 50, a p-type capping layer 62 on the first capping layer 61, and a second capping layer 63 on the p-type capping layer 62. Wherein the thickness of the composite capping layer 60 is in the range of 1nm to 1500nm.
In one embodiment of the present invention, the material forming the first cap layer 61 comprises an acceptor-doped p-type group iii nitride material, wherein the impurities in the acceptor-doped p-type group iii nitride material comprise one or more of Li, be, cd, hg, zn, mg, C, and Si, and the group iii nitride material in the acceptor-doped p-type group iii nitride material comprises one or more of GaN, alGaN, inN, inAlN, inGaN, BN, BAlN, BInN, BGaN, inAlGaN, BAlGaN, BInGaN, and binalinn;
the thickness of the first cap layer 61 is greater than or equal to 1nm and less than or equal to 500nm.
In an embodiment of the present invention, the first cap layer 61 may Be an acceptor-doped p-type group iii nitride material, wherein the impurities include one or more of Li, be, cd, hg, zn, mg, C, and Si; the III group nitride material comprises one or more of GaN, alGaN, inN, inAlN, inGaN, BN, BAlN, BInN, BGaN, inAlGaN, BAlGaN, BInGaN, BInAlN and the like. The thickness of the first cap layer 61 ranges from 1nm to 500nm.
In one embodiment of the present invention, the material forming the second cap layer 63 comprises one or more layers of donor-doped n-type group iii nitride material, wherein the donor impurity in the donor-doped n-type group iii nitride material comprises Si, and the group iii nitride material in the donor-doped n-type group iii nitride material comprises one or more of GaN, alGaN, inN, inAlN, inGaN, BN, BAlN, BInN, BGaN, inAlGaN, BAlGaN, BInGaN, and nabiln;
the polarization strength of the second capping layer 63 is greater than that of the first capping layer, and the thickness of the second capping layer is greater than or equal to 1nm and less than or equal to 1000nm.
In embodiments of the present invention, the second cap 63 can be one or more layers of donor-doped n-type group iii nitride material, wherein the donor impurity includes donor elements of common group iii nitride materials such as Si; the III group nitride material comprises one or more of GaN, alGaN, inN, inAlN, inGaN, BN, BALN, BInN, BGaN, inAlGaN, BALGaN, BInGaN, BInAlN and the like nitride materials.
The thickness range of the second capping layer 63 is 1nm to 1000nm; the second capping layer 63 has a polarization strength greater than that of the first capping layer 61.
In one embodiment of the present invention, the material forming barrier layer 50 includes Al x Ga 1-x N, wherein, 0<x≤1；
The barrier layer 50 has a thickness of 1nm or more and 100nm or less.
In embodiments of the present invention, barrier layer 50 may be Al x Ga 1-x And (3) N material. Wherein x is a component of Al, 1-x is a component of Ga, and x satisfies the relationship: 0<x is less than or equal to 1. The thickness of the barrier layer 50 may be in the range of 1nm to 100nm.
In one embodiment of the present invention, the material forming barrier layer 50 includes In y Al z Ga 1-y-z N, wherein y is more than or equal to 0 and less than or equal to 1, and z is more than or equal to 0 and less than or equal to 1;
the barrier layer 50 has a thickness of 1nm or more and 100nm or less.
In the present inventionIn an illustrative embodiment, barrier layer 50 may be In y Al z Ga 1-y-z And (3) N material. Wherein y is an In component, z is an Al component, 1-y-z is a Ga component, and y and z satisfy the relationship: y is more than or equal to 0 and less than or equal to 1, and z is more than or equal to 0 and less than or equal to 1. Alternatively, 0 ≦ y + z ≦ 1.
The thickness of the barrier layer 50 may be in the range of 1nm to 100nm.
In one embodiment of the present invention, the material of the channel layer 40 includes any one of GaN and AlGaN;
the thickness of the channel layer is greater than or equal to 1nm and less than or equal to 1000nm.
In embodiments of the present invention, the channel layer 40 may be GaN or AlGaN of low Al composition. The thickness of the channel layer 40 ranges from 1nm to 1000nm.
In one embodiment of the present invention, the buffer layer 30 is formed of a material including any one of BN, alN, gaN, inN, alGaN, BGaN, inGaN, BAlN, inAlN, inAlGaN, and BInN;
the thickness of the buffer layer is greater than or equal to 1nm and less than or equal to 10000nm.
In the embodiment of the present invention, the buffer layer 30 may be any one of BN, alN, gaN, inN, alGaN, BGaN, inGaN, BAlN, inAlN, inAlGaN, BInN, and the like. The thickness of the buffer layer 30 ranges from 1nm to 10000nm.
In one embodiment of the present invention, the formation material of the nucleation layer 20 includes any one of AlN, gaN, alGaN, BGaN, BAlN, inGaN, and InAlGaN;
the thickness of the nucleation layer is greater than or equal to 1nm and less than or equal to 500nm.
In the embodiment of the present invention, the nucleation layer 20 may be any one of AlN, gaN, alGaN, BGaN, BAlN, inGaN, and InAlGaN. The thickness of the nucleation layer 20 ranges from 1nm to 500nm.
Fig. 3 is a schematic flow chart of an implementation of a method for manufacturing an enhancement mode GaN field effect transistor according to an embodiment of the present invention, and only a portion related to the embodiment of the present invention is shown for convenience of illustration. Wherein the enhancement mode GaN field effect transistor may be an enhancement mode GaN field effect transistor as described above.
As shown in fig. 3, the method of manufacturing the enhancement type GaN field effect transistor may include the steps of:
s301: a nucleation layer is grown on the substrate.
Wherein the thickness of the nucleation layer is 1 nm-500 nm.
S302: and growing a buffer layer on the nucleation layer.
Wherein the thickness range of the buffer layer is 1 nm-10000 nm.
S303: and growing a channel layer on the buffer layer.
Wherein the thickness range of the channel layer is 1 nm-1000 nm.
S304: and growing a barrier layer on the channel layer.
The thickness of the barrier layer may be in a range of 1nm to 100nm.
S305: and growing a composite capping layer on the barrier layer, wherein the composite capping layer comprises a plurality of capping layers, and at least one capping layer in the plurality of capping layers is a p-type capping layer.
Wherein the thickness range of the composite capping layer is 1 nm-1500 nm.
S306: and etching the source electrode and the drain electrode to the channel layer to form the source electrode and the drain electrode.
Specifically, at the source electrode and the drain electrode, etching is performed until reaching the channel layer, and then ohmic contact metal is deposited and high temperature alloy is performed to form the source electrode and the drain electrode.
S307: and etching the composite capping layer to the p-type capping layer to form a gate electrode at the position of the gate electrode.
Specifically, at the position of preparing the gate electrode, the composite cap layer is subjected to groove etching to the p-type cap layer, schottky contact metal is deposited at the groove, and high-temperature alloy is carried out to form the gate electrode.
S308: a passivation layer is deposited between the source electrode and the gate electrode and between the gate electrode and the drain electrode.
Optionally, the growth of each layer adopts a nitride epitaxial growth method; the nitride epitaxial growth method is any one of the nitride epitaxial growth methods of metal organic chemical vapor deposition epitaxial deposition, molecular beam epitaxial deposition, pulsed laser deposition, magnetron sputtering deposition, electron beam evaporation deposition and chemical vapor deposition.
In a specific application scene, a GaN nucleating layer with the thickness of 20nm is grown on a sapphire substrate by using a Metal-Organic Chemical Vapor Deposition (MOCVD) process at the temperature of 800 ℃; then growing a GaN buffer layer with the thickness of 2 mu m at 1200 ℃, and then growing a GaN channel layer with the thickness of 200 nm; then growing an AlGaN barrier layer with the thickness of 25nm and the Al component of 22 percent; and growing a composite cap layer with the thickness of 100nm, wherein the p-type GaN cap layer with the thickness of 50nm is grown firstly, the hole concentration is 1E18cm-3, and then the n-type GaN cap layer with the thickness of 50nm is grown, and the electron concentration is 1E18cm-3. Then, the device isolation uses a mesa isolation technology; etching to the channel layer under the source electrode and the drain electrode by electron beams, and using Ti/Al/Ni/Au evaporated by electron beams for source-drain ohmic contact, and then annealing at 850 ℃ for 30s. And etching the composite capping layer under the gate to the interface of the p-type capping layer and the n-type capping layer, and adopting electron beam evaporated Ni/Au as gate metal. Final deposition of SiN x As a passivation layer. The source-drain distance of the device is 4 mu m, the gate length is 1 mu m, and the gate width is 40 mu m.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (10)
1. An enhancement mode GaN field effect transistor is characterized by comprising a substrate, a nucleating layer, a buffer layer, a channel layer, a barrier layer, a composite capping layer, a source electrode, a drain electrode and a gate electrode from bottom to top in sequence, wherein passivation layers are arranged between the source electrode and the gate electrode and between the drain electrode and the gate electrode;
the composite capping layer comprises a plurality of capping layers, and at least one of the capping layers is a p-type capping layer; the composite cap layer sequentially comprises a first cap layer, a p-type cap layer and a second cap layer from bottom to top; the forming material of the first cap layer comprises an acceptor-doped p-type III-group nitride material, and the forming material of the second cap layer comprises one or more layers of donor-doped n-type III-group nitride materials; the polarization strength of the second cap layer is greater than that of the first cap layer;
the source electrode and the drain electrode are respectively arranged on the channel layer, the gate electrode is positioned on the p-type cap layer and is in contact with the p-type cap layer.
2. The enhancement mode GaN field effect transistor of claim 1 wherein the thickness of the composite cap layer is greater than 1nm and less than or equal to 1500nm.
3. The enhancement-mode GaN field-effect transistor of claim 2 wherein the impurities in the acceptor doped p-type group iii nitride material include one or more of Li, be, cd, hg, zn, mg and C, and wherein the group iii nitride material in the acceptor doped p-type group iii nitride material includes one or more of GaN, alGaN, inN, inAlN, inGaN, BN, BAlN, BInN, BGaN, inAlGaN, BAlGaN, BInGaN, and BInAlN;
the thickness of the first cap layer is greater than or equal to 1nm and less than or equal to 500nm.
4. The enhancement mode GaN field effect transistor of claim 2 wherein the donor impurity in the donor doped n-type group iii nitride material comprises Si and the group iii nitride material in the donor doped n-type group iii nitride material comprises one or more of GaN, alGaN, inN, inAlN, inGaN, BN, BAlN, BInN, BGaN, inAlGaN, BAlGaN, BInGaN, and BInAlN;
the thickness of the second cap layer is greater than or equal to 1nm and less than or equal to 1000nm.
5. The enhancement mode GaN FET of claim 1, wherein the barrier layer is formed from a material comprising Al x Ga 1-x N, wherein, 0<x≤1；
The thickness of the barrier layer is greater than or equal to 1nm and less than or equal to 100nm.
6. The enhancement mode GaN FET as claimed In claim 1, wherein the barrier layer is formed from a material comprising In y Al z Ga 1-y-z N, wherein y is more than or equal to 0 and less than or equal to 1,0<z≤1；
The barrier layer has a thickness of 1nm or more and 100nm or less.
7. The enhancement mode GaN field effect transistor of claim 1 wherein the channel layer is formed of a material including any one of GaN and AlGaN;
the thickness of the channel layer is greater than or equal to 1nm and less than or equal to 1000nm.
8. The enhancement mode GaN field effect transistor according to claim 1, wherein the buffer layer is formed from a material comprising any of BN, alN, gaN, inN, alGaN, BGaN, inGaN, BALN, inAlN, inAlGaN, and BInN;
the thickness of the buffer layer is greater than or equal to 1nm and less than or equal to 10000nm.
9. The enhancement mode GaN field effect transistor according to any of claims 1 to 8, wherein the formation material of the nucleation layer comprises any of AlN, gaN, alGaN, BGaN, BALN, inGaN, and InAlGaN;
the nucleation layer has a thickness greater than or equal to 1nm and less than or equal to 500nm.
10. A method of fabricating an enhanced GaN field effect transistor, comprising:
growing a nucleation layer on a substrate;
growing a buffer layer on the nucleation layer;
growing a channel layer on the buffer layer;
growing a barrier layer on the channel layer;
growing a composite capping layer on the barrier layer, wherein the composite capping layer comprises a plurality of capping layers, and at least one capping layer in the plurality of capping layers is a p-type capping layer; the composite cap layer sequentially comprises a first cap layer, a p-type cap layer and a second cap layer from bottom to top; the forming material of the first cap layer comprises an acceptor-doped p-type III-group nitride material, and the forming material of the second cap layer comprises one or more layers of donor-doped n-type III-group nitride materials; the polarization strength of the second cap layer is greater than that of the first cap layer;
etching the source electrode and the drain electrode to the channel layer to form a source electrode and a drain electrode;
etching the composite capping layer to the p-type capping layer to form a gate electrode at the gate electrode preparation position; the gate electrode is in contact with the p-type cap layer;
depositing a passivation layer between the source electrode and the gate electrode and between the gate electrode and the drain electrode.
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