CN208781852U - A kind of normally-off gallium nitride HEMT device - Google Patents
A kind of normally-off gallium nitride HEMT device Download PDFInfo
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- CN208781852U CN208781852U CN201820833002.2U CN201820833002U CN208781852U CN 208781852 U CN208781852 U CN 208781852U CN 201820833002 U CN201820833002 U CN 201820833002U CN 208781852 U CN208781852 U CN 208781852U
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Abstract
The application provides a kind of normally-off gallium nitride HEMT device, the device includes heterojunction structure and the source electrode connecting with the heterojunction structure, drain and gate, the heterojunction structure includes: the first semiconductor layer as channel layer and the second semiconductor layer as barrier layer, second semiconductor layer is formed on the first semiconductor layer, is formed with two-dimensional electron gas between the first semiconductor layer and the second semiconductor layer；It is formed with semiconductor insert layer on second semiconductor layer, p-type semiconductor layer is formed in the semiconductor insert layer, the upper surface of the p-type semiconductor layer is arranged in the grid, in electrical contact with the p-type semiconductor layer；The source electrode and the drain electrode are formed in the upper surface of the semiconductor insert layer across p-type semiconductor layer deposition by etching technics.Using embodiment each in the application, barrier layer can be prevented to be etched and be thinned, to avoid the reduction of two-dimensional electron gas, reduce conducting resistance.
Description
Technical field
This application involves technical field of semiconductor device, in particular to a kind of normally-off gallium nitride HEMT device.
Background technique
Because its conducting resistance is small, the features such as high temperature high voltage resistant, is obtaining more gallium nitride base high mobility transistor (HEMT)
Carry out more concerns.The HEMT device of normally-off (normally-off) has more extensive prospect in such devices.Mesh
Before, realize normally-off HEMT device mainstream technology route be by Gate below p-type GaN layer (pGaN) exhaust AlGaN
Two-dimensional electron gas (2DEG) between barrier layer (AlGaN barrier) and GaN channel layer (GaN channel), thus real
The shutdown of existing device.Source (source) and leak the formation of (drain) electrode then --- by way of etch away below source and drain
PGaN layer after, in AlGaN potential barrier surface deposit metal electrodes.Therefore, accurately etching is very important step.
Existing normally-off HEMT device can be by potential barrier in etching process due to form source electrode and drain electrode to deposit
Layer etching is thinned so as to cause barrier layer, and then two-dimensional electron gas is caused to reduce, and the conducting resistance of HEMT device is caused to increase
Greatly.As shown in Fig. 2, existing normally-off HEMT device, source electrode and drain electrode are plugged in barrier layer, barrier layer is caused to be thinned.
At least there are the following problems in the prior art: can etch barrier layer in etching process and subtract so as to cause barrier layer
It is thin, and then two-dimensional electron gas is caused to reduce, cause the conducting resistance of HEMT device to increase.
Utility model content
The purpose of the embodiment of the present application is to provide a kind of normally-off gallium nitride HEMT device, barrier layer is etched to prevent and
It is thinned, to avoid the reduction of two-dimensional electron gas, reduces conducting resistance.
The embodiment of the present application provides a kind of normally-off gallium nitride HEMT device and is achieved in that
A kind of normally-off gallium nitride HEMT device, including heterojunction structure and the source electrode being connect with the heterojunction structure, drain electrode
And grid, the heterojunction structure include:
The first semiconductor layer as channel layer and the second semiconductor layer as barrier layer, the second semiconductor layer shape
At on first semiconductor layer, Two-dimensional electron is formed between first semiconductor layer and second semiconductor layer
Gas；
It is formed with semiconductor insert layer on second semiconductor layer, is formed with p-type in the semiconductor insert layer and partly leads
The upper surface of the p-type semiconductor layer is arranged in body layer, the grid, in electrical contact with the p-type semiconductor layer；
The source electrode and the drain electrode are formed in across p-type semiconductor layer deposition and described are partly led by etching technics
The upper surface of body insert layer.
In preferred embodiment, the composition material of the semiconductor insert layer includes AlN, AlxGa(1-x)Any one in N
Or two kinds of combination, wherein x > 30%；
The etching selection ratio of the semiconductor insert layer and second semiconductor layer, be greater than the p-type semiconductor layer with
The etching selection ratio of second semiconductor layer.
In preferred embodiment, the thickness of the semiconductor insert layer is more than or equal to 0.5 nanometer and is less than or equal to 3 nanometers.
In preferred embodiment, the composition material of the p-type semiconductor is p-type gallium nitride, and the thickness of the p-type semiconductor is big
In equal to 50 nanometers and less than or equal to 150 nanometers.
In preferred embodiment, the composition material of first semiconductor layer is gallium nitride, the thickness of first semiconductor layer
Degree is more than or equal to 50 nanometers and is less than or equal to 350 nanometers.
In preferred embodiment, the composition material of second semiconductor layer is AlxGa(1-x)N, second semiconductor layer
Thickness is more than or equal to 10 nanometers and is less than or equal to 30 nanometers, wherein 10%≤x≤30%.
In preferred embodiment, the device further includes substrate, is distributed between the substrate and first semiconductor layer
Buffer layer.
In preferred embodiment, the composition material of the substrate include silicon, sapphire, silicon carbide, gallium nitride, in aluminium nitride
Any one or two or more combinations, the composition material of the buffer layer include gallium nitride or aluminium gallium nitride alloy.
It, can be by as barrier layer using a kind of normally-off gallium nitride HEMT device provided by the embodiments of the present application
Growth forms semiconductor insert layer between second semiconductor layer and the p-type semiconductor, effectively source electrode and drain electrode is avoided to carve
A part that second semiconductor layer is etched away when erosion effectively avoids barrier layer from being thinned.So as to avoid two-dimensional electron gas
Concentration reduces, and then the conducting resistance of the HEMT device is effectively reduced.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The some embodiments recorded in application, for those of ordinary skill in the art, in the premise of not making the creative labor property
Under, it is also possible to obtain other drawings based on these drawings.
Fig. 1 is a kind of structural schematic diagram for normally-off gallium nitride HEMT device that the application one embodiment provides；
Fig. 2 is a kind of structural schematic diagram of existing normally-off gallium nitride HEMT device.
Specific embodiment
The embodiment of the present application provides a kind of normally-off gallium nitride HEMT device.
In order to make those skilled in the art better understand the technical solutions in the application, below in conjunction with the application reality
The attached drawing in example is applied, the technical scheme in the embodiment of the application is clearly and completely described, it is clear that described implementation
Example is merely a part but not all of the embodiments of the present application.Based on the embodiment in the application, this field is common
The application protection all should belong in technical staff's every other embodiment obtained without creative efforts
Range.
Fig. 1 is a kind of a kind of herein described structural schematic diagram of embodiment of normally-off gallium nitride HEMT device.Although this
Application provides as the following examples or method operating procedure shown in the drawings or structure, but based on conventional or without creativeness
Labour may include more or less operating procedure or modular unit in the method or device.In logicality not
In the step of there are necessary causalities or structure, the execution sequence of these steps or the modular structure of device are not limited to the application
Embodiment or execution shown in the drawings sequence or structure.
Specifically, as described in Figure 1, a kind of a kind of embodiment of normally-off gallium nitride HEMT device provided by the present application can be with
Include: including heterojunction structure and the source electrode being connect with the heterojunction structure 5, drain electrode 6 and grid 7, the heterojunction structure
The first semiconductor layer 1 as channel layer and the second semiconductor layer 2 as barrier layer, second semiconductor layer
2 are formed on first semiconductor layer 1, are formed with two dimension between first semiconductor layer 1 and second semiconductor layer 2
Electron gas, dotted line indicates the two-dimensional electron gas position as shown in figure 1；
It is formed with semiconductor insert layer 3 on second semiconductor layer 2, p-type half is formed in the semiconductor insert layer 3
The upper surface of the p-type semiconductor layer 4 is arranged in conductor layer 4, the grid 7, in electrical contact with the p-type semiconductor layer 4；
The source electrode 5 and the drain electrode 6 are formed in described half across the p-type semiconductor layer 4 deposition by etching technics
The upper surface of conductor insert layer 3.
In this example, the composition material of the semiconductor insert layer 3 includes AlN, AlxGa(1-x)Any one in N or two kinds
Combination, wherein x > 30%；
The etching selection ratio of the semiconductor insert layer 3 and second semiconductor layer 2, is greater than the p-type semiconductor layer 4
With the etching selection ratio of second semiconductor layer 2.
In this example, the thickness of the semiconductor insert layer 3 is more than or equal to 0.5 nanometer and is less than or equal to 3 nanometers.
In this example, the composition material of the p-type semiconductor 4 is p-type gallium nitride, and the thickness of the p-type semiconductor is greater than etc.
In 50 nanometers and it is less than or equal to 150 nanometers.
In this example, the composition material of first semiconductor layer 1 is gallium nitride, and the thickness of first semiconductor layer 1 is big
In equal to 50 nanometers and less than or equal to 350 nanometers.
In this example, the composition material of second semiconductor layer 2 is AlxGa(1-x)N, the thickness of second semiconductor layer
More than or equal to 10 nanometers and it is less than or equal to 30 nanometers, wherein 10%≤x≤30%.
In this example, the device further includes substrate 9, and buffering is distributed between the substrate 9 and first semiconductor layer 1
Layer 8.
In this example, the composition material of the substrate 9 includes silicon, sapphire, silicon carbide, gallium nitride, any in aluminium nitride
A combination of one or more, the composition material of the buffer layer 9 include gallium nitride or aluminium gallium nitride alloy.
It, can be by conduct using a kind of embodiment of normally-off gallium nitride HEMT device provided by the above embodiment
Growth forms semiconductor insert layer between second semiconductor layer of barrier layer and the p-type semiconductor, effectively avoids source electrode
A part with second semiconductor layer is etched away when drain electrode etching, effectively avoids barrier layer from being thinned.So as to avoid two
Dimensional electron gas concentration reduces, and then the conducting resistance of the HEMT device is effectively reduced.
Each embodiment in this specification is described in a progressive manner, the same or similar portion between each embodiment
Dividing may refer to each other, and each embodiment focuses on the differences from other embodiments.
Although depicting the application by embodiment, it will be appreciated by the skilled addressee that the application there are many deformation and
Variation is without departing from spirit herein, it is desirable to which the attached claims include these deformations and change without departing from the application's
Spirit.
Claims (8)
1. a kind of normally-off gallium nitride HEMT device, including heterojunction structure and the source electrode being connect with the heterojunction structure, drain electrode and
Grid, which is characterized in that the heterojunction structure includes:
The first semiconductor layer as channel layer and the second semiconductor layer as barrier layer, second semiconductor layer are formed in
On first semiconductor layer, two-dimensional electron gas is formed between first semiconductor layer and second semiconductor layer；
It is formed with semiconductor insert layer on second semiconductor layer, is formed with p-type semiconductor layer in the semiconductor insert layer,
The upper surface of the p-type semiconductor layer is arranged in the grid, in electrical contact with the p-type semiconductor layer；
The source electrode and the drain electrode are formed in the semiconductor across p-type semiconductor layer deposition and are inserted by etching technics
Enter the upper surface of layer.
2. a kind of normally-off gallium nitride HEMT device as described in claim 1, which is characterized in that the semiconductor insert layer
Composition material includes AlN, AlxGa(1-x)The combination of any one or two kinds in N, wherein x > 30%；
The etching selection ratio of the semiconductor insert layer and second semiconductor layer, be greater than the p-type semiconductor layer with it is described
The etching selection ratio of second semiconductor layer.
3. a kind of normally-off gallium nitride HEMT device as claimed in claim 1 or 2, which is characterized in that the semiconductor insertion
The thickness of layer is more than or equal to 0.5 nanometer and is less than or equal to 3 nanometers.
4. a kind of normally-off gallium nitride HEMT device as described in claim 1, which is characterized in that the group of the p-type semiconductor
It is p-type gallium nitride at material, the thickness of the p-type semiconductor is more than or equal to 50 nanometers and is less than or equal to 150 nanometers.
5. a kind of normally-off gallium nitride HEMT device as described in claim 1, which is characterized in that first semiconductor layer
Composition material is gallium nitride, and the thickness of first semiconductor layer is more than or equal to 50 nanometers and is less than or equal to 350 nanometers.
6. a kind of normally-off gallium nitride HEMT device as described in claim 1, which is characterized in that second semiconductor layer
Composition material is AlxGa(1-x)N, the thickness of second semiconductor layer are more than or equal to 10 nanometers and less than or equal to 30 nanometers,
In, 10%≤x≤30%.
7. a kind of normally-off gallium nitride HEMT device as described in claim 1, which is characterized in that the device further includes lining
Buffer layer is distributed between the substrate and first semiconductor layer in bottom.
8. a kind of normally-off gallium nitride HEMT device as claimed in claim 7, which is characterized in that the composition material of the substrate
Including any one or the two or more combinations in silicon, sapphire, silicon carbide, gallium nitride, aluminium nitride, the group of the buffer layer
It include gallium nitride or aluminium gallium nitride alloy at material.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201820833002.2U CN208781852U (en) | 2018-05-31 | 2018-05-31 | A kind of normally-off gallium nitride HEMT device |
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| CN201820833002.2U CN208781852U (en) | 2018-05-31 | 2018-05-31 | A kind of normally-off gallium nitride HEMT device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108649065A (en) * | 2018-05-31 | 2018-10-12 | 江苏能华微电子科技发展有限公司 | A kind of normally-off gallium nitride HEMT device and preparation method thereof |
| WO2021142823A1 (en) * | 2020-01-19 | 2021-07-22 | 中国科学院半导体研究所 | Gan-based normally-off high-electron-mobility transistor and preparation method therefor |
| CN116631960A (en) * | 2023-05-15 | 2023-08-22 | 江苏能华微电子科技发展有限公司 | GaN HEMT device manufacturing method and GaN HEMT device |
-
2018
- 2018-05-31 CN CN201820833002.2U patent/CN208781852U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108649065A (en) * | 2018-05-31 | 2018-10-12 | 江苏能华微电子科技发展有限公司 | A kind of normally-off gallium nitride HEMT device and preparation method thereof |
| WO2021142823A1 (en) * | 2020-01-19 | 2021-07-22 | 中国科学院半导体研究所 | Gan-based normally-off high-electron-mobility transistor and preparation method therefor |
| CN116631960A (en) * | 2023-05-15 | 2023-08-22 | 江苏能华微电子科技发展有限公司 | GaN HEMT device manufacturing method and GaN HEMT device |
| CN116631960B (en) * | 2023-05-15 | 2024-04-05 | 江苏能华微电子科技发展有限公司 | GaN HEMT device manufacturing method and GaN HEMT device |
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