CN104409480B - Insulated gate type right-angled source field plate device with high electron mobility and manufacturing method thereof - Google Patents
Insulated gate type right-angled source field plate device with high electron mobility and manufacturing method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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Abstract
The invention discloses an insulated gate type right-angled source field plate device with high electron mobility and a manufacturing method thereof and mainly solves a problem that the process for realizing high breakdown voltage is complex in the present field plate technique. The insulated gate type right-angled source field plate device with high electron mobility comprises a substrate (1), a transition layer (2), a barrier layer (3), an insulated medium layer (7), a passivation layer (9) and a protective layer (12); a source electrode (4) and a drain electrode (5) are deposited on the barrier layer; a table top (6) is formed on the lateral side of the barrier layer; an insulated gate electrode (8) is deposited on the insulated medium layer; a groove (10) is etched in the passivation layer; a right-angled source field plate (10) is deposited between the passivation layer and the protective layer; the edge of the right-angled source field plate (11) close to one side of the insulated gate electrode aligns with that of the groove close to one side of the insulated gate electrode; the right-angled source field plate is electrically connected with the source electrode (4) and the lower end is completely filled in the groove (10). The insulated gate type right-angled source field plate device with high electron mobility has the advantages of simple manufacturing process, good forward characteristics and reverse characteristics and high rate of finished products.
Description
Technical field
The invention belongs to microelectronics technology, is related to the high electricity of semiconductor device, particularly insulated-gate type right angle source field plate
Transport factor device, can be used as the basic device of power electronic system.
Technical background
Power semiconductor is the critical elements of power electronic system, is to carry out electric treatable effective tool.In recent years
Come, with becoming increasingly conspicuous for the energy and environmental problem, research and development novel high-performance, low-loss power device become raising electric energy profit
With one of rate, energy saving, the effective way of alleviating energy crisis.However, in power device research, at a high speed, high pressure with it is low
Serious restricting relation is there is between conducting resistance, rationally, to effectively improve this restricting relation be to improve device globality
The key of energy.As market constantly proposes the requirement of higher efficiency, smaller volume, higher frequency, traditional Si base to power system
Semiconductor power device performance has approached its theoretical limit.In order to be able to further reducing chip area, improving operating frequency, improve
Operating temperature, reduction conducting resistance, raising breakdown voltage, reduction machine volume, raising overall efficiency, with gallium nitride as representative
Semiconductor material with wide forbidden band, drifts about by the electronics saturation of its bigger energy gap, higher critical breakdown electric field and Geng Gao
Speed, and the outstanding advantages such as stable chemical performance, high temperature resistant, radioprotective, show one's talent in terms of high performance power device is prepared,
Application potential is huge.Especially with the HEMT of GaN base heterojunction structure, i.e. GaN base HEMT device, more
It is, because of characteristics such as its low on-resistance, senior engineer's working frequencies, electronics of future generation to be met more high-power to power device, higher
The requirement of frequency, smaller volume and more severe hot operation, has wide and special application prospect in economy and military field.
However, there is inherent shortcoming in conventional GaN base HEMT device structure, device channel electric field intensity can be caused in deformity
, especially there is high peak electric field near vicinity in device grids in distribution.Cause hitting for actual GaN base HEMT device
Voltage is worn often far below theoretical eapectation, and there is the integrity problems such as current collapse, inverse piezoelectric effect, seriously constrain
Application and development in field of power electronics.In order to solve problem above, domestic and international researchers propose numerous methods, and field
Hardened structure be wherein effect significantly, one kind for being most widely used.N.Q.Zhang of U.S. UCSB in 2000 et al. is first
Field plate structure is successfully applied in GaN base HEMT power device, overlapping gate device is developed, saturation output current is 500mA/
Mm, up to 570V, this is reported breakdown voltage highest GaN device at that time to breakdown voltage, referring to High
breakdown GaN HEMT with overlapping gate structure,IEEE Electron Device
Letters,Vol.21,No.9,pp.421-423,2000.Subsequently, research institution of various countries expands one after another the research work of correlation
Make, and the U.S. and Japan are the main leaders in the field.In the U.S., mainly UCSB, Nan Ka university, Cornell University with
And famous IR companies of power electronic devices manufacturer etc. are engaged in the research.Japan is relative to start late, but they are to this side
The work in face is paid much attention to, fund input great efforts, and it is numerous to be engaged in mechanism, including：Toshiba, Furukawa, Panasonic, Toyota and Fuji etc.
Major company.With going deep into for research, researchers have found correspondingly to increase field plate length, can improve device electric breakdown strength.But
The increase of field plate length can make field plate efficiency, i.e. breakdown voltage than field plate length, constantly reduce, that is, field plate improves device and hits
The ability of voltage is worn as the increase of field plate length gradually tends to saturation, referring to Enhancement of breakdown
voltage in AlGaN/GaN high electron mobility transistors using a field plate,
IEEE Transactions on Electron Devices, Vol.48, No.8, pp.1515-1521,2001, and
Development and characteristic analysis of a field-plated Al2O3/AlInN/GaN MOS
HEMT,Chinese Physics B,Vol.20,No.1,pp.0172031-0172035,2011.Therefore, in order to further carry
High device electric breakdown strength, while taking into account field plate efficiency, H.L.Xing of UCSB in 2004 et al. proposes a kind of double-deck field plate knot
Structure, the double-layer grid field plate GaN base HEMT device that they develop can obtain the up to breakdown voltage of 900V, maximum output current
700mA/mm, referring to High breakdown voltage AlGaN-GaN HEMTs achieved by multiple
field plates,IEEE Electron Device Letters,Vol.25,No.4,pp.161-163,2004.It is this double
Layer field plate structure has become current in the world for improving GaN base power device breakdown characteristics, improves the master of device overall performance
Flow field plate technique.However, the complex process of GaN base bilayer field plate HEMT device, manufacturing cost is higher, the making of each layer of field plate
It is required for the processing steps such as photoetching, deposit metal, deposit dielectric passivation.And to optimize under each layer field plate dielectric material thickness with
Realize that breakdown voltage is maximized, it is necessary to carry out loaded down with trivial details process debugging and optimization, therefore considerably increase the difficulty of device manufacture,
Reduce the yield rate of device.
The content of the invention
Present invention aims to the deficiency of above-mentioned prior art, there is provided a kind of manufacturing process is simple, breakdown voltage
High insulated-gate type right angle source field plate device with high electron mobility of high, field plate efficiency high and reliability and preparation method thereof, to subtract
The manufacture difficulty of gadget, improves the breakdown characteristics and reliability of device, improves the yield rate of device.
For achieving the above object, the technical scheme is that what is be achieved in that：
First, device architecture
The heterojunction structure that the device architecture that the present invention is provided is constituted using GaN base semiconductor material with wide forbidden band, from lower
On include：Substrate, transition zone, barrier layer, insulating medium layer, passivation layer and protective layer, are deposited with source electrode, leakage above barrier layer
Table top is carved with pole, the side of barrier layer, and land depth is more than barrier layer thickness, and insulating medium layer is deposited over insulated gate electrode.
Characterized in that, being carved with groove in passivation layer, right angle source field plate is deposited between passivation layer and protective layer, right angle source field plate is close
With groove near the side edge-justified calibrations of insulated gate electrode one, the right angle source field plate is electrically connected the lateral edges of insulated gate electrode one with source electrode, and
Lower end is completely filled in groove.
Preferably, described depth of groove s is 0.22～9.3 μm, width b is 0.55～7.7 μm.
Preferably, the distance between described bottom portion of groove and insulating medium layer d is 0.078～0.57 μm.
Preferably, the thickness e of described insulating medium layer is 3～87nm.
Preferably, described right angle source field plate is between one lateral edges of drain electrode and groove one lateral edges of close drain electrode
It it is 0.74～9.3 μm apart from c.
Preferably, described groove is between the lateral edges of insulated gate electrode one and insulated gate electrode one lateral edges of close drain electrode
Apart from a be s × (d+e × ε2/ε1)0.5, wherein s is depth of groove, and d is the distance between bottom portion of groove and insulating medium layer, e
For the thickness of insulating medium layer, ε2For the relative dielectric constant of passivation layer, ε1For the relative dielectric constant of insulating medium layer.
Two. manufacture method
The method that the present invention makes insulated-gate type right angle source field plate device with high electron mobility, including following process：
(1) the extension GaN base semiconductor material with wide forbidden band on substrate, forms transition zone；
(2) the extension GaN base semiconductor material with wide forbidden band on transition zone, forms barrier layer；
(3) make mask for the first time on barrier layer, metal is deposited at the two ends of barrier layer using the mask, then in N2Gas
Rapid thermal annealing is carried out in atmosphere, source electrode and drain electrode are made respectively；
(4) second making mask on barrier layer, enterprising using barrier layer of the mask on the left of source electrode, on the right side of drain electrode
Row etching, and etched area depth is more than barrier layer thickness, forms table top；
(5) the barrier layer top deposition thickness e on source electrode top, drain electrode top and between source electrode and drain electrode be 3～
The insulating dielectric materials of 87nm, make insulating medium layer；
(6) mask is made for the third time on insulating medium layer, the dielectric using the mask between source electrode and drain electrode
Metal is deposited on layer, insulated gate electrode is made；
(7) respectively in insulated gate electrode top and other area top deposit passivation layers of insulating medium layer；
(8) mask is made the 4th time over the passivation layer, in the passivation layer using the mask between insulated gate electrode and drain electrode
Perform etching, to make depth s as 0.22～9.3 μm, width b is 0.55～7.7 μm of groove, bottom portion of groove and dielectric
The distance between layer d is 0.078～0.57 μm；The groove is near the lateral edges of insulated gate electrode one and insulated gate electrode near drain electrode side
The distance between edge a is s × (d+e × ε2/ε1)0.5, wherein s is depth of groove, and d is between bottom portion of groove and insulating medium layer
Distance, e for insulating medium layer thickness, ε2For the relative dielectric constant of passivation layer, ε1Relative dielectric for insulating medium layer is normal
Number；
(9) mask is made the 5th time over the passivation layer, using passivation of the mask in groove and source electrode and drain electrode between
Metal is deposited on layer, the metal for being deposited will be filled up completely with groove, and the metal is close near the lateral edges of insulated gate electrode one and groove
The side edge-justified calibrations of insulated gate electrode one, form the right angle source field plate that thickness is 0.22～9.3 μm, and right angle source field plate and source electrode is electric
Gas connects, and right angle source field plate is 0.74～9.3 near the distance between one lateral edges of drain electrode c with groove near one lateral edges of drain electrode
μm；
(10) in right angle source field plate top and other area top deposit insulating dielectric materials of passivation layer, protection is formed
Layer, completes the making of whole device.
Device of the present invention with compared with advantages below using the device with high electron mobility of conventional source field plate：
1. breakdown voltage is further increased.
The present invention is due to using right angle source field plate structure, making device in the in running order work for being particularly in OFF state
During state, barrier layer surface potential gradually rises from insulated gate electrode to drain electrode, so as to increased barrier layer in depletion region, i.e. high resistant
Area, area, improve the distribution of depletion region, promote the depletion region between insulated gate electrode and drain electrode in barrier layer to undertake bigger
Drain-source voltage, so as to substantially increase the breakdown voltage of device.
2. insulated gate electrode leakage current is further reduced, device reliability is improve.
The present invention is because using right angle source field plate structure, the distribution for making electric field line in device barrier layer depletion region has been obtained more
Effectively modulation, insulated gate electrode is near one lateral edges of drain electrode, right angle source field plate one lateral edges of close drain electrode and groove in device
Can all produce a peak electric field near one lateral edges of drain electrode, and by adjust right angle source field plate underlying passivation layer thickness,
Depth of groove and width, right angle source field plate near one lateral edges of drain electrode and groove near drain the distance between lateral edges and
Groove near the lateral edges of insulated gate electrode one and insulated gate electrode near the distance between one lateral edges of drain electrode, can cause it is above-mentioned each
Peak electric field is equal and less than the breakdown electric field of GaN base semiconductor material with wide forbidden band, so as to reduce insulated gate to greatest extent
Electric field line collected by the edge of extremely close drain electrode side, significantly reduces the electric field at this, substantially reduces insulated gate electrode
Leakage current so that the reliability and breakdown characteristics of device is significantly increased.
3. process is simple, it is easy to accomplish, improve yield rate.
The making of right angle source field plate in device architecture of the present invention only needs a step process just can complete, it is to avoid traditional stack layers
The process complications problem that field plate structure is brought, substantially increases the yield rate of device.
Simulation result shows that the breakdown voltage of device of the present invention is far longer than the high electron mobility using conventional source field plate
The breakdown voltage of device.
The technology contents and effect of the present invention are further illustrated below in conjunction with drawings and Examples.
Description of the drawings
Fig. 1 is the structure chart using the device with high electron mobility of conventional source field plate；
Fig. 2 is the structure chart of insulated-gate type right angle of the present invention source field plate device with high electron mobility；
Fig. 3 is the flow chart that the present invention makes insulated-gate type right angle source field plate device with high electron mobility；
Fig. 4 is to electric field curve diagram in the barrier layer obtained by traditional devices and device simulation of the present invention；
Fig. 5 is to puncturing curve chart obtained by traditional devices and device simulation of the present invention.
Specific embodiment
With reference to Fig. 2, insulated-gate type right angle of the present invention source field plate device with high electron mobility is partly led based on GaN base broad stopband
Bulk heterojunction structure, it includes：Substrate 1, transition zone 2, barrier layer 3, source electrode 4, drain electrode 5, table top 6, insulating medium layer 7, insulation
Grid 8, passivation layer 9, groove 10, right angle source field plate 11 and protective layer 12.Substrate 1, transition zone 2 are with barrier layer 3 for from bottom to top
Distribution, source electrode 4 and drain electrode 5 are deposited on barrier layer 3, and table top 6 is located at the left side of source electrode and the right side of drain electrode, and the land depth is big
In barrier layer thickness, insulating medium layer 7 is respectively overlay in source electrode top, drain electrode top and the barrier layer between source electrode and drain electrode
Top, the thickness e of insulating medium layer is 3～87nm, and insulated gate electrode 8 is deposited on the insulating medium layer 7 between source electrode and drain electrode；
Passivation layer 9 is located at the top on insulated gate electrode top and other regions of insulating medium layer.Groove 10 is located in passivation layer 9, the groove
Depth s is 0.22～9.3 μm, and width b is 0.55～7.7 μm, and the distance between bottom portion of groove and insulating medium layer d is 0.078
～0.57 μm；Groove is near the lateral edges of insulated gate electrode one and insulated gate electrode near the distance between one lateral edges of drain electrode a, groove depth
The thickness e of the distance between degree s, bottom portion of groove and insulating medium layer d and insulating medium layer meet relation a=s × (d+e ×
ε2/ε1)0.5, wherein ε2For the relative dielectric constant of passivation layer, ε1For the relative dielectric constant of insulating medium layer.Right angle source field plate
11 are deposited between passivation layer 9 and protective layer 12, and right angle source field plate is near the lateral edges of insulated gate electrode one and groove near insulated gate
The side edge-justified calibrations of pole one, the right angle source field plate is electrically connected with source electrode 4, and the lower end of right angle source field plate 11 is filled up completely with groove
10.Right angle source field plate is 0.74～9.3 μm near the distance between one lateral edges of drain electrode c with groove near one lateral edges of drain electrode.
Protective layer 12 is located at other area tops of the top of right angle source field plate 11 and passivation layer 9.
The substrate 1 of above-mentioned device is using sapphire or carborundum or silicon materials；If transition zone 2 is identical or different by dried layer
GaN base semiconductor material with wide forbidden band is constituted, and its thickness is 1～5 μm；If barrier layer 3 is prohibited by the identical or different GaN base width of dried layer
Carrying semiconductor material is constituted, and its thickness is 5～50nm；Insulating medium layer 7, passivation layer 9 can adopt SiO with protective layer 122、
SiN、Al2O3、Sc2O3、HfO2、TiO2In any one or other insulating dielectric materials, the thickness of passivation layer 9 is depth of groove
The distance between s and bottom portion of groove and insulating medium layer d sums, i.e., 0.298～9.87 μm；The thickness of protective layer 12 be 0.26～
5.6μm；Right angle source field plate 11 is constituted using the combination of three layers of different metal, and its thickness is 0.22～9.3 μm.
With reference to Fig. 3, the present invention makes the process of insulated-gate type right angle source field plate device with high electron mobility, provides following three
Plant embodiment：
Embodiment one：Making substrate is sapphire, and insulating medium layer is HfO2, passivation layer is SiN, and protective layer is SiO2, directly
Angle source field plate is the insulated-gate type right angle source field plate device with high electron mobility of Ti/Mo/Au metallic combinations.
From bottom to top extension GaN material makes transition zone 2, such as Fig. 3 a to step 1. in Sapphire Substrate 1.
Using metal organic chemical vapor deposition technology, epitaxial thickness is 1 μm of undoped p mistake in Sapphire Substrate 1
Layer 2 is crossed, the transition zone is respectively from bottom to top 30nm and 0.97 μm of GaN material by thickness and is constituted.Extension lower floor GaN material is adopted
Process conditions are：Temperature is 530 DEG C, and pressure is 45Torr, and hydrogen flowing quantity is 4400sccm, and ammonia flow is
4400sccm, gallium source flux is 22 μm of ol/min；The process conditions that extension upper strata GaN material is adopted for：Temperature is 960 DEG C, pressure
It is by force 45Torr, hydrogen flowing quantity is 4400sccm, and ammonia flow is 4400sccm, and gallium source flux is 120 μm of ol/min.
Step 2. deposits unadulterated Al in GaN transition layer 20.5Ga0.5N makes barrier layer 3, such as Fig. 3 b.
Using metal organic chemical vapor deposition technology, deposition thickness is 5nm in GaN transition layer 2, and al composition is
0.5 undoped p Al0.5Ga0.5N barrier layers 3, the process conditions that it is adopted for：Temperature is 980 DEG C, and pressure is 45Torr, hydrogen
Flow is 4400sccm, and ammonia flow is 4400sccm, and gallium source flux is 35 μm of ol/min, and silicon source flow is 7 μm of ol/min.
Step 3. makes source electrode 4 and drain electrode 5, such as Fig. 3 c in the two ends deposit metal Ti/Al/Ni/Au of barrier layer 3.
In Al0.5Ga0.5Mask is made on N barrier layers 3 for the first time, using electron beam evaporation technique in its two ends deposit gold
Category, then in N2Rapid thermal annealing is carried out in atmosphere, source electrode 4 and drain electrode 5 is made, wherein the metal for being deposited is Ti/Al/Ni/Au
Metallic combination, i.e., be respectively from bottom to top Ti, Al, Ni and Au, and its thickness is 0.018 μm/0.135 μm/0.046 μm/0.052 μ
m.That is the thickness of Ti, Al, Ni and Au is respectively 0.018 μm, 0.135 μm, 0.046 μm and 0.052 μm.The work that deposit metal is adopted
Skill condition is：Vacuum is less than 1.8 × 10-3Pa, power bracket is 200～1000W, and evaporation rate is less thanFast speed heat is moved back
The process conditions that adopt of fire for：Temperature is 850 DEG C, and the time is 35s.
Step 4. performs etching making table top 6, such as Fig. 3 d on the barrier layer on the right of the source electrode left side with drain electrode.
In Al0.5Ga0.5Second making mask on N barrier layers 3, using reactive ion etching technology in the source electrode left side and leakage
Perform etching on the barrier layer on ultra-Right side, form table top 6, etching depth is 10nm.The process conditions that adopt of etching for：Cl2Stream
Measure as 15sccm, pressure is 10mTorr, and power is 100W.
Barrier layer top deposit HfO of the step 5. on the top of source electrode 4,5 tops of drain electrode and between source electrode and drain electrode2Make
Insulating medium layer 7, such as Fig. 3 e.
Using superconducting RF technology in the top of source electrode 4,5 tops of drain electrode and the potential barrier between source electrode and drain electrode
Layer top deposition thickness e is the HfO of 3nm2, make insulating medium layer 7.The process conditions that adopt of deposit insulating medium layer for：Instead
Room sputtering pressure is answered to be maintained at 0.1Pa or so, O21sccm and 8sccm are respectively with the flow of Ar, substrate temperature is fixed on 200
DEG C, Hf targets radio-frequency power is 150W.
W metal/Au is deposited on insulating medium layer 7 of the step 6. between source electrode and drain electrode and makes insulated gate electrode 8, such as schemed
3f。
Make mask for the third time on insulating medium layer 7, it is exhausted between source electrode and drain electrode using electron beam evaporation technique
On edge dielectric layer 7 deposit metal make insulated gate electrode 8, wherein the metal for being deposited be Ni/Au metallic combinations, i.e. lower floor be Ni,
Upper strata is Au, and its thickness is 0.043 μm/and the thickness of 0.25 μm, i.e. Ni and Au is respectively 0.043 μm with 0.25 μm.Deposit metal
The process conditions for adopting for：Vacuum is less than 1.8 × 10-3Pa, power bracket is 200～1000W, and evaporation rate is less than
Step 7. makes passivation layer 9 in other area tops deposit SiN of insulated gate electrode top and insulating medium layer 7, such as
Fig. 3 g.
Its of insulated gate electrode top and insulating medium layer is covered each by using plasma enhanced CVD technology
His area top, completes the SiN passivation layers 9 that deposition thickness is 0.298 μm.The process conditions that adopt of deposit passivation layer for：Gas
For NH3、N2And SiH4, gas flow is respectively 2.5sccm, 950sccm and 250sccm, and temperature, RF power and pressure are respectively
300 DEG C, 25W and 950mTorr.
Step 8. performs etching making groove 10, such as Fig. 3 h in the passivation layer between insulated gate electrode 8 and drain electrode 5.
The 4th making mask on passivation layer 9, using reactive ion etching technology between insulated gate electrode 8 and drain electrode 5
Passivation layer in perform etching, to make groove 10, wherein depth of groove s is 0.22 μm, and width b is 0.55 μm, bottom portion of groove
It it is 0.078 μm with the distance between insulating medium layer d, groove is near the lateral edges of insulated gate electrode one and insulated gate electrode near drain electrode one
The distance between lateral edges a is 0.062 μm.The process conditions that adopt of etching for：CF4Flow is 45sccm, O2Flow is 5sccm,
Pressure is 15mTorr, and power is 250W.
Step 9. deposits metal Ti/Mo/Au and makes right angle source on the passivation layer in groove and between source electrode 4 and drain electrode 5
Field plate 11, such as Fig. 3 i.
On passivation layer 9 the 5th time making mask, using electron beam evaporation technique in groove and source electrode 4 with drain 5 it
Between passivation layer on deposit metal, wherein deposited metal will be filled up completely with groove 10, the metal is near the side of insulated gate electrode one
Edge, near the side edge-justified calibrations of insulated gate electrode one, forms right angle source field plate with groove, and right angle source field plate and source electrode are electrically connected.
The metal for being deposited be Ti/Mo/Au metallic combinations, i.e. lower floor be Ti, middle level be Mo, upper strata be Au, its thickness be 0.1 μm/
0.08 μm/the thickness of 0.04 μm, i.e. Ti, Mo and Au be respectively 0.1 μm, 0.08 μm with 0.04 μm.Right angle source field plate 11 is near leakage
The lateral edges of pole one are 0.74 μm near the distance between one lateral edges of drain electrode c with groove 10.The process conditions that deposit metal is adopted
For：Vacuum is less than 1.8 × 10-3Pa, power bracket is 200～1000W, and evaporation rate is less than
Step 10. is in the top of right angle source field plate 11 and other area tops deposit SiO of passivation layer 92Make protective layer
12, such as Fig. 3 j.
Using plasma enhanced CVD technology in the top of right angle source field plate 11 and other areas of passivation layer 9
Domain top deposits SiO2Protective layer 12 is made, its thickness is 0.26 μm, so as to complete the making of whole device, deposit protective layer is adopted
Process conditions are：N2O flows are 850sccm, SiH4Flow is 200sccm, and temperature is 250 DEG C, and RF power is 25W, pressure
For 1100mTorr.
Embodiment two：Making substrate is carborundum, and insulating medium layer is Al2O3, passivation layer is SiO2, protective layer is SiN,
Right angle source field plate is the insulated-gate type right angle source field plate device with high electron mobility of Ti/Ni/Au metallic combinations.
Step one. from bottom to top extension AlN makes transition zone 2, such as Fig. 3 a with GaN material in silicon carbide substrates 1.
1.1) using metal organic chemical vapor deposition technology, epitaxial thickness is not mixing for 50nm in silicon carbide substrates 1
Miscellaneous AlN materials；The process conditions of its extension are：Temperature is 1000 DEG C, and pressure is 45Torr, and hydrogen flowing quantity is 4600sccm,
Ammonia flow is 4600sccm, and silicon source flow is 5 μm of ol/min；
1.2) using metal organic chemical vapor deposition technology, epitaxial thickness is 2.45 μm of GaN materials on AlN materials
Material, completes the making of transition zone 2；The process conditions of its extension are：Temperature is 1000 DEG C, and pressure is 45Torr, and hydrogen flowing quantity is
4600sccm, ammonia flow is 4600sccm, and gallium source flux is 120 μm of ol/min.
The extension of this step is not limited to metal organic chemical vapor deposition technology, it would however also be possible to employ molecular beam epitaxy skill
Art or hydride gas-phase epitaxy technology.
Step 2. extension Al from bottom to top on transition zone 20.3Ga0.7N and GaN material make barrier layer 3, such as Fig. 3 b.
2.1) using metal organic chemical vapor deposition technology, deposition thickness is that 27nm, al composition are on transition zone 2
0.3 Al0.3Ga0.7N materials；The process conditions of its extension are：Temperature is 1100 DEG C, and pressure is 45Torr, and hydrogen flowing quantity is
4600sccm, ammonia flow is 4600sccm, and gallium source flux is 16 μm of ol/min, and silicon source flow is 8 μm of ol/min；
2.2) using metal organic chemical vapor deposition technology in Al0.3Ga0.7Epitaxial thickness is the GaN of 3nm on N materials
Material, completes the making of barrier layer 3；The process conditions of its extension are：Temperature is 1000 DEG C, and pressure is 47Torr, hydrogen flowing quantity
For 4700sccm, ammonia flow is 4700sccm, and gallium source flux is 11 μm of ol/min.
The extension of this step is not limited to metal organic chemical vapor deposition technology, it would however also be possible to employ molecular beam epitaxy skill
Art or hydride gas-phase epitaxy technology.
Step 3. make source electrode 4 and drain electrode 5, such as Fig. 3 c in the two ends deposit metal Ti/Al/Ni/Au of barrier layer 3.
3.1) mask is made for the first time on barrier layer 3, using electron beam evaporation technique in its two ends deposit metal, deposit
Metal be Ti/Al/Ni/Au metallic combinations, i.e., from bottom to top be respectively Ti, Al, Ni and Au, its thickness be 0.018 μm/
0.135 μm/0.046 μm/0.052 μm, its deposit smithcraft condition be：Vacuum is less than 1.8 × 10-3Pa, power bracket is
200～1000W, evaporation rate is less than
3.2) in N2Rapid thermal annealing is carried out in atmosphere, the making of source electrode 4 and drain electrode 5, the work of its rapid thermal annealing is completed
Skill condition is：Temperature is 850 DEG C, and the time is 35s.
The Metal deposition of this step is not limited to electron beam evaporation technique, it would however also be possible to employ sputtering technology.
Step 4. making table top 6, such as Fig. 3 d are performed etching on barrier layer 3 of the left side of source electrode with the right of drain electrode.
Second making mask on barrier layer 3, using reactive ion etching technology on the right of the source electrode left side with drain electrode
Perform etching on barrier layer 3, form table top 6, wherein etching depth is 100nm；Reactive ion etching technology etching table top 6 is adopted
Process conditions be：Cl2Flow is 15sccm, and pressure is 10mTorr, and power is 100W.
The etching of this step is not limited to reactive ion etching technology, it would however also be possible to employ sputtering technology or plasma etching
Technology.
Step 5. the barrier layer top deposit Al on source electrode top, drain electrode top and between source electrode and drain electrode2O3Make
Insulating medium layer 7, such as Fig. 3 e.
Formed sediment using barrier layer top of the atomic layer deposition technology on source electrode top, drain electrode top and between source electrode and drain electrode
Product thickness is the Al of 50nm2O3Insulating medium layer 7.The process conditions that adopt of deposit insulating medium layer for：With TMA and H2O is reaction
Source, carrier gas is N2, carrier gas flux is 200sccm, and underlayer temperature is 300 DEG C, and air pressure is 700Pa.
The deposit of the insulating medium layer of this step is not limited to atomic layer deposition technology, it would however also be possible to employ evaporation technique is waited
Gas ions strengthen chemical vapor deposition techniques or sputtering technology or molecular beam epitaxy technique.
Step 6. W metal/Au is deposited on the insulating medium layer 7 between source electrode and drain electrode and makes insulated gate electrode 8, such as schemed
3f。
Make mask for the third time on insulating medium layer 7, it is exhausted between source electrode and drain electrode using electron beam evaporation technique
Deposit metal on edge dielectric layer 7, make insulated gate electrode 8, wherein the metal for being deposited is Ni/Au metallic combinations, i.e. lower floor be Ni,
Upper strata is Au, and its thickness is 0.043 μm/0.25 μm；The electron beam evaporation technique process conditions that adopt of deposit Ni/Au for：Vacuum
Degree is less than 1.8 × 10-3Pa, power bracket is 200～1000W, and evaporation rate is less than
The Metal deposition of this step is not limited to electron beam evaporation technique, it would however also be possible to employ sputtering technology.
Step 7. in insulated gate electrode top and other area tops deposit SiO of insulating medium layer2Passivation layer 9 is made, such as
Fig. 3 g.
Its of insulated gate electrode top and insulating medium layer is covered each by using plasma enhanced CVD technology
His area top, completes the SiO that deposition thickness is 6.3 μm2Passivation layer 9；The process conditions that it is adopted for：N2O flows are
850sccm, SiH4Flow is 200sccm, and temperature is 250 DEG C, and RF power is 25W, and pressure is 1100mTorr.
The deposit of the passivation layer of this step is not limited to plasma enhanced CVD technology, it would however also be possible to employ steam
Send out technology or atomic layer deposition technology or sputtering technology or molecular beam epitaxy technique.
Step 8. making groove 10, such as Fig. 3 h are performed etching in the passivation layer 9 between insulated gate electrode 8 and drain electrode 5.
The 4th making mask on passivation layer 9, using reactive ion etching technology between insulated gate electrode 8 and drain electrode 5
Passivation layer in perform etching, to make groove 10, wherein depth of groove s is 6 μm, and width b is 4 μm, bottom portion of groove and insulation
The distance between dielectric layer d is 0.3 μm, groove near the lateral edges of insulated gate electrode one and insulated gate electrode near one lateral edges of drain electrode it
Between apart from a be 3.403 μm；The process conditions that reactive ion etching technology etched recesses are adopted for：CF4Flow is 45sccm, O2
Flow is 5sccm, and pressure is 15mTorr, and power is 250W.
The etching of this step is not limited to reactive ion etching technology, it would however also be possible to employ sputtering technology or plasma etching
Technology.
Step 9. metal Ti/Ni/Au is deposited on the passivation layer 9 in groove and between source electrode 4 and drain electrode 5 and makes right angle
Source field plate 11, such as Fig. 3 i.
On passivation layer 9 the 5th time making mask, using electron beam evaporation technique in groove and source electrode 4 with drain 5 it
Between passivation layer on deposit metal, wherein deposited metal will be filled up completely with groove 10, the metal is near the side of insulated gate electrode one
Edge, near the side edge-justified calibrations of insulated gate electrode one, forms right angle source field plate 11 with groove, and right angle source field plate and source electrode are electrically connected
Connect.The metal for being deposited be Ti/Ni/Au metallic combinations, i.e. lower floor be Ti, middle level be Ni, upper strata be Au, its thickness be 3.9 μm/
1.6μm/0.5μm.One lateral edges of close drain electrode of right angle source field plate 11 and groove 10 are near the distance between one lateral edges of drain electrode c
6μm；The electron beam evaporation technique process conditions that adopt of deposit Ti/Ni/Au for：Vacuum is less than 1.8 × 10-3Pa, power bracket
For 200～1000W, evaporation rate is less than
The Metal deposition of this step is not limited to electron beam evaporation technique, it would however also be possible to employ sputtering technology.
Step 10. in right angle source, other area tops deposit SiN of the top of field plate 11 and passivation layer 9 makes protective layer
12, such as Fig. 3 j.
Using plasma enhanced CVD technology in the top of right angle source field plate 11 and other areas of passivation layer 9
Domain top deposit SiN makes protective layer 12, and its thickness is 3 μm, so as to complete the making of whole device；Its process conditions for adopting
For：Gas is NH3、N2And SiH4, gas flow is respectively 2.5sccm, 950sccm and 250sccm, temperature, RF power and pressure
Respectively 300 DEG C, 25W and 950mTorr.
The deposit of the protective layer of this step is not limited to plasma enhanced CVD technology, it would however also be possible to employ steam
Send out technology or atomic layer deposition technology or sputtering technology or molecular beam epitaxy technique.
Embodiment three：Making substrate is silicon, and insulating medium layer is Al2O3, passivation layer is HfO2, protective layer is SiN, right angle
Source field plate is the insulated-gate type right angle source field plate device with high electron mobility of Ti/Pt/Au metallic combinations.
From bottom to top extension AlN makes transition zone 2, such as Fig. 3 a to step A. with GaN material on silicon substrate 1.
A1 the use of metal organic chemical vapor deposition technology in temperature it is) 800 DEG C, pressure is 40Torr, hydrogen flowing quantity
For 4000sccm, ammonia flow is 4000sccm, and silicon source flow is under the process conditions of 25 μm of ol/min, on silicon substrate 1 outward
Prolong the AlN materials that thickness is 200nm；
A2 the use of metal organic chemical vapor deposition technology in temperature it is) 980 DEG C, pressure is 45Torr, hydrogen flowing quantity
For 4000sccm, ammonia flow is 4000sccm, and gallium source flux is under the process conditions of 120 μm of ol/min, on AlN materials outward
Prolong the GaN material that thickness is 4.8 μm, complete the making of transition zone 2.
Step B. deposits from bottom to top Al on transition zone0.1Ga0.9N makes barrier layer 3, such as Fig. 3 b with GaN material.
B1 the use of metal organic chemical vapor deposition technology in temperature it is) 1000 DEG C, pressure is 40Torr, hydrogen flowing quantity
For 4000sccm, ammonia flow is 4000sccm, and gallium source flux is 12 μm of ol/min, and silicon source flow is the technique of 12 μm of ol/min
Under the conditions of, epitaxial thickness is 46nm, the Al that al composition is 0.1 on transition zone 20.1Ga0.9N materials；
B2 the use of metal organic chemical vapor deposition technology in temperature it is) 1000 DEG C, pressure is 40Torr, hydrogen flowing quantity
For 4000sccm, ammonia flow is 4000sccm, and gallium source flux is under the process conditions of 3 μm of ol/min, in Al0.1Ga0.9N materials
Upper epitaxial thickness is the GaN material of 4nm, completes the making of barrier layer 3.
Step C. makes source electrode 4 and drain electrode 5, such as Fig. 3 c in the two ends of barrier layer 3 deposit metal Ti/Al/Ni/Au.
C1) make mask for the first time on barrier layer 3,1.8 × 10 are less than in vacuum using electron beam evaporation technique- 3Pa, power bracket is 200～1000W, and evaporation rate is less thanProcess conditions under, in its two ends deposit metal, wherein institute
The metal of deposit be Ti/Al/Ni/Au metallic combinations, i.e., from bottom to top be respectively Ti, Al, Ni and Au, its thickness be 0.018 μm/
0.135μm/0.046μm/0.052μm；
C2) in N2Atmosphere, temperature is 850 DEG C, and the time, to carry out rapid thermal annealing under the process conditions of 35s, completes source electrode 4
With the making of drain electrode 5.
Step D. performs etching making table top 6, such as Fig. 3 d on the barrier layer 3 on the right of the source electrode left side with drain electrode.
Second making mask on barrier layer 3, using reactive ion etching technology in Cl2Flow is 15sccm, pressure
For 10mTorr, under power is for the process conditions of 100W, perform etching on the barrier layer 3 on the right of the source electrode left side with drain electrode, formed
Table top 6, wherein etching depth are 200nm.
Barrier layer top deposit Al of step E. on source electrode top, drain electrode top and between source electrode and drain electrode2O3Make exhausted
Edge dielectric layer 7, such as Fig. 3 e.
Using atomic layer deposition technology with TMA and H2O is reaction source, and carrier gas is N2, carrier gas flux is 200sccm, substrate
Temperature is 300 DEG C, under air pressure is for the process conditions of 700Pa, in source electrode top, drain electrode top and the gesture between source electrode and drain electrode
Barrier layer top deposition thickness is the Al of 87nm2O3, make insulating medium layer 7.
W metal/Au is deposited on insulating medium layer 7 of step F. between source electrode and drain electrode and makes insulated gate electrode 8, such as schemed
3f。
Make mask for the third time on insulating medium layer 7,1.8 × 10 are less than in vacuum using electron beam evaporation technique- 3Pa, power bracket is 200～1000W, and evaporation rate is less thanProcess conditions under, the insulation between source electrode and drain electrode
Metal is deposited on dielectric layer 7, insulated gate electrode 8 is made, the metal for being deposited is that Ni/Au metallic combinations, i.e. lower floor are for Ni, upper strata
Au, its thickness is 0.043 μm/0.25 μm.
Step G. is in insulated gate electrode top and other area tops deposit HfO of insulating medium layer 72Material makes passivation layer
9, such as Fig. 3 g.
0.1Pa or so, O are maintained at using superconducting RF technology in reative cell sputtering pressure2With the flow of Ar
Respectively 1sccm and 8sccm, substrate temperature is fixed on 200 DEG C, under Hf targets radio-frequency power is for the process conditions of 150W, in insulation
Grid top deposits 9.87 μm of HfO with other area tops of insulating medium layer 72Material makes passivation layer 9.
Step H. performs etching making groove 10, such as Fig. 3 h in the passivation layer 9 between insulated gate electrode 8 and drain electrode 5.
The 4th making mask on passivation layer 9, using reactive ion etching technology in CF4Flow is 45sccm, O2Flow
For 5sccm, pressure is 15mTorr, under power is for the process conditions of 250W, in the passivation layer between insulated gate electrode 8 and drain electrode 5
Perform etching, to make groove 10, wherein depth of groove s is 9.3 μm, and width b is 7.7 μm, bottom portion of groove and insulating medium layer
The distance between d be 0.57 μm, groove is near the lateral edges of insulated gate electrode one and insulated gate electrode between one lateral edges of drain electrode
It it is 8.379 μm apart from a.
Step I. deposits metal Ti/Pt/Au on the passivation layer in groove and between source electrode 4 and drain electrode 5, makes right angle source
Field plate 11, such as Fig. 3 i.
The 5th making mask, 1.8 × 10 are less than using electron beam evaporation technique in vacuum on passivation layer 9-3Pa, work(
Rate scope is 200～1000W, and evaporation rate is less thanProcess conditions under, in groove and source electrode 4 and drain electrode 5 between
Metal is deposited on passivation layer, wherein deposited metal will be filled up completely with groove 10, the metal near the lateral edges of insulated gate electrode one with
Groove forms right angle source field plate 11 near the side edge-justified calibrations of insulated gate electrode one, and right angle source field plate and source electrode are electrically connected.Institute
The metal of deposit be thickness be Ti/Pt/Au metallic combinations, i.e. lower floor be Ti, middle level be Pt, upper strata be Au, its thickness be 5.7 μ
m/2.8μm/0.8μm.Right angle source field plate 11 is near one lateral edges of drain electrode with groove 10 near the distance between one lateral edges of drain electrode c
For 9.3 μm.
Step J. makes protective layer in the top of right angle source field plate 11 and other area tops deposit SiN of passivation layer 9
12, such as Fig. 3 j.
Using plasma enhanced CVD technology gas be NH3、N2And SiH4, gas flow is respectively
2.5sccm, 950sccm and 250sccm, temperature, RF power and pressure are respectively 300 DEG C, the process conditions of 25W and 950mTorr
Under, in right angle source, other area tops deposit SiN of the top of field plate 11 and passivation layer 9 makes protective layer 12, and its thickness is 5.6
μm, so as to complete the making of whole device.
The effect of the present invention can be further illustrated by following emulation.
Emulation 1：The barrier layer of barrier layer and device of the present invention to the device with high electron mobility using conventional source field plate
In electric field emulated, as a result such as Fig. 4, wherein conventional source field plate effective length L and the effective overall length of right angle source of the present invention field plate
Degree is equal.
As seen from Figure 4：Using electric field curve of the device with high electron mobility of conventional source field plate in barrier layer only
2 approximately equalised peak electric fields are defined, the area very little that its electric field curve in barrier layer is covered, and device of the present invention
Electric field curve of the part in barrier layer defines 3 approximately equalised peak electric fields so that device of the present invention is in barrier layer
The area that electric field curve is covered is greatly increased, because the area approximation that the electric field curve in barrier layer is covered is equal to device
Breakdown voltage, the breakdown voltage for illustrating device of the present invention is far longer than using the device with high electron mobility of conventional source field plate
Breakdown voltage.
Emulation 2：Device with high electron mobility using conventional source field plate is imitated with the breakdown characteristics of device of the present invention
Very, as a result such as Fig. 5.
As seen from Figure 5, punctured using the device with high electron mobility of conventional source field plate, i.e., drain current is rapid
Increase, when drain-source voltage about in 789V, and drain-source voltage of the device of the present invention when puncturing is about in 2920V, it was demonstrated that
The breakdown voltage of device of the present invention is far longer than the breakdown voltage of the device with high electron mobility using conventional source field plate, the conclusion
It is consistent with the conclusion of accompanying drawing 4.
For those skilled in the art, after present invention and principle has been understood, can be without departing substantially from this
In the case of bright principle and scope, the method according to the invention carries out various amendments and change in form and details, but
These amendments and change based on the present invention are still within the claims of the present invention.
Claims (7)
1. a kind of insulated-gate type right angle source field plate device with high electron mobility, includes from bottom to top：Substrate (1), transition zone (2),
Barrier layer (3), insulating medium layer (7), passivation layer (9) and protective layer (12), are deposited with source electrode (4), leakage above barrier layer (3)
Table top (6) is carved with pole (5), the side of barrier layer (3), and land depth is more than barrier layer thickness, and insulating medium layer (7) is deposited over
There is insulated gate electrode (8), it is characterised in that be carved with groove (10) in passivation layer (9), form sediment between passivation layer (9) and protective layer (12)
Product has right angle source field plate (11), and right angle source field plate (11) is near the lateral edges of insulated gate electrode one with groove (10) near insulated gate electrode one
Side edge-justified calibrations, the right angle source field plate is electrically connected with source electrode (4), and lower end is completely filled in groove (10)；
The groove (10) is near the lateral edges of insulated gate electrode one with insulated gate electrode (8) near the distance between one lateral edges of drain electrode a
For s × (d+e × ε2/ε1)0.5, wherein s is depth of groove, and d is the distance between bottom portion of groove and insulating medium layer, and e is insulation
The thickness of dielectric layer, ε2For the relative dielectric constant of passivation layer, ε1For the relative dielectric constant of insulating medium layer；Groove is near leakage
The lateral edges of pole one are 0.74～9.3 μm near the distance between one lateral edges of drain electrode c with right angle source field plate.
2. insulated-gate type right angle according to claim 1 source field plate device with high electron mobility, it is characterised in that groove
(10) depth s is 0.22～9.3 μm, and width b is 0.55～7.7 μm；Between groove (10) bottom and insulating medium layer (7)
It it is 0.078～0.57 μm apart from d；The thickness e of insulating medium layer (7) is 3～87nm.
3. insulated-gate type right angle according to claim 1 source field plate device with high electron mobility, it is characterised in that substrate (1)
Using sapphire or carborundum or silicon materials.
4. a kind of method for making insulated-gate type right angle source field plate device with high electron mobility, including following process：
1) the extension GaN base semiconductor material with wide forbidden band on substrate (1), forms transition zone (2)；
2) the extension GaN base semiconductor material with wide forbidden band on transition zone, forms barrier layer (3)；
3) mask is made for the first time on barrier layer (3), metal is deposited at the two ends of barrier layer (3) using the mask, then in N2Gas
Rapid thermal annealing is carried out in atmosphere, source electrode (4) and drain electrode (5) are made respectively；
4) second mask is made on barrier layer (3), using carrying out on barrier layer of the mask on the left of source electrode, on the right side of drain electrode
Etching, and etched area depth is more than barrier layer thickness, forms table top (6)；
5) the barrier layer top deposition thickness e on source electrode top, drain electrode top and between source electrode and drain electrode is the exhausted of 3～87nm
Edge dielectric material, makes insulating medium layer (7)；
6) mask is made for the third time on insulating medium layer (7), the insulating medium layer using the mask between source electrode and drain electrode
Upper deposit metal, makes insulated gate electrode (8)；
7) respectively in insulated gate electrode top and other area tops deposit passivation layer (9) of insulating medium layer；
8) the 4th making mask on passivation layer (9), in the passivation layer (9) using the mask between insulated gate electrode and drain electrode
Perform etching, to make depth s as 0.22～9.3 μm, width b is 0.55～7.7 μm of groove (10), groove (10) bottom with
The distance between insulating medium layer (7) d is 0.078～0.57 μm；The groove is near the lateral edges of insulated gate electrode one and insulated gate electrode
It is s × (d+e × ε near the distance between one lateral edges of drain electrode a2/ε1)0.5, wherein s be depth of groove, d be bottom portion of groove with it is exhausted
The distance between edge dielectric layer, e for insulating medium layer thickness, ε2For the relative dielectric constant of passivation layer, ε1For insulating medium layer
Relative dielectric constant；
9) the 5th making mask on passivation layer (9), using passivation layer of the mask in groove and source electrode and drain electrode between
Upper deposit metal, depositing metal will be filled up completely with groove, and the metal is near the lateral edges of insulated gate electrode one and groove near insulation
The side edge-justified calibrations of grid one, form right angle source field plate (11) that thickness is 0.22～9.3 μm, and by right angle source field plate (11) and source
Pole (4) is electrically connected, and right angle source field plate is near the distance between one lateral edges of drain electrode c with groove near one lateral edges of drain electrode
0.74～9.3 μm；
10) in right angle source field plate (11) top and other area top deposit insulating dielectric materials of passivation layer (9), protection is formed
Layer (12), completes the making of whole device.
5. method according to claim 4, it is characterised in that is 9) blunt and source electrode and drain electrode between in groove in step
It is Ti that the metal deposited on change layer adopts three-layer metal combination Ti/Mo/Au, i.e. lower floor, middle level is Mo, upper strata is Au, its thickness
Spend for 0.1～5.7 μm/0.08～2.8 μm/0.04～0.8 μm.
6. method according to claim 4, it is characterised in that is 9) blunt and source electrode and drain electrode between in groove in step
Change the metal that deposited on layer to combine using Ti/Ni/Au three-layer metals, i.e., lower floor be Ti, middle level be Ni, upper strata be Au, its thickness
Spend for 0.1～5.7 μm/0.08～2.8 μm/0.04～0.8 μm.
7. method according to claim 4, it is characterised in that is 9) blunt and source electrode and drain electrode between in groove in step
Change the metal that deposited on layer to combine using Ti/Pt/Au three-layer metals, i.e., lower floor be Ti, middle level be Pt, upper strata be Au, its thickness
Spend for 0.1～5.7 μm/0.08～2.8 μm/0.04～0.8 μm.
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| CN103137476A (en) * | 2011-12-01 | 2013-06-05 | 电力集成公司 | GaN high voltage HFET with passivation plus gate dielectric multilayer structure |
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