CN104393041B - High-electron-mobility transistor of T-shaped gate field plate and manufacturing method of high-electron-mobility transistor - Google Patents

Abstract

The invention discloses a T-shaped gate field plate high electron mobility transistor and a manufacturing method thereof, which mainly solves the problem of complicated process when the existing field plate technology realizes high breakdown voltage. Its structure includes from bottom to top: substrate (1), transition layer (2), barrier layer (3), passivation layer (8) and protective layer (11), deposited on the barrier layer (3) There are source (4), drain (5) and gate (7), mesas (6) are engraved on the side of the barrier layer (3), grooves (9) are engraved in the passivation layer (8), passivation A T-shaped grid field plate (10) is deposited between the chemical layer (8) and the protective layer (11), the T-shaped grid field plate is electrically connected to the grid (7), and the lower end is completely filled in the groove (9) Inside. The invention has the advantages of simple manufacturing process, high breakdown voltage, high reliability and high yield.

Description

T-shaped gate field plate high electron mobility transistor and manufacturing method thereof

technical field

The invention belongs to the technical field of microelectronics, and relates to a semiconductor device, especially a T-shaped gate field plate high electron mobility transistor, which can be used as a basic device of a power electronic system.

technical background

Power semiconductor devices are important components of power electronic systems and effective tools for power processing. In recent years, as energy and environmental issues have become increasingly prominent, research and development of new high-performance, low-loss power devices has become one of the effective ways to improve power utilization, save energy, and alleviate energy crises. However, in the research of power devices, there is a serious constraint relationship between high speed, high voltage and low on-resistance. Reasonable and effective improvement of this constraint relationship is the key to improving the overall performance of the device. As the market continues to put forward higher efficiency, smaller size, and higher frequency requirements for power systems, the performance of traditional Si-based semiconductor power devices has approached its theoretical limit. In order to further reduce the chip area, increase the operating frequency, increase the operating temperature, reduce the on-resistance, increase the breakdown voltage, reduce the volume of the whole machine, and improve the efficiency of the whole machine, the wide bandgap semiconductor material represented by gallium nitride, with its Larger bandgap width, higher critical breakdown electric field and higher electron saturation drift velocity, as well as outstanding advantages such as stable chemical properties, high temperature resistance, and radiation resistance, stand out in the preparation of high-performance power devices and have great application potential. In particular, high electron mobility transistors using GaN-based heterojunction structures, that is, GaN-based HEMT devices, can meet the needs of next-generation electronic equipment for higher power, The requirements of higher frequency, smaller volume and harsher high temperature work have broad and special application prospects in the economic and military fields.

However, there are inherent defects in the structure of conventional GaN-based HEMT devices, which will lead to a distorted distribution of the electric field intensity in the device channel, especially the extremely high electric field peak near the device gate and drain. As a result, the breakdown voltage of the actual GaN-based HEMT device is often far lower than the theoretical expectation, and there are reliability problems such as current collapse and inverse piezoelectric effect, which seriously restrict the application and development in the field of power electronics. In order to solve the above problems, researchers at home and abroad have proposed many methods, and the field plate structure is the most effective and widely used one among them. In 2000, NQ Zhang and others from UCSB in the United States successfully applied the field plate structure to GaN-based HEMT power devices for the first time, and developed an overlapping gate device with a saturated output current of 500mA/mm and an off-state breakdown voltage of 570V. For the GaN device with the highest reported breakdown voltage, see Highbreakdown GaN HEMT with overlapping gate structure, IEEE Electron Device Letters, Vol.21, No.9, pp.421-423, 2000. Subsequently, research institutions in various countries have launched related research work, and the United States and Japan are the main leaders in this field. In the United States, UCSB, University of South Carolina, Cornell University, and IR Corporation, a well-known manufacturer of power electronic devices, are mainly engaged in this research. Japan started relatively late, but they attach great importance to the work in this area, with large capital investment and a large number of institutions, including: Toshiba, Furukawa, Panasonic, Toyota and Fuji and other large companies. With the deepening of the research, the researchers found that increasing the length of the field plate can increase the breakdown voltage of the device. However, the increase of the field plate length will make the field plate efficiency, that is, the breakdown voltage ratio of the field plate length, continue to decrease, that is, the ability of the field plate to increase the breakdown voltage of the device gradually tends to saturation with the increase of the field plate length, see Enhancement of breakdown voltage in AlGaN/GaN high electron mobility transistors using a field plate, IEEE Transactions on Electron Devices, Vol.48, No.8, pp.1515-1521, 2001, and Development and characteristic analysis of a field-plated Al ₂ O ₃ /AlInN/GaN MOSHEMT, Chinese Physics B, Vol.20, No.1, pp.0172031-0172035, 2011. Therefore, in order to further improve the breakdown voltage of the device while taking into account the efficiency of the field plate, HL Xing et al. of UCSB proposed a double-layer field plate structure in 2004. The double-layer gate field plate GaN-based HEMT device they developed can obtain up to 900V Breakdown voltage, maximum output current 700mA/mm, see High breakdown voltage AlGaN-GaN HEMTs achieved by multiplefield plates, IEEE Electron Device Letters, Vol.25, No.4, pp.161-163, 2004. This double-layer field plate structure has become the mainstream field plate technology used internationally to improve the breakdown characteristics of GaN-based power devices and improve the overall performance of the device. However, the process of GaN-based double-layer field plate HEMT devices is complex and the manufacturing cost is higher. The fabrication of each layer of field plate requires process steps such as photolithography, metal deposition, and passivation dielectric deposition. Moreover, in order to optimize the thickness of the dielectric material under the field plates of each layer to maximize the breakdown voltage, tedious process debugging and optimization must be carried out, which greatly increases the difficulty of device manufacturing and reduces the yield of devices.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies of the above-mentioned prior art, to provide a T-shaped gate field plate high electron mobility transistor with simple manufacturing process, high breakdown voltage, high field plate efficiency and high reliability and a manufacturing method thereof, to The manufacturing difficulty of the device is reduced, the breakdown characteristic and reliability of the device are improved, and the yield of the device is increased.

In order to achieve the above object, the device structure provided by the present invention adopts a heterojunction structure composed of GaN-based wide bandgap semiconductor materials, including from bottom to top: substrate, transition layer, barrier layer, passivation layer and protective layer, potential A source, a drain, and a gate are deposited on the barrier layer, and a mesa is engraved on the side of the barrier layer, and the depth of the mesa is greater than the thickness of the barrier layer. It is characterized in that a groove is engraved in the passivation layer, and the passivation layer A T-shaped grid field plate is deposited between the protection layer, and the T-shaped grid field plate is electrically connected to the gate, and the lower end of the T-shaped grid field plate completely fills the groove.

Preferably, the groove depth s is 0.11-8.2 μm, and the width b is 0.42-6.3 μm.

Preferably, the distance d between the bottom of the groove and the barrier layer is 0.057-0.29 μm.

Preferably, the distance c between the edge of the T-shaped gate field plate near the drain and the edge of the groove near the drain is 0.62-7.9 μm.

Preferably, the distance a between the edge of the groove near the gate and the edge of the gate near the drain is s×(d) ^0.5 , where s is the depth of the groove, and d is the distance between the bottom of the groove and the potential distance between layers.

In order to achieve the above object, the present invention makes the method for T-shaped gate field plate high electron mobility transistor, comprises following process:

The first step is to epitaxially GaN-based wide bandgap semiconductor material on the substrate to form a transition layer;

The second step is to epitaxially GaN-based wide bandgap semiconductor material on the transition layer to form a barrier layer;

The third step is to make a mask on the barrier layer for the first time, use the mask to deposit metal on both ends of the barrier layer, and then perform rapid thermal annealing in _N2 atmosphere to make the source and drain respectively;

The fourth step is to make a mask on the barrier layer for the second time, and use the mask to etch the barrier layer on the left side of the source and the right side of the drain, and the depth of the etching area is greater than the thickness of the barrier layer. form a table;

The fifth step is to make a mask on the barrier layer for the third time, and use the mask to deposit metal on the barrier layer between the source and the drain to make the gate;

The sixth step is to deposit a passivation layer on the upper part of the source, the upper part of the drain, the upper part of the gate, the upper part of the barrier layer between the gate and the source, and the upper part of the barrier layer between the gate and the drain;

The seventh step is to make a mask on the passivation layer for the fourth time, and use the mask to etch in the passivation layer between the gate and the drain to make a depth s of 0.11-8.2 μm and a width b of For a groove of 0.42-6.3 μm, the distance d between the bottom of the groove and the barrier layer is 0.057-0.29 μm, and the distance a between the edge of the groove near the gate and the edge of the gate near the drain is s×(d) ^0.5 , where s is the depth of the groove, and d is the distance between the bottom of the groove and the barrier layer;

The eighth step is to make a mask for the fifth time on the passivation layer, using the mask to deposit metal in the groove and on the passivation layer between the source and the drain, the deposited metal should completely fill the cavity groove to form a T-shaped grid field plate with a thickness of 0.11-8.2 μm, the distance c between the edge of the groove on the side close to the drain and the edge of the T-shaped grid field plate close to the drain is 0.62-7.9 μm, and The T-shaped grid field plate is electrically connected to the grid;

In the ninth step, an insulating dielectric material is deposited on the upper part of the T-shaped gate field plate and other regions of the passivation layer to form a protective layer and complete the fabrication of the entire device.

The device of the present invention has the following advantages compared with the high electron mobility transistor using the traditional gate field plate:

1. Further increase the breakdown voltage.

Because the present invention adopts the T-shaped gate field plate structure, when the device is in the working state, especially in the off state, the surface potential of the barrier layer gradually increases from the gate to the drain, thereby increasing the power consumption in the barrier layer. The area of the depletion region, that is, the high resistance region, improves the distribution of the depletion region, and promotes the depletion region in the barrier layer between the gate and the drain to bear a larger drain-source voltage, thereby greatly improving the device's strike wear voltage.

2. The gate leakage current is further reduced, and the reliability of the device is improved.

Because the present invention adopts the T-shaped gate field plate structure, the distribution of electric field lines in the depletion region of the device barrier layer is more effectively modulated, and the gate in the device is close to the edge of the drain side, and the T-shaped gate field plate is close to the drain. An electric field peak will be generated on one side of the edge and the edge of the groove near the drain, and by adjusting the thickness of the passivation layer under the T-shaped gate field plate, the depth and width of the groove, the edge of the T-shaped gate field plate near the drain The distance between the edge of the groove near the drain and the distance between the edge of the groove near the gate and the edge of the gate near the drain can make the above-mentioned electric field peaks equal and smaller than the GaN-based wide bandgap The breakdown electric field of the semiconductor material, thereby minimizing the electric field lines collected by the edge of the gate close to the drain side, effectively reducing the electric field there, greatly reducing the gate leakage current, making the device reliable Both performance and breakdown characteristics have been significantly enhanced.

3. The process is simple, easy to implement, and the yield rate is improved.

The manufacture of the T-shaped grid field plate in the device structure of the present invention can be completed in only one process, which avoids the problem of complicated process brought about by the traditional stacked layer field plate structure, and greatly improves the yield of the device.

Simulation results show that the breakdown voltage of the device of the invention is far greater than that of a high electron mobility transistor using a traditional gate field plate.

The technical contents and effects of the present invention will be further described below in conjunction with the accompanying drawings and embodiments.

Description of drawings

Figure 1 is a structural diagram of a high electron mobility transistor using a conventional gate field plate;

Fig. 2 is the structural diagram of the T-shaped gate field plate high electron mobility transistor of the present invention;

Fig. 3 is the fabrication flowchart of T-shaped gate field plate high electron mobility transistor of the present invention;

Fig. 4 is a graph of the electric field in the barrier layer obtained by simulating the conventional device and the device of the present invention.

detailed description

Referring to Figure 2, the T-shaped gate field plate high electron mobility transistor of the present invention is based on a GaN-based wide bandgap semiconductor heterojunction structure, which includes: a substrate 1, a transition layer 2, a barrier layer 3, a source 4, a drain pole 5, mesa 6, gate 7, passivation layer 8, groove 9, T-shaped gate field plate 10 and protective layer 11. The substrate 1, the transition layer 2 and the barrier layer 3 are distributed from bottom to top, the source 4 and the drain 5 are deposited on the barrier layer 3, and the gate 7 is deposited between the source 4 and the drain 5 On the barrier layer, the mesa 6 is made on the barrier layer on the left side of the source and the right side of the drain, and the depth of the mesa is greater than the thickness of the barrier layer; the passivation layer 8 covers the upper part of the source, the upper part of the drain, and the gate respectively. The upper part of the electrode, the upper part of the barrier layer between the gate and the source, and the upper part of the barrier layer between the gate and the drain. The groove 9 is located in the passivation layer 8, the depth s of the groove is 0.11-8.2 μm, the width b is 0.42-6.3 μm, the distance d between the bottom of the groove and the barrier layer is 0.057-0.29 μm, and the groove is close to The distance a between the edge of the gate side and the edge of the gate close to the drain, the depth s of the groove, and the distance d between the bottom of the groove and the barrier layer satisfy the relationship a=s×(d) ^0.5 . A T-shaped grid field plate 10 is deposited between the passivation layer 8 and the protective layer 11 , the T-shaped grid field plate is electrically connected to the gate 7 , and the lower end of the T-shaped grid field plate completely fills the groove 9 . The distance c between the edge of the T-shaped gate field plate near the drain and the edge of the groove near the drain is 0.62-7.9 μm. The protection layer 11 is located on the upper part of the T-shaped gate field plate 10 and on other regions of the passivation layer 8 .

The substrate 1 of the above-mentioned device is made of sapphire or silicon carbide or silicon material; the transition layer 2 is composed of several layers of the same or different GaN-based wide bandgap semiconductor materials, and its thickness is 1-5 μm; the barrier layer 3 is composed of several layers of the same or different Composition of different GaN-based wide bandgap semiconductor materials, the thickness of which is 5-50nm; passivation layer 8 and protective layer 11 are made of SiO ₂ , SiN, Al ₂ O ₃ , Sc ₂ O ₃ , HfO ₂ , TiO ₂ Any one or other insulating dielectric material, the thickness of the passivation layer is the sum of the depth s of the groove and the distance d between the bottom of the groove and the barrier layer, that is, 0.167-8.49 μm; the thickness of the protective layer is 0.12-8 μm; The T-shaped grid field plate 10 is composed of three layers of different metals, and its thickness is 0.11-8.2 μm.

Referring to Fig. 3, the process of making T-shaped gate field plate high electron mobility transistor in the present invention provides the following three embodiments:

Embodiment 1: The substrate is sapphire, the passivation layer is Al ₂ O ₃ , the protective layer is SiN, and the T-gate field plate is a T-gate field plate high electron mobility transistor composed of Ti/Mo/Au metal.

Step 1. Epitaxial GaN material on the sapphire substrate 1 from bottom to top to form the transition layer 2, as shown in FIG. 3a.

An undoped transition layer 2 with a thickness of 1 μm is epitaxially formed on the sapphire substrate 1 by metal organic chemical vapor deposition technology, and the transition layer is composed of GaN materials with thicknesses of 30 nm and 0.97 μm from bottom to top. The process conditions used for the epitaxial lower layer GaN material are: temperature 530°C, pressure 45 Torr, hydrogen gas flow rate 4400 sccm, ammonia gas flow rate 4400 sccm, gallium source flow rate 22 μmol/min; the process conditions for the epitaxial upper layer GaN material are: temperature 960°C, pressure 45 Torr, hydrogen flow rate 4400 sccm, ammonia gas flow rate 4400 sccm, gallium source flow rate 120 μmol/min.

Step 2. Deposit undoped Al _0.5 Ga _0.5 N on the GaN transition layer 2 to form a barrier layer 3, as shown in FIG. 3b.

Deposit an undoped Al _0.5 Ga _0.5 N barrier layer 3 with a thickness of 5 nm and an aluminum composition of 0.5 on the GaN transition layer 2 using metal organic chemical vapor deposition technology. The process conditions used are: the temperature is 980 °C, the pressure is 45 Torr, the flow rate of hydrogen gas is 4400 sccm, the flow rate of ammonia gas is 4400 sccm, the flow rate of gallium source is 35 μmol/min, and the flow rate of aluminum source is 7 μmol/min.

Step 3. Deposit metal Ti/Al/Ni/Au on both ends of the barrier layer 3 to make the source 4 and the drain 5, as shown in FIG. 3c.

Make a mask on the Al _0.5 Ga _0.5 N barrier layer 3 for the first time, use electron beam evaporation technology to deposit metal on both ends, and then perform rapid thermal annealing in N ₂ atmosphere to make source 4 and drain 5 , where the deposited metal is a Ti/Al/Ni/Au metal combination, that is, Ti, Al, Ni and Au from bottom to top, and its thickness is 0.018μm/0.135μm/0.046μm/0.052μm. The process conditions used for depositing metal are: the degree of vacuum is less than 1.8×10 ^-3 Pa, the power range is 200-1000W, and the evaporation rate is less than The technological conditions adopted for the rapid thermal annealing are: the temperature is 850° C., and the time is 35 s.

Step 4. Etching the barrier layer on the left side of the source and the right side of the drain to form the mesa 6, as shown in FIG. 3d.

Make a mask for the second time on the Al _0.5 Ga _0.5 N barrier layer 3, and use reactive ion etching technology to etch the barrier layer on the left side of the source and the right side of the drain to form a mesa 6 with an etching depth of 10nm . The process conditions used for etching are as follows: the flow rate of Cl ₂ is 15 sccm, the pressure is 10 mTorr, and the power is 100 W.

Step 5. Deposit metal Ni/Au on the barrier layer between the source 4 and the drain 5 to make the gate 7, as shown in FIG. 3e.

Make a mask on the Al _0.5 Ga _0.5 N barrier layer 3 for the third time, use electron beam evaporation technology to deposit metal on the barrier layer between the source 4 and the drain 5, and make the gate 7, where the deposited The deposited metal is a Ni/Au metal combination, that is, the lower layer is Ni and the upper layer is Au, and its thickness is 0.046μm/0.21μm. The process conditions used for depositing metal are: the degree of vacuum is less than 1.8×10 ^-3 Pa, the power range is 200-1000W, and the evaporation rate is less than

Step 6. On the upper part of the source, the upper part of the drain, the upper part of the gate, the upper part of the Al _0.5 Ga _0.5 N barrier layer between the gate and the source, and the Al _0.5 Ga _0.5 N barrier between the gate and the drain Deposit an Al ₂ O ₃ passivation layer 8 on top of the layer, as shown in Figure 3f.

Use atomic layer deposition technology to cover the upper part of the source, the upper part of the drain, the upper part of the gate, the upper part of the Al _0.5 Ga _0.5 N barrier layer between the gate and the source, and the Al _0.5 Ga between the gate and the drain On the top of the _0.5 N barrier layer, an Al ₂ O ₃ passivation layer 8 with a thickness of 0.167 μm is deposited. The process conditions for depositing the passivation layer are as follows: TMA and H ₂ O are used as reaction sources, the carrier gas is N ₂ , the flow rate of the carrier gas is 200 sccm, the substrate temperature is 300° C., and the pressure is 700 Pa.

Step 7. Etching the passivation layer between the gate 7 and the drain 5 to form a groove 9, as shown in FIG. 3g.

Make a mask for the fourth time on the passivation layer 8, and use reactive ion etching technology to etch in the passivation layer between the grid 7 and the drain 5 to make a groove 9, wherein the groove depth s is 0.11 μm, the width b is 0.42 μm, the distance d between the bottom of the groove and the barrier layer is 0.057 μm, and the distance a between the edge of the groove near the gate and the edge of the gate near the drain is 0.026 μm . The process conditions used for etching are as follows: the flow rate of CF ₄ is 45 sccm, the flow rate of O ₂ is 5 sccm, the pressure is 15 mTorr, and the power is 250W.

Step 8. Deposit metal Ti/Mo/Au in the groove and on the passivation layer between the source 4 and the drain 5 to make a T-shaped gate field plate 10, as shown in FIG. 3h.

Make a mask for the fifth time on the passivation layer 8, use electron beam evaporation technology to deposit metal on the passivation layer in the groove and between the source electrode 4 and the drain electrode 5 to make the T-shaped grid field plate 10, and The T-shaped gate field plate is electrically connected to the gate, and the deposited metal is a metal combination of Ti/Mo/Au, that is, the lower layer is Ti, the middle layer is Mo, and the upper layer is Au, and its thickness is 0.05 μm/0.05 μm/0.01 μm. The deposited metal should completely fill the groove 9, and the distance c between the edge of the T-shaped gate field plate 10 near the drain and the edge of the groove 9 near the drain is 0.62 μm. The process conditions used for depositing metal are: the degree of vacuum is less than 1.8×10 ^-3 Pa, the power range is 200-1000W, and the evaporation rate is less than

Step 9. Deposit SiN on the top of the T-shaped gate field plate 10 and other areas of the passivation layer 8 to form a protective layer 11, as shown in FIG. 3i.

Use plasma-enhanced chemical vapor deposition technology to deposit SiN on the top of the T-shaped gate field plate 10 and other regions of the passivation layer 8 to make a protective layer 11, and its thickness is 0.12 μm, thereby completing the production of the entire device. The process conditions used in the layer are: the gas is NH ₃ , N ₂ and SiH ₄ , the gas flow rates are 2.5 sccm, 950 sccm and 250 sccm respectively, and the temperature, RF power and pressure are 300°C, 25W and 950mTorr respectively.

Embodiment 2: The substrate is silicon carbide, the passivation layer is SiN, the protective layer is SiO ₂ , and the T-gate field plate is a T-gate field plate high electron mobility transistor composed of Ti/Ni/Au metal.

Step 1. Epitaxially AlN and GaN materials on the silicon carbide substrate 1 from bottom to top to form a transition layer 2, as shown in FIG. 3a.

1.1) Using metal-organic chemical vapor deposition technology to epitaxially undoped AlN material with a thickness of 50nm on the silicon carbide substrate 1; the process conditions for the epitaxy are: temperature is 1000°C, pressure is 45Torr, hydrogen flow rate is 4600sccm, The flow rate of ammonia gas is 4600 sccm, and the flow rate of aluminum source is 5 μmol/min;

1.2) Using metal-organic chemical vapor deposition technology to epitaxially GaN material with a thickness of 2.45 μm on the AlN material to complete the fabrication of the transition layer 2; the epitaxy process conditions are: temperature 1000 ° C, pressure 45 Torr, hydrogen flow rate 4600 sccm , the flow rate of ammonia gas is 4600 sccm, and the flow rate of gallium source is 120 μmol/min.

The epitaxy in this step is not limited to metal-organic chemical vapor deposition technology, and molecular beam epitaxy technology or hydride vapor phase epitaxy technology can also be used.

Step 2. Epitaxially Al _0.3 Ga _0.7 N and GaN materials on the transition layer 2 from bottom to top to form a barrier layer 3 , as shown in FIG. 3 b .

2.1) Deposit an Al _0.3 Ga _0.7 N material with a thickness of 27nm and an aluminum composition of 0.3 on the GaN transition layer 2 by metal-organic chemical vapor deposition technology; the epitaxy process conditions are: temperature 1100°C, pressure 45Torr , the flow rate of hydrogen gas is 4600 sccm, the flow rate of ammonia gas is 4600 sccm, the flow rate of gallium source is 16 μmol/min, and the flow rate of aluminum source is 8 μmol/min;

2.2) Using metal-organic chemical vapor deposition technology to epitaxially GaN material with a thickness of 3nm on the Al _0.3 Ga _0.7 N material to complete the fabrication of the barrier layer 3; the epitaxy process conditions are: temperature 1050°C, pressure 40Torr, The flow rate of hydrogen gas is 4200 sccm, the flow rate of ammonia gas is 4200 sccm, and the flow rate of gallium source is 12 μmol/min.

The epitaxy in this step is not limited to metal-organic chemical vapor deposition technology, and molecular beam epitaxy technology or hydride vapor phase epitaxy technology can also be used.

Step 3. Deposit metal Ti/Al/Ni/Au on both ends of the barrier layer 3 to form the source 4 and the drain 5, as shown in FIG. 3c.

3.1) Make a mask on the barrier layer 3 for the first time, and use electron beam evaporation technology to deposit metal on its two ends. The deposited metal is a metal combination of Ti/Al/Ni/Au, that is, from bottom to top, respectively Ti, Al, Ni and Au, the thickness of which is 0.018μm/0.135μm/0.046μm/0.052μm, the metal deposition process conditions are: the vacuum degree is less than 1.8×10 ^-3 Pa, the power range is 200 ~ 1000W, the evaporation rate less than

3.2) Perform rapid thermal annealing in N ₂ atmosphere to complete the fabrication of the source electrode 4 and the drain electrode 5 , the process conditions of the rapid thermal annealing are as follows: the temperature is 850° C., and the time is 35 s.

The metal deposition in this step is not limited to the electron beam evaporation technique, and sputtering technique can also be used.

Step 4. Etching the barrier layer 3 on the left side of the source and the right side of the drain to form a mesa 6, as shown in FIG. 3d.

Make a mask on the barrier layer 3 for the second time, and use reactive ion etching technology to etch the barrier layer 3 on the left side of the source and the right side of the drain to form a mesa 6, wherein the etching depth is 100nm; Etching technology The process conditions used for etching the mesa 6 are: the Cl ₂ flow rate is 15 sccm, the pressure is 10 mTorr, and the power is 100 W.

The etching in this step is not limited to the reactive ion etching technique, and sputtering technique or plasma etching technique may also be used.

Step 5. Deposit metal Ni/Au on the barrier layer 3 between the source and the drain to make the gate 7, as shown in FIG. 3e.

Make a mask on the barrier layer 3 for the third time, use electron beam evaporation technology to deposit metal on the barrier layer 3 between the source electrode 4 and the drain electrode 5, and make the gate 7, wherein the deposited metal is Ni/Au metal combination, that is, the lower layer is Ni and the upper layer is Au, and its thickness is 0.046μm/0.21μm; the process conditions used for depositing Ni/Au by electron beam evaporation technology are: the process conditions used for depositing metal are: vacuum degree Less than 1.8×10 ^-3 Pa, the power range is 200~1000W, and the evaporation rate is less than

The metal deposition in this step is not limited to the electron beam evaporation technique, and sputtering technique can also be used.

Step 6. Deposit SiN on the top of the source, the top of the drain, the top of the gate, the top of the barrier layer 3 between the gate and the source, and the top of the barrier layer 3 between the gate and the drain to make passivation Layer 8, as shown in Figure 3f.

Use plasma enhanced chemical vapor deposition technology to cover the upper part of the source, the upper part of the drain, the upper part of the gate, the upper part of the barrier layer 3 between the gate and the source, and the barrier layer 3 between the gate and the drain On the upper part, a SiN passivation layer 8 with a thickness of 4.12 μm is deposited; the process conditions used are: the gas is NH ₃ , N ₂ and SiH ₄ , the gas flow rates are 2.5 sccm, 950 sccm and 250 sccm respectively, and the temperature, RF power and The pressures were 300°C, 25W and 950mTorr, respectively.

The deposition of the passivation layer in this step is not limited to the plasma enhanced chemical vapor deposition technique, and electron beam evaporation technique, sputtering technique or atomic layer deposition technique may also be used.

Step 7. Etching and forming a groove 9 in the passivation layer 8 between the gate 7 and the drain 5, as shown in FIG. 3g.

Make a mask for the fourth time on the passivation layer 8, use reactive ion etching technology to etch on the passivation layer between the grid 7 and the drain 5, to make the groove 9, wherein the groove depth s is 4 μm, the width b is 3.5 μm, the distance d between the bottom of the groove and the barrier layer is 0.12 μm, and the distance a between the edge of the groove near the gate and the edge of the gate near the drain is 1.386 μm; The process conditions used for etching grooves by reactive ion etching technology are: the flow rate of CF ₄ is 45 sccm, the flow rate of O ₂ is 5 sccm, the pressure is 15 mTorr, and the power is 250W.

The etching in this step is not limited to the reactive ion etching technique, and sputtering technique or plasma etching technique may also be used.

Step 8. Deposit metal Ti/Ni/Au in the groove and on the passivation layer 8 between the source 4 and the drain 5 to make a T-shaped gate field plate 10, as shown in FIG. 3h.

Make a mask for the fifth time on the passivation layer 8, use electron beam evaporation technology to deposit metal on the passivation layer in the groove and between the source electrode 4 and the drain electrode 5 to make the T-shaped grid field plate 10, and The T-shaped gate field plate is electrically connected to the gate, and the deposited metal is a metal combination of Ti/Ni/Au, that is, the lower layer is Ti, the middle layer is Ni, and the upper layer is Au, and its thickness is 3 μm/0.8 μm/0.2 μm. Wherein the deposited metal will completely fill the groove 9, and the distance c between the edge of the T-shaped gate field plate 10 near the drain and the edge of the groove 9 near the drain is 4 μm; electron beam evaporation technology deposits Ti The process conditions used for /Ni/Au are: the degree of vacuum is less than 1.8×10 ^-3 Pa, the power range is 200-1000W, and the evaporation rate is less than

The metal deposition in this step is not limited to the electron beam evaporation technique, and sputtering technique can also be used.

Step 9. Deposit SiO ₂ on the top of the T-shaped gate field plate 10 and other areas of the passivation layer 8 to form a protective layer 11 , as shown in FIG. 3 i .

Use plasma-enhanced chemical vapor deposition technology to deposit _SiO2 on the top of the T-shaped gate field plate 10 and other regions of the passivation layer 8 to make a protective layer 11, and its thickness is 4 μm, thereby completing the production of the entire device; The process conditions are as follows: the flow rate of N ₂ O is 850 sccm, the flow rate of SiH ₄ is 200 sccm, the temperature is 250° C., the RF power is 25 W, and the pressure is 1100 mTorr.

The deposition of the protective layer in this step is not limited to the plasma enhanced chemical vapor deposition technique, and electron beam evaporation technique, sputtering technique or atomic layer deposition technique may also be used.

Embodiment 3: Manufacturing a T-gate field plate high electron mobility transistor with a silicon substrate, a passivation layer of SiO ₂ , a protective layer of SiN, and a T-gate field plate of Ti/Pt/Au metal combination.

Step A. Epitaxially AlN and GaN materials on the silicon substrate 1 from bottom to top to form the transition layer 2, as shown in FIG. 3a.

A1) Using metal-organic chemical vapor deposition technology at a temperature of 800° C., a pressure of 40 Torr, a flow rate of hydrogen gas of 4000 sccm, a flow rate of ammonia gas of 4000 sccm, and a flow rate of aluminum source of 25 μmol/min, the epitaxy on the silicon substrate 1 AlN material with a thickness of 200nm;

A2) Using metal-organic chemical vapor deposition technology at a temperature of 980°C, a pressure of 45Torr, a flow rate of hydrogen gas of 4000 sccm, a flow rate of ammonia gas of 4000 sccm, and a source flow rate of gallium of 120 μmol/min, the epitaxial thickness on the AlN material is 4.8 μm GaN material to complete the fabrication of the transition layer 2 .

Step B. Depositing Al _0.1 Ga _0.9 N and GaN materials from bottom to top on the transition layer to form a barrier layer 3 , as shown in FIG. 3 b .

B1) Using metal-organic chemical vapor deposition technology at a temperature of 1000°C, a pressure of 40Torr, a hydrogen flow rate of 4000 sccm, an ammonia gas flow rate of 4000 sccm, a gallium source flow rate of 12 μmol/min, and an aluminum source flow rate of 12 μmol/min. , epitaxial Al _0.1 Ga _0.9 N material with a thickness of 46 nm and an aluminum composition of 0.1 on the GaN transition layer 2;

B2) Using metal-organic chemical vapor deposition technology at a temperature of 1000°C, a pressure of 40Torr, a flow rate of hydrogen gas of 4000 sccm, a flow rate of ammonia gas of 4000 sccm, and a source flow rate of gallium of 3 μmol/min, on the Al _0.1 Ga _0.9 N material GaN material with a thickness of 4 nm is epitaxially applied to complete the fabrication of the barrier layer 3 .

Step C. Deposit metal Ti/Al/Ni/Au on both ends of the barrier layer 3 to make the source 4 and the drain 5, as shown in FIG. 3c.

C1) Make a mask on the barrier layer 3 for the first time, use electron beam evaporation technology at a vacuum degree of less than 1.8×10 ^{- 3} Pa, a power range of 200-1000W, and an evaporation rate of less than Metals are deposited on both ends under the process conditions, and the deposited metals are Ti/Al/Ni/Au metal combination, that is, Ti, Al, Ni and Au from bottom to top, and the thickness is 0.018μm /0.135μm/0.046μm/0.052μm;

C2) Perform rapid thermal annealing under the process conditions of N ₂ atmosphere, temperature 850° C., and time 35 s, to complete the fabrication of source 4 and drain 5 .

Step D. Etching the barrier layer 3 on the left side of the source and the right side of the drain to form a mesa 6, as shown in FIG. 3d.

Make a mask on the barrier layer 3 for the second time, using reactive ion etching technology, under the process conditions of Cl ₂ flow rate of 15 sccm, pressure of 10 mTorr, and power of 100 W, the barrier layer on the left side of the source and the right side of the drain 3 is etched to form a mesa 6, wherein the etching depth is 200 nm.

Step E. Deposit metal Ni/Au on the barrier layer 3 between the source 4 and the drain 5 to make the gate 7, as shown in FIG. 3e.

Make a mask on the barrier layer 3 for the third time, using electron beam evaporation technology at a vacuum degree of less than 1.8×10 ^-3 Pa, a power range of 200-1000W, and an evaporation rate of less than Under the process conditions, metal is deposited on the barrier layer 3 between the source 4 and the drain 5 to make the gate 7. The deposited metal is a Ni/Au metal combination, that is, the lower layer is Ni and the upper layer is Au. , and its thickness is 0.046μm/0.21μm.

Step F. Deposit _SiO2 material on the upper part of the source, the upper part of the drain, the upper part of the gate, the upper part of the barrier layer 3 between the gate and the source, and the upper part of the barrier layer 3 between the gate and the drain. Passivation layer 8, as shown in Figure 3f.

Using plasma-enhanced chemical vapor deposition technology, under the process conditions of N ₂ O flow rate of 850 sccm, SiH ₄ flow rate of 200 sccm, temperature of 250°C, RF power of 25W, and pressure of 1100mTorr, the upper part of the source, the upper part of the drain, On the top of the gate, the top of the barrier layer 3 between the gate and the source, and the top of the barrier layer 3 between the gate and the drain, SiO ₂ with a thickness of 8.49 μm is deposited to make a passivation layer 8 .

Step G. Etching and forming a groove 9 in the passivation layer 8 between the gate 7 and the drain 5 , as shown in FIG. 3 g .

Make a mask on the passivation layer 8 for the fourth time, using reactive ion etching technology, under the process conditions that the flow rate of CF ₄ is 20 sccm, the flow rate of O ₂ is 2 sccm, the pressure is 20 mTorr, and the bias voltage is 100 V. Etching is carried out in the passivation layer between the drain electrode 5 to make a groove 9, wherein the groove depth s is 8.2 μm, the width b is 6.3 μm, and the distance d between the bottom of the groove and the barrier layer is 0.29 μm, the distance a between the edge of the groove near the gate and the edge of the gate near the drain is 4.416 μm.

Step H. Deposit Ti/Pt/Au in the groove and on the passivation layer between the source 4 and the drain 5 to make a T-shaped gate field plate 10, as shown in FIG. 3h.

Make a mask on the passivation layer 8 for the fifth time, using electron beam evaporation technology at a vacuum degree of less than 1.8×10 ^-3 Pa, a power range of 200-1000W, and an evaporation rate of less than Under the process conditions, metal is deposited in the groove and on the passivation layer between the source 4 and the drain 5 to make a T-shaped grid field plate 10, and the T-shaped grid field plate is electrically connected to the gate, and the deposited The deposited metal is a metal combination of Ti/Pt/Au in thickness, that is, the lower layer is Ti, the middle layer is Pt, and the upper layer is Au. The deposited metal should completely fill the groove 9, and the distance c between the edge of the T-shaped gate field plate 10 near the drain and the edge of the groove 9 near the drain is 7.9 μm.

Step I. Deposit SiN on the upper part of the T-shaped gate field plate 10 and other regions of the passivation layer 8 to form a protective layer 11, as shown in FIG. 3i.

Using plasma-enhanced chemical vapor deposition technology, the gas is NH ₃ , N ₂ and SiH ₄ , the gas flow rate is 2.5sccm, 950sccm and 250sccm, and the temperature, RF power and pressure are 300℃, 25W and 950mTorr. SiN is deposited on the top of the T-shaped gate field plate 10 and other regions of the passivation layer 8 to make a protective layer 11 with a thickness of 8 μm, thereby completing the fabrication of the entire device.

The effect of the present invention can be further illustrated by the following simulation.

The electric field in the potential barrier layer of the high electron mobility transistor that adopts traditional grid field plate and the potential barrier layer of the device of the present invention is simulated, and the result is as shown in Figure 4, wherein the traditional grid field plate effective length L and the T-shaped grid field of the present invention The effective overall length of the plates is equal.

It can be seen from Figure 4 that the electric field curve of the high electron mobility transistor using the traditional gate field plate in the barrier layer only forms two approximately equal electric field peaks, and the area covered by the electric field curve in the barrier layer is is very small, and the electric field curve of the device of the present invention in the potential barrier layer forms 3 approximately equal electric field peaks, so that the area covered by the electric field curve of the device of the present invention in the potential barrier layer is greatly increased, because in the potential barrier layer The area covered by the electric field curve is approximately equal to the breakdown voltage of the device, indicating that the breakdown voltage of the device of the present invention is far greater than the breakdown voltage of a high electron mobility transistor using a traditional gate field plate.

For those skilled in the art, after understanding the content and principles of the present invention, they can make various amendments and changes in form and details according to the methods of the present invention without departing from the principles and scope of the present invention. But these amendments and changes based on the present invention are still within the protection scope of the claims of the present invention.

Claims (2)

1. A T-shaped gate field plate high electron mobility transistor, comprising from bottom to top: substrate (1), transition layer (2), barrier layer (3), passivation layer (8) and protective layer ( 11), the source (4), drain (5) and gate (7) are deposited on the barrier layer (3), the side of the barrier layer (3) is engraved with a mesa (6), and the mesa depth greater than the thickness of the barrier layer, characterized in that the passivation layer (8) is engraved with a groove (9), the depth s of the groove (9) is 0.11-8.2 μm, the width b is 0.42-6.3 μm, the groove (9) The distance d between the bottom and the barrier layer (3) is 0.057-0.29 μm, and the distance a between the edge of the groove (9) near the gate and the edge of the gate (7) near the drain is s×(d) ^0.5 ; a T-shaped grid field plate (10) is deposited between the passivation layer (8) and the protective layer (11), and the T-shaped grid field plate is electrically connected to the gate (7), and The lower end is completely filled in the groove (9), and the distance c between the edge of the groove (9) near the drain and the edge of the T-shaped gate field plate near the drain is 0.62-7.9 μm. 2. A method for making a T-shaped gate field plate high electron mobility transistor, comprising the following process: In the first step, a GaN-based wide bandgap semiconductor material is epitaxially formed on the substrate (1) to form a transition layer (2); In the second step, a GaN-based wide bandgap semiconductor material is epitaxially formed on the transition layer to form a barrier layer (3); The third step is to make a mask on the barrier layer (3) for the first time, use the mask to deposit metal on both ends of the barrier layer (3), and then perform rapid thermal annealing in _N2 atmosphere, respectively fabricate source (4) and drain (5); The fourth step is to make a mask for the second time on the barrier layer (3), and use the mask to etch the barrier layer on the left side of the source and the right side of the drain, and the depth of the etched area is greater than the barrier layer layer thickness, forming the mesa (6); The fifth step is to make a mask for the third time on the barrier layer (3), and use the mask to deposit metal on the barrier layer between the source and the drain to make the gate (7); The sixth step is to deposit a passivation layer on the top of the source, the top of the drain, the top of the gate, the top of the barrier layer between the gate and the source, and the top of the barrier layer between the gate and the drain ( 8); The seventh step is to make a mask on the passivation layer (8) for the fourth time, and use the mask to etch in the passivation layer (8) between the gate and the drain to make a depth s of 0.11~ 8.2 μm, a groove (9) with a width b of 0.42-6.3 μm, the distance d between the bottom of the groove (9) and the barrier layer (3) is 0.057-0.29 μm, and the groove is close to the edge of the gate side The distance a between the edge of the gate and the side close to the drain is s×(d) ^0.5 , where s is the depth of the groove, and d is the distance between the bottom of the groove and the barrier layer; In the 8th step, make a mask for the fifth time on the passivation layer (8), utilize this mask to deposit metal on the passivation layer in the groove and between the source electrode and the drain electrode, and the deposited metal should be Fill the groove completely to form a T-shaped grid field plate (10) with a thickness of 0.11-8.2 μm, and the distance c between the edge of the groove near the drain and the edge of the T-shaped grid field plate near the drain is 0.62 ~7.9 μm, and electrically connect the T-shaped grid field plate (10) to the grid (7); In the ninth step, an insulating dielectric material is deposited on the upper part of the T-shaped gate field plate (10) and other regions of the passivation layer (8) to form a protective layer (11) to complete the manufacture of the entire device.