CN104393041B - High-electron-mobility transistor of T-shaped gate field plate and manufacturing method of high-electron-mobility transistor - Google Patents
High-electron-mobility transistor of T-shaped gate field plate and manufacturing method of high-electron-mobility transistor Download PDFInfo
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- CN104393041B CN104393041B CN201410659603.2A CN201410659603A CN104393041B CN 104393041 B CN104393041 B CN 104393041B CN 201410659603 A CN201410659603 A CN 201410659603A CN 104393041 B CN104393041 B CN 104393041B
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- 238000004519 manufacturing process Methods 0.000 title abstract description 7
- 239000010410 layer Substances 0.000 claims abstract description 160
- 230000004888 barrier function Effects 0.000 claims abstract description 89
- 238000002161 passivation Methods 0.000 claims abstract description 52
- 238000000034 method Methods 0.000 claims abstract description 50
- 239000011241 protective layer Substances 0.000 claims abstract description 21
- 230000007704 transition Effects 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims description 43
- 229910052751 metal Inorganic materials 0.000 claims description 43
- 230000008569 process Effects 0.000 claims description 30
- 239000000463 material Substances 0.000 claims description 26
- 238000005530 etching Methods 0.000 claims description 19
- 239000004065 semiconductor Substances 0.000 claims description 13
- 238000004151 rapid thermal annealing Methods 0.000 claims description 6
- 230000008859 change Effects 0.000 claims description 5
- 239000012298 atmosphere Substances 0.000 claims description 4
- 239000003989 dielectric material Substances 0.000 claims description 4
- 238000005036 potential barrier Methods 0.000 claims description 3
- 239000013049 sediment Substances 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 40
- 230000015556 catabolic process Effects 0.000 abstract description 26
- 229910002601 GaN Inorganic materials 0.000 description 34
- 239000010931 gold Substances 0.000 description 24
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 20
- 230000005684 electric field Effects 0.000 description 18
- 238000005566 electron beam evaporation Methods 0.000 description 11
- 238000005229 chemical vapour deposition Methods 0.000 description 10
- 238000001020 plasma etching Methods 0.000 description 10
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 9
- 229910021529 ammonia Inorganic materials 0.000 description 9
- 229910052739 hydrogen Inorganic materials 0.000 description 9
- 239000001257 hydrogen Substances 0.000 description 9
- 230000008020 evaporation Effects 0.000 description 8
- 238000001704 evaporation Methods 0.000 description 8
- 230000004907 flux Effects 0.000 description 8
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052733 gallium Inorganic materials 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 238000004544 sputter deposition Methods 0.000 description 7
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 5
- 229910052593 corundum Inorganic materials 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- 238000011160 research Methods 0.000 description 5
- 229910001845 yogo sapphire Inorganic materials 0.000 description 5
- 229910052681 coesite Inorganic materials 0.000 description 4
- 229910052906 cristobalite Inorganic materials 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 229910052594 sapphire Inorganic materials 0.000 description 4
- 239000010980 sapphire Substances 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 229910052682 stishovite Inorganic materials 0.000 description 4
- 229910052905 tridymite Inorganic materials 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000012159 carrier gas Substances 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 150000004678 hydrides Chemical class 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 235000010724 Wisteria floribunda Nutrition 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000004223 radioprotective effect Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- HYXGAEYDKFCVMU-UHFFFAOYSA-N scandium(III) oxide Inorganic materials O=[Sc]O[Sc]=O HYXGAEYDKFCVMU-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N titanium dioxide Inorganic materials O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- Condensed Matter Physics & Semiconductors (AREA)
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- Junction Field-Effect Transistors (AREA)
Abstract
The invention discloses a high-electron-mobility transistor of a T-shaped gate field plate and a manufacturing method of the high-electron-mobility transistor in order to mainly solve the problem that a technique for realizing high breakdown voltage is complex in the existing field plate technology. The structure of the high-electron-mobility transistor, from bottom to top, comprises a substrate (1), a transition layer (2), a barrier layer (3), a passivation layer (8) and a protective layer (11), wherein a source electrode (4), a drain electrode (5) and a grid electrode (7) are deposited on the barrier layer (3); a table surface (6) is engraved on the side surface of the barrier surface (3); a groove (9) is engraved in the passivation layer (8); a T-shaped gate field plate (10) is deposited between the passivation layer (8) and the protective layer (11); the T-shaped gate field plate (10) is electrically connected with the grid electrode (7), and the lower end of the T-shaped gate field plate (10) is totally filled in the groove (9). The high-electron-mobility transistor disclosed by the invention has the advantages of being simple in manufacturing process, high in breakdown voltage, high in reliability and high in rate of finished products.
Description
Technical field
The invention belongs to microelectronics technology, is related to semiconductor device, particularly T-shaped grid field plate high electron mobility brilliant
Body pipe, can be used as the basic device of power electronic system.
Technical background
Power semiconductor is the critical elements of power electronic system, is to carry out electric treatable effective tool.In recent years
Come, with becoming increasingly conspicuous for the energy and environmental problem, research and development novel high-performance, low-loss power device become raising electric energy profit
With one of rate, energy saving, the effective way of alleviating energy crisis.However, in power device research, at a high speed, high pressure with it is low
Serious restricting relation is there is between conducting resistance, rationally, to effectively improve this restricting relation be to improve device globality
The key of energy.As market constantly proposes the requirement of higher efficiency, smaller volume, higher frequency, traditional Si base to power system
Semiconductor power device performance has approached its theoretical limit.In order to be able to further reducing chip area, improving operating frequency, improve
Operating temperature, reduction conducting resistance, raising breakdown voltage, reduction machine volume, raising overall efficiency, with gallium nitride as representative
Semiconductor material with wide forbidden band, drifts about by the electronics saturation of its bigger energy gap, higher critical breakdown electric field and Geng Gao
Speed, and the outstanding advantages such as stable chemical performance, high temperature resistant, radioprotective, show one's talent in terms of high performance power device is prepared,
Application potential is huge.Especially with the HEMT of GaN base heterojunction structure, i.e. GaN base HEMT device, more
It is, because of characteristics such as its low on-resistance, senior engineer's working frequencies, electronics of future generation to be met more high-power to power device, higher
The requirement of frequency, smaller volume and more severe hot operation, has wide and special application prospect in economy and military field.
However, there is inherent shortcoming in conventional GaN base HEMT device structure, device channel electric field intensity can be caused in deformity
, especially there is high peak electric field near vicinity in device grids in distribution.Cause hitting for actual GaN base HEMT device
Voltage is worn often far below theoretical eapectation, and there is the integrity problems such as current collapse, inverse piezoelectric effect, seriously constrain
Application and development in field of power electronics.In order to solve problem above, domestic and international researchers propose numerous methods, and field
Hardened structure be wherein effect significantly, one kind for being most widely used.N.Q.Zhang of U.S. UCSB in 2000 et al. is first
Field plate structure is successfully applied in GaN base HEMT power device, overlapping gate device is developed, saturation output current is 500mA/
Mm, up to 570V, this is reported breakdown voltage highest GaN device at that time to breakdown voltage, referring to High
breakdown GaN HEMT with overlapping gate structure,IEEE Electron Device
Letters,Vol.21,No.9,pp.421-423,2000.Subsequently, research institution of various countries expands one after another the research work of correlation
Make, and the U.S. and Japan are the main leaders in the field.In the U.S., mainly UCSB, Nan Ka university, Cornell University with
And famous IR companies of power electronic devices manufacturer etc. are engaged in the research.Japan is relative to start late, but they are to this side
The work in face is paid much attention to, fund input great efforts, and it is numerous to be engaged in mechanism, including：Toshiba, Furukawa, Panasonic, Toyota and Fuji etc.
Major company.With going deep into for research, researchers have found correspondingly to increase field plate length, can improve device electric breakdown strength.But
The increase of field plate length can make field plate efficiency, i.e. breakdown voltage than field plate length, constantly reduce, that is, field plate improves device and hits
The ability of voltage is worn as the increase of field plate length gradually tends to saturation, referring to Enhancement of breakdown
voltage in AlGaN/GaN high electron mobility transistors using a field plate,
IEEE Transactions on Electron Devices, Vol.48, No.8, pp.1515-1521,2001, and
Development and characteristic analysis of a field-plated Al2O3/AlInN/GaN MOS
HEMT,Chinese Physics B,Vol.20,No.1,pp.0172031-0172035,2011.Therefore, in order to further carry
High device electric breakdown strength, while taking into account field plate efficiency, H.L.Xing of UCSB in 2004 et al. proposes a kind of double-deck field plate knot
Structure, the double-layer grid field plate GaN base HEMT device that they develop can obtain the up to breakdown voltage of 900V, maximum output current
700mA/mm, referring to High breakdown voltage AlGaN-GaN HEMTs achieved by multiple
field plates,IEEE Electron Device Letters,Vol.25,No.4,pp.161-163,2004.It is this double
Layer field plate structure has become current in the world for improving GaN base power device breakdown characteristics, improves the master of device overall performance
Flow field plate technique.However, the complex process of GaN base bilayer field plate HEMT device, manufacturing cost is higher, the making of each layer of field plate
It is required for the processing steps such as photoetching, deposit metal, deposit dielectric passivation.And to optimize under each layer field plate dielectric material thickness with
Realize that breakdown voltage is maximized, it is necessary to carry out loaded down with trivial details process debugging and optimization, therefore considerably increase the difficulty of device manufacture,
Reduce the yield rate of device.
The content of the invention
It is an object of the invention to overcome the shortcomings of above-mentioned prior art, there is provided a kind of manufacturing process is simple, breakdown voltage
High T-shaped grid field plate transistor with high electron mobility of high, field plate efficiency high and reliability and preparation method thereof, to reduce device
Manufacture difficulty, improves the breakdown characteristics and reliability of device, improves the yield rate of device.
For achieving the above object, the device architecture that the present invention is provided is different using GaN base semiconductor material with wide forbidden band composition
Matter junction structure, includes from bottom to top：Substrate, transition zone, barrier layer, passivation layer and protective layer, deposit active above barrier layer
Table top is carved with pole, drain electrode and grid, the side of barrier layer, and land depth is more than barrier layer thickness, it is characterised in that passivation layer
Groove is inside carved with, T-shaped grid field plate is deposited between passivation layer and protective layer, the T-shaped grid field plate is electrically connected with grid, and lower end
It is filled up completely with groove.
Preferably, described depth of groove s is 0.11～8.2 μm, width b is 0.42～6.3 μm.
Preferably, the distance between described bottom portion of groove and barrier layer d is 0.057～0.29 μm.
Preferably, described T-shaped grid field plate is between one lateral edges of drain electrode and groove one lateral edges of close drain electrode
It it is 0.62～7.9 μm apart from c.
Preferably, described groove is near the distance between the lateral edges of grid one and grid one lateral edges of close drain electrode a
For s × (d)0.5, wherein s is depth of groove, and d is the distance between bottom portion of groove and barrier layer.
For achieving the above object, the method that the present invention makes T-shaped grid field plate transistor with high electron mobility, including following mistake
Journey：
The first step, the extension GaN base semiconductor material with wide forbidden band on substrate forms transition zone；
Second step, the extension GaN base semiconductor material with wide forbidden band on transition zone forms barrier layer；
3rd step, makes for the first time mask on barrier layer, using the mask barrier layer two ends deposit metal, then
N2Rapid thermal annealing is carried out in atmosphere, source electrode and drain electrode are made respectively；
4th step, second making mask on barrier layer, using barrier layer of the mask on the left of source electrode, on the right side of drain electrode
On perform etching, and etched area depth be more than barrier layer thickness, formed table top；
5th step, makes for the third time mask on barrier layer, using on mask barrier layer between the source and drain
Deposit metal, makes grid；
6th step, respectively on source electrode top, drain electrode top, grid top, the barrier layer top between grid and source electrode, with
And the barrier layer top deposit passivation layer between grid and drain electrode；
7th step, makes mask the 4th time, in the passivation layer using the mask between grid and drain electrode over the passivation layer
Perform etching, to make depth s as 0.11～8.2 μm, width b is 0.42～6.3 μm of groove, bottom portion of groove and barrier layer it
Between apart from d be 0.057～0.29 μm, the groove near the lateral edges of grid one and grid between one lateral edges of drain electrode away from
It is s × (d) from a0.5, wherein s is depth of groove, and d is the distance between bottom portion of groove and barrier layer；
8th step, over the passivation layer the 5th time making mask, using the mask in groove and source electrode and drain electrode between
Metal is deposited on passivation layer, the metal for being deposited will be filled up completely with groove, to form the T-shaped grid field that thickness is 0.11～8.2 μm
Plate, groove is 0.62～7.9 μm near the distance between one lateral edges of drain electrode c with T-shaped grid field plate near one lateral edges of drain electrode, and
T-shaped grid field plate and grid are electrically connected；
9th step, in T-shaped grid field plate top and other area top deposit insulating dielectric materials of passivation layer, forms protection
Layer, completes the making of whole device.
Device of the present invention compares with advantages below with the HEMT for adopting traditional grid field plate：
1. breakdown voltage is further increased.
The present invention is due to using T-shaped grid field plate structure, making device in the in running order work for being particularly in OFF state
During state, barrier layer surface potential gradually rises from grid to drain electrode, so as to increased barrier layer in depletion region, i.e. high resistance area,
Area, improve the distribution of depletion region, promote the depletion region between grid and drain electrode in barrier layer to undertake bigger drain-source electricity
Pressure, so as to substantially increase the breakdown voltage of device.
2. gate leakage current is further reduced, the reliability of device is improve.
The present invention is because using T-shaped grid field plate structure, the distribution for making electric field line in device barrier layer depletion region has been obtained more
Effectively modulate, grid is near one lateral edges of drain electrode, T-shaped grid field plate one lateral edges of close drain electrode and the close leakage of groove in device
The lateral edges of pole one can all produce a peak electric field, and by adjusting thickness, the depth of groove of T-shaped grid field plate underlying passivation layer
It is close near the distance between one lateral edges of drain electrode and groove near one lateral edges of drain electrode and groove with width, T-shaped grid field plate
The lateral edges of grid one, near the distance between one lateral edges of drain electrode, can cause above-mentioned each peak electric field equal and little with grid
In the breakdown electric field of GaN base semiconductor material with wide forbidden band, so as to reduce edge of the grid near drain electrode side to greatest extent
Collected electric field line, significantly reduces the electric field at this, substantially reduces gate leakage current so that the reliability of device
Significantly increased with breakdown characteristics.
3. process is simple, it is easy to accomplish, improve yield rate.
The making of T-shaped grid field plate in device architecture of the present invention only needs a step process just can complete, it is to avoid traditional stack layers
The process complications problem that field plate structure is brought, substantially increases the yield rate of device.
Simulation result shows that the breakdown voltage of device of the present invention is far longer than the high electron mobility using traditional grid field plate
The breakdown voltage of transistor.
The technology contents and effect of the present invention are further illustrated below in conjunction with drawings and Examples.
Description of the drawings
Fig. 1 is the structure chart of the HEMT using traditional grid field plate；
Fig. 2 is the structure chart of T-shaped grid field plate transistor with high electron mobility of the present invention；
Fig. 3 is the Making programme figure of T-shaped grid field plate transistor with high electron mobility of the present invention；
Fig. 4 is to electric field curve diagram in the barrier layer obtained by traditional devices and device simulation of the present invention.
Specific embodiment
With reference to Fig. 2, T-shaped grid field plate transistor with high electron mobility of the present invention is heterogeneous based on GaN base wide bandgap semiconductor
Junction structure, it includes：Substrate 1, transition zone 2, barrier layer 3, source electrode 4, drain electrode 5, table top 6, grid 7, passivation layer 8, groove 9, T-shaped
Grid field plate 10 and protective layer 11., with barrier layer 3 to be distributed from bottom to top, source electrode 4 and drain electrode 5 are deposited on gesture for substrate 1, transition zone 2
In barrier layer 3, grid 7 is deposited on the barrier layer between source electrode 4 and drain electrode 5, and table top 6 is produced on the right side of source electrode left side and drain electrode
On barrier layer, the land depth is more than barrier layer thickness；Passivation layer 8 is respectively overlay in source electrode top, drain electrode top, on grid
Barrier layer top between portion, grid and source electrode, and the barrier layer top between grid and drain electrode.Groove 9 is located at passivation layer 8
Interior, depth of groove s is 0.11～8.2 μm, and width b is 0.42～6.3 μm, and the distance between bottom portion of groove and barrier layer d is
0.057～0.29 μm, groove is near the lateral edges of grid one and grid near the distance between one lateral edges of drain electrode a, depth of groove s
And the distance between bottom portion of groove and barrier layer d meets relation a=s × (d)0.5.Deposit between passivation layer 8 and protective layer 11
There is T-shaped grid field plate 10, the T-shaped grid field plate is electrically connected with grid 7, and lower end is filled up completely with groove 9.T-shaped grid field plate is near leakage
The lateral edges of pole one are 0.62～7.9 μm near the distance between one lateral edges of drain electrode c with groove.Protective layer 11 is located at T-shaped grid field
The top of plate 10 and other area tops of passivation layer 8.
The substrate 1 of above-mentioned device is using sapphire or carborundum or silicon materials；If transition zone 2 is identical or different by dried layer
GaN base semiconductor material with wide forbidden band is constituted, and its thickness is 1～5 μm；If barrier layer 3 is prohibited by the identical or different GaN base width of dried layer
Carrying semiconductor material is constituted, and its thickness is 5～50nm；Passivation layer 8 and protective layer 11 adopt SiO2、SiN、Al2O3、Sc2O3、
HfO2、TiO2In any one or other insulating dielectric materials, the thickness of passivation layer is depth of groove s and bottom portion of groove and gesture
The distance between barrier layer d sums, i.e., 0.167～8.49 μm；The thickness of protective layer is 0.12～8 μm；T-shaped grid field plate 10 adopts three
The combination of layer different metal is constituted, and its thickness is 0.11～8.2 μm.
With reference to Fig. 3, the present invention makes the process of T-shaped grid field plate transistor with high electron mobility, provides following three kinds of enforcement
Example：
Embodiment one：Making substrate is sapphire, and passivation layer is Al2O3, protective layer is SiN, and T-shaped grid field plate is Ti/Mo/
The T-shaped grid field plate transistor with high electron mobility of Au metallic combinations.
From bottom to top extension GaN material makes transition zone 2, such as Fig. 3 a to step 1. in Sapphire Substrate 1.
Using metal organic chemical vapor deposition technology, epitaxial thickness is 1 μm of undoped p mistake in Sapphire Substrate 1
Layer 2 is crossed, the transition zone is respectively from bottom to top 30nm and 0.97 μm of GaN material by thickness and is constituted.Extension lower floor GaN material is adopted
Process conditions are：Temperature is 530 DEG C, and pressure is 45Torr, and hydrogen flowing quantity is 4400sccm, and ammonia flow is
4400sccm, gallium source flux is 22 μm of ol/min；The process conditions that extension upper strata GaN material is adopted for：Temperature is 960 DEG C, pressure
It is by force 45Torr, hydrogen flowing quantity is 4400sccm, and ammonia flow is 4400sccm, and gallium source flux is 120 μm of ol/min.
Step 2. deposits unadulterated Al in GaN transition layer 20.5Ga0.5N makes barrier layer 3, such as Fig. 3 b.
Using metal organic chemical vapor deposition technology, deposition thickness is 5nm in GaN transition layer 2, and al composition is
0.5 undoped p Al0.5Ga0.5N barrier layers 3, the process conditions that it is adopted for：Temperature is 980 DEG C, and pressure is 45Torr, hydrogen
Flow is 4400sccm, and ammonia flow is 4400sccm, and gallium source flux is 35 μm of ol/min, and silicon source flow is 7 μm of ol/min.
Step 3. makes source electrode 4 and drain electrode 5, such as Fig. 3 c in the two ends deposit metal Ti/Al/Ni/Au of barrier layer 3.
In Al0.5Ga0.5Mask is made on N barrier layers 3 for the first time, using electron beam evaporation technique in its two ends deposit gold
Category, then in N2Rapid thermal annealing is carried out in atmosphere, source electrode 4 and drain electrode 5 is made, wherein the metal for being deposited is Ti/Al/Ni/Au
Metallic combination, i.e., be respectively from bottom to top Ti, Al, Ni and Au, and its thickness is 0.018 μm/0.135 μm/0.046 μm/0.052 μ
m.The process conditions that adopt of deposit metal for：Vacuum is less than 1.8 × 10-3Pa, power bracket be 200～1000W, evaporation rate
It is less thanThe process conditions that rapid thermal annealing is adopted for：Temperature is 850 DEG C, and the time is 35s.
Step 4. performs etching making table top 6, such as Fig. 3 d on the barrier layer on the right of the source electrode left side with drain electrode.
In Al0.5Ga0.5Second making mask on N barrier layers 3, using reactive ion etching technology in the source electrode left side and leakage
Perform etching on the barrier layer on ultra-Right side, form table top 6, etching depth is 10nm.The process conditions that adopt of etching for：Cl2Stream
Measure as 15sccm, pressure is 10mTorr, and power is 100W.
Step 5. deposits W metal/Au and makes grid 7, such as Fig. 3 e on the barrier layer between source electrode 4 and drain electrode 5.
In Al0.5Ga0.5Make mask on N barrier layers 3 for the third time, using electron beam evaporation technique source electrode 4 and drain electrode 5 it
Between barrier layer on deposit metal, make grid 7, wherein the metal for being deposited is Ni/Au metallic combinations, i.e. lower floor be Ni, on
Layer is Au, and its thickness is 0.046 μm/0.21 μm.The process conditions that adopt of deposit metal for：Vacuum is less than 1.8 × 10-3Pa,
Power bracket is 200～1000W, and evaporation rate is less than
Step 6. is in source electrode top, drain electrode top, grid top, the Al between grid and source electrode0.5Ga0.5On N barrier layers
Al between portion, and grid and drain electrode0.5Ga0.5N barrier layers top deposits Al2O3Passivation layer 8, such as Fig. 3 f.
Using atomic layer deposition technology be covered each by source electrode top, drain electrode top, grid top, between grid and source electrode
Al0.5Ga0.5N barrier layers top, and the Al between grid and drain electrode0.5Ga0.5N barrier layers top, completing deposition thickness is
0.167 μm of Al2O3Passivation layer 8.The process conditions that adopt of deposit passivation layer for：With TMA and H2O is reaction source, and carrier gas is N2,
Carrier gas flux is 200sccm, and underlayer temperature is 300 DEG C, and air pressure is 700Pa.
Step 7. performs etching making groove 9, such as Fig. 3 g in the passivation layer between grid 7 and drain electrode 5.
The 4th making mask on passivation layer 8, it is blunt between grid 7 and drain electrode 5 using reactive ion etching technology
Change and performed etching in layer, to make groove 9, wherein depth of groove s is 0.11 μm, and width b is 0.42 μm, bottom portion of groove and potential barrier
The distance between layer d is 0.057 μm, and groove is near the lateral edges of grid one and grid near the distance between one lateral edges of drain electrode a
For 0.026 μm.The process conditions that adopt of etching for：CF4Flow is 45sccm, O2Flow is 5sccm, and pressure is 15mTorr, work(
Rate is 250W.
Step 8. deposits metal Ti/Mo/Au and makes T-shaped grid field on the passivation layer in groove and between source electrode 4 and drain electrode 5
Plate 10, such as Fig. 3 h.
On passivation layer 8 the 5th time making mask, using electron beam evaporation technique in groove and source electrode 4 with drain 5 it
Between passivation layer on deposit metal and make T-shaped grid field plate 10, and T-shaped grid field plate and grid are electrically connected, the metal for being deposited
For Ti/Mo/Au metallic combinations, i.e. lower floor be Ti, middle level be Mo, upper strata be Au, its thickness be 0.05 μm/0.05 μm/0.01 μm.
The metal for wherein being deposited will be filled up completely with groove 9, and T-shaped grid field plate 10 is near one lateral edges of drain electrode with groove 9 near drain electrode one
The distance between lateral edges c is 0.62 μm.The process conditions that adopt of deposit metal for：Vacuum is less than 1.8 × 10-3Pa, power
Scope is 200～1000W, and evaporation rate is less than
Step 9. makes protective layer 11 in other area tops deposit SiN of the top of T-shaped grid field plate 10 and passivation layer 8,
Such as Fig. 3 i.
Using plasma enhanced CVD technology in the top of T-shaped grid field plate 10 and other areas of passivation layer 8
Domain top deposit SiN makes protective layer 11, and its thickness is 0.12 μm, and so as to complete the making of whole device, deposit protective layer is adopted
Process conditions are：Gas is NH3、N2And SiH4, gas flow is respectively 2.5sccm, 950sccm and 250sccm, temperature,
RF power and pressure are respectively 300 DEG C, 25W and 950mTorr.
Embodiment two：Making substrate is carborundum, and passivation layer is SiN, and protective layer is SiO2, T-shaped grid field plate is Ti/Ni/
The T-shaped grid field plate transistor with high electron mobility of Au metallic combinations.
Step one. from bottom to top extension AlN makes transition zone 2, such as Fig. 3 a with GaN material in silicon carbide substrates 1.
1.1) using metal organic chemical vapor deposition technology, epitaxial thickness is not mixing for 50nm in silicon carbide substrates 1
Miscellaneous AlN materials；The process conditions of its extension are：Temperature is 1000 DEG C, and pressure is 45Torr, and hydrogen flowing quantity is 4600sccm,
Ammonia flow is 4600sccm, and silicon source flow is 5 μm of ol/min；
1.2) using metal organic chemical vapor deposition technology, epitaxial thickness is 2.45 μm of GaN materials on AlN materials
Material, completes the making of transition zone 2；The process conditions of its extension are：Temperature is 1000 DEG C, and pressure is 45Torr, and hydrogen flowing quantity is
4600sccm, ammonia flow is 4600sccm, and gallium source flux is 120 μm of ol/min.
The extension of this step is not limited to metal organic chemical vapor deposition technology, it would however also be possible to employ molecular beam epitaxy skill
Art or hydride gas-phase epitaxy technology.
Step 2. extension Al from bottom to top on transition zone 20.3Ga0.7N and GaN material make barrier layer 3, such as Fig. 3 b.
2.1) using metal organic chemical vapor deposition technology, deposition thickness is 27nm, al composition in GaN transition layer 2
For 0.3 Al0.3Ga0.7N materials；The process conditions of its extension are：Temperature is 1100 DEG C, and pressure is 45Torr, and hydrogen flowing quantity is
4600sccm, ammonia flow is 4600sccm, and gallium source flux is 16 μm of ol/min, and silicon source flow is 8 μm of ol/min；
2.2) using metal organic chemical vapor deposition technology in Al0.3Ga0.7Epitaxial thickness is the GaN of 3nm on N materials
Material, completes the making of barrier layer 3；The process conditions of its extension are：Temperature is 1050 DEG C, and pressure is 40Torr, hydrogen flowing quantity
For 4200sccm, ammonia flow is 4200sccm, and gallium source flux is 12 μm of ol/min.
The extension of this step is not limited to metal organic chemical vapor deposition technology, it would however also be possible to employ molecular beam epitaxy skill
Art or hydride gas-phase epitaxy technology.
Step 3. make source electrode 4 and drain electrode 5, such as Fig. 3 c in the two ends deposit metal Ti/Al/Ni/Au of barrier layer 3.
3.1) mask is made for the first time on barrier layer 3, using electron beam evaporation technique in its two ends deposit metal, deposit
Metal be Ti/Al/Ni/Au metallic combinations, i.e., from bottom to top be respectively Ti, Al, Ni and Au, its thickness be 0.018 μm/
0.135 μm/0.046 μm/0.052 μm, its deposit smithcraft condition be：Vacuum is less than 1.8 × 10-3Pa, power bracket is
200～1000W, evaporation rate is less than
3.2) in N2Rapid thermal annealing is carried out in atmosphere, the making of source electrode 4 and drain electrode 5, the work of its rapid thermal annealing is completed
Skill condition is：Temperature is 850 DEG C, and the time is 35s.
The Metal deposition of this step is not limited to electron beam evaporation technique, it would however also be possible to employ sputtering technology.
Step 4. making table top 6, such as Fig. 3 d are performed etching on barrier layer 3 of the left side of source electrode with the right of drain electrode.
Second making mask on barrier layer 3, using reactive ion etching technology on the right of the source electrode left side with drain electrode
Perform etching on barrier layer 3, form table top 6, wherein etching depth is 100nm；Reactive ion etching technology etching table top 6 is adopted
Process conditions be：Cl2Flow is 15sccm, and pressure is 10mTorr, and power is 100W.
The etching of this step is not limited to reactive ion etching technology, it would however also be possible to employ sputtering technology or plasma etching
Technology.
Step 5. W metal/Au is deposited on the barrier layer 3 between source electrode and drain electrode and makes grid 7, such as Fig. 3 e.
Make mask for the third time on barrier layer 3, the potential barrier using electron beam evaporation technique between source electrode 4 and drain electrode 5
Metal is deposited on layer 3, grid 7 is made, wherein it is Au for Ni, upper strata that the metal for being deposited is Ni/Au metallic combinations, i.e. lower floor,
Its thickness is 0.046 μm/0.21 μm；The electron beam evaporation technique process conditions that adopt of deposit Ni/Au for：Deposit metal is adopted
Process conditions are：Vacuum is less than 1.8 × 10-3Pa, power bracket is 200～1000W, and evaporation rate is less than
The Metal deposition of this step is not limited to electron beam evaporation technique, it would however also be possible to employ sputtering technology.
Step 6. on source electrode top, drain electrode top, grid top, the top of barrier layer 3 between grid and source electrode, and
The top of barrier layer 3 deposit SiN between grid and drain electrode makes passivation layer 8, such as Fig. 3 f.
Source electrode top, drain electrode top, grid top, grid are covered each by using plasma enhanced CVD technology
The top of barrier layer 3 between pole and source electrode, and the top of barrier layer 3 between grid and drain electrode, complete deposition thickness for 4.12 μ
The SiN passivation layers 8 of m；The process conditions that it is adopted for：Gas is NH3、N2And SiH4, gas flow be respectively 2.5sccm,
950sccm and 250sccm, temperature, RF power and pressure are respectively 300 DEG C, 25W and 950mTorr.
The deposit of the passivation layer of this step is not limited to plasma enhanced CVD technology, it would however also be possible to employ electricity
Beamlet evaporation technique or sputtering technology or atomic layer deposition technology.
Step 7. making groove 9, such as Fig. 3 g are performed etching in the passivation layer 8 between grid 7 and drain electrode 5.
The 4th making mask on passivation layer 8, it is blunt between grid 7 and drain electrode 5 using reactive ion etching technology
Change and performed etching on layer, to make groove 9, wherein depth of groove s is 4 μm, and width b is 3.5 μm, bottom portion of groove and barrier layer it
Between be 0.12 μm apart from d, groove is near the distance between the lateral edges a that drains near the lateral edges of grid one and grid
1.386μm；The process conditions that reactive ion etching technology etched recesses are adopted for：CF4Flow is 45sccm, O2Flow is
5sccm, pressure is 15mTorr, and power is 250W.
The etching of this step is not limited to reactive ion etching technology, it would however also be possible to employ sputtering technology or plasma etching
Technology.
Step 8. metal Ti/Ni/Au is deposited on the passivation layer 8 in groove and between source electrode 4 and drain electrode 5 and makes T-shaped grid
Field plate 10, such as Fig. 3 h.
On passivation layer 8 the 5th time making mask, using electron beam evaporation technique in groove and source electrode 4 with drain 5 it
Between passivation layer on deposit metal and make T-shaped grid field plate 10, and T-shaped grid field plate and grid are electrically connected, the metal for being deposited
For Ti/Ni/Au metallic combinations, i.e. lower floor be Ti, middle level be Ni, upper strata be Au, its thickness be 3 μm/0.8 μm/0.2 μm.Wherein
The metal for being deposited will be filled up completely with groove 9, and T-shaped grid field plate 10 is near one lateral edges of drain electrode with groove 9 near one side of drain electrode
The distance between edge c is 4 μm；The electron beam evaporation technique process conditions that adopt of deposit Ti/Ni/Au for：Vacuum less than 1.8 ×
10-3Pa, power bracket is 200～1000W, and evaporation rate is less than
The Metal deposition of this step is not limited to electron beam evaporation technique, it would however also be possible to employ sputtering technology.
Step 9. in the top of T-shaped grid field plate 10 and other area tops deposit SiO of passivation layer 82Make protective layer
11, such as Fig. 3 i.
Using plasma enhanced CVD technology in the top of T-shaped grid field plate 10 and other areas of passivation layer 8
Domain top deposits SiO2Protective layer 11 is made, its thickness is 4 μm, so as to complete the making of whole device；The technique bar that it is adopted
Part is：N2O flows are 850sccm, SiH4Flow is 200sccm, and temperature is 250 DEG C, and RF power is 25W, and pressure is
1100mTorr。
The deposit of the protective layer of this step is not limited to plasma enhanced CVD technology, it would however also be possible to employ electricity
Beamlet evaporation technique or sputtering technology or atomic layer deposition technology.
Embodiment three：Making substrate is silicon, and passivation layer is SiO2, protective layer is SiN, and T-shaped grid field plate is that Ti/Pt/Au is golden
The T-shaped grid field plate transistor with high electron mobility of category combination.
From bottom to top extension AlN makes transition zone 2, such as Fig. 3 a to step A. with GaN material on silicon substrate 1.
A1 the use of metal organic chemical vapor deposition technology in temperature it is) 800 DEG C, pressure is 40Torr, hydrogen flowing quantity
For 4000sccm, ammonia flow is 4000sccm, and silicon source flow is under the process conditions of 25 μm of ol/min, on silicon substrate 1 outward
Prolong the AlN materials that thickness is 200nm；
A2 the use of metal organic chemical vapor deposition technology in temperature it is) 980 DEG C, pressure is 45Torr, hydrogen flowing quantity
For 4000sccm, ammonia flow is 4000sccm, and gallium source flux is under the process conditions of 120 μm of ol/min, on AlN materials outward
Prolong the GaN material that thickness is 4.8 μm, complete the making of transition zone 2.
Step B. deposits from bottom to top Al on transition zone0.1Ga0.9N makes barrier layer 3, such as Fig. 3 b with GaN material.
B1 the use of metal organic chemical vapor deposition technology in temperature it is) 1000 DEG C, pressure is 40Torr, hydrogen flowing quantity
For 4000sccm, ammonia flow is 4000sccm, and gallium source flux is 12 μm of ol/min, and silicon source flow is the technique of 12 μm of ol/min
Under the conditions of, epitaxial thickness is 46nm, the Al that al composition is 0.1 in GaN transition layer 20.1Ga0.9N materials；
B2 the use of metal organic chemical vapor deposition technology in temperature it is) 1000 DEG C, pressure is 40Torr, hydrogen flowing quantity
For 4000sccm, ammonia flow is 4000sccm, and gallium source flux is under the process conditions of 3 μm of ol/min, in Al0.1Ga0.9N materials
Upper epitaxial thickness is the GaN material of 4nm, completes the making of barrier layer 3.
Step C. makes source electrode 4 and drain electrode 5, such as Fig. 3 c in the two ends of barrier layer 3 deposit metal Ti/Al/Ni/Au.
C1) make mask for the first time on barrier layer 3,1.8 × 10 are less than in vacuum using electron beam evaporation technique- 3Pa, power bracket is 200～1000W, and evaporation rate is less thanProcess conditions under, in its two ends deposit metal, wherein institute
The metal of deposit be Ti/Al/Ni/Au metallic combinations, i.e., from bottom to top be respectively Ti, Al, Ni and Au, its thickness be 0.018 μm/
0.135μm/0.046μm/0.052μm；
C2) in N2Atmosphere, temperature is 850 DEG C, and the time, to carry out rapid thermal annealing under the process conditions of 35s, completes source electrode 4
With the making of drain electrode 5.
Step D. performs etching making table top 6, such as Fig. 3 d on the barrier layer 3 on the right of the source electrode left side with drain electrode.
Second making mask on barrier layer 3, using reactive ion etching technology in Cl2Flow is 15sccm, pressure
For 10mTorr, under power is for the process conditions of 100W, perform etching on the barrier layer 3 on the right of the source electrode left side with drain electrode, formed
Table top 6, wherein etching depth are 200nm.
Step E. deposits W metal/Au and makes grid 7, such as Fig. 3 e on the barrier layer 3 between source electrode 4 and drain electrode 5.
Make mask for the third time on barrier layer 3,1.8 × 10 are less than in vacuum using electron beam evaporation technique-3Pa, work(
Rate scope is 200～1000W, and evaporation rate is less thanProcess conditions under, source electrode 4 and drain electrode 5 between barrier layer 3
Upper deposit metal, makes grid 7, and it is Au for Ni, upper strata that the metal for being deposited is Ni/Au metallic combinations, i.e. lower floor, and its thickness is
0.046μm/0.21μm。
Step F. is in source electrode top, drain electrode top, grid top, the top of barrier layer 3 between grid and source electrode, and grid
The top of barrier layer 3 deposit SiO between pole and drain electrode2Material makes passivation layer 8, such as Fig. 3 f.
Using plasma enhanced CVD technology in N2O flows are 850sccm, SiH4Flow is 200sccm,
Temperature is 250 DEG C, and RF power is 25W, under pressure is for the process conditions of 1100mTorr, in source electrode top, drain electrode top, grid
The top of barrier layer 3 between top, grid and source electrode, and the top of barrier layer 3 between grid and drain electrode, deposition thickness is
8.49 μm of SiO2Make passivation layer 8.
Step G. performs etching making groove 9, such as Fig. 3 g in the passivation layer 8 between grid 7 and drain electrode 5.
The 4th making mask on passivation layer 8, using reactive ion etching technology in CF4Flow is 20sccm, O2Flow
For 2sccm, pressure is 20mTorr, under bias voltage is for the process conditions of 100V, in the passivation layer between grid 7 and drain electrode 5
Perform etching, to make groove 9, wherein depth of groove s is 8.2 μm, and width b is 6.3 μm, between bottom portion of groove and barrier layer
It it is 0.29 μm apart from d, groove is 4.416 μm near the distance between one lateral edges of drain electrode a near the lateral edges of grid one and grid.
Step H. deposits Ti/Pt/Au on the passivation layer in groove and between source electrode 4 and drain electrode 5, makes T-shaped grid field plate
10, such as Fig. 3 h.
The 5th making mask, 1.8 × 10 are less than using electron beam evaporation technique in vacuum on passivation layer 8-3Pa, work(
Rate scope is 200～1000W, and evaporation rate is less thanProcess conditions under, in groove and source electrode 4 and drain electrode 5 between
Metal is deposited on passivation layer and makes T-shaped grid field plate 10, and T-shaped grid field plate and grid are electrically connected, the metal for being deposited is thickness
Spend for Ti/Pt/Au metallic combinations, i.e. lower floor be Ti, middle level be Pt, upper strata be Au, its thickness be 6 μm/1.7 μm/0.5 μm, with
Make T-shaped grid field plate 10.The metal for wherein being deposited will be filled up completely with groove 9, T-shaped grid field plate 10 near one lateral edges of drain electrode with
Groove 9 is 7.9 μm near the distance between one lateral edges of drain electrode c.
Step I. makes protective layer 11 in the top of T-shaped grid field plate 10 and other area tops deposit SiN of passivation layer 8,
Such as Fig. 3 i.
Using plasma enhanced CVD technology gas be NH3、N2And SiH4, gas flow is respectively
2.5sccm, 950sccm and 250sccm, temperature, RF power and pressure are respectively 300 DEG C, the process conditions of 25W and 950mTorr
Under, protective layer 11 is made in other area tops deposit SiN of the top of T-shaped grid field plate 10 and passivation layer 8, its thickness is 8 μm,
So as to complete the making of whole device.
The effect of the present invention can be further illustrated by following emulation.
To in the barrier layer of HEMT and the barrier layer of device of the present invention using traditional grid field plate
Electric field is emulated, as a result such as Fig. 4, wherein traditional grid field plate effective length L and the effective total length phase of T-shaped grid field plate of the present invention
Deng.
As seen from Figure 4：Using electric field curve of the HEMT of traditional grid field plate in barrier layer
2 approximately equalised peak electric fields have been only formed, the area very little that its electric field curve in barrier layer is covered, and it is of the invention
Electric field curve of the device in barrier layer defines 3 approximately equalised peak electric fields so that device of the present invention is in barrier layer
The area that covered of electric field curve greatly increase, because the area approximation that the electric field curve in barrier layer is covered is equal to device
The breakdown voltage of part, the breakdown voltage for illustrating device of the present invention is far longer than the high electron mobility crystal using traditional grid field plate
The breakdown voltage of pipe.
For those skilled in the art, after present invention and principle has been understood, can be without departing substantially from this
In the case of bright principle and scope, the method according to the invention carries out various amendments and change in form and details, but
These amendments and change based on the present invention are still within the claims of the present invention.
Claims (2)
1. a kind of T-shaped grid field plate transistor with high electron mobility, includes from bottom to top：Substrate (1), transition zone (2), barrier layer
(3), passivation layer (8) and protective layer (11), are deposited with source electrode (4), drain electrode (5) and grid (7), potential barrier above barrier layer (3)
Table top (6) is carved with the side of layer (3), and land depth is more than barrier layer thickness, it is characterised in that be carved with passivation layer (8) recessed
Groove (9), depth s of the groove (9) is 0.11～8.2 μm, and width b is 0.42～6.3 μm, groove (9) bottom and barrier layer (3)
The distance between d be 0.057～0.29 μm, groove (9) near the lateral edges of grid one and grid (7) near one lateral edges of drain electrode it
Between apart from a be s × (d)0.5；T-shaped grid field plate (10) is deposited between passivation layer (8) and protective layer (11), the T-shaped grid field plate
It is completely filled in groove (9) with grid (7) electrical connection, and lower end, groove (9) is near one lateral edges of drain electrode and T-shaped grid field
Plate is 0.62～7.9 μm near the distance between one lateral edges of drain electrode c.
2. a kind of method for making T-shaped grid field plate transistor with high electron mobility, including following process：
The first step, the extension GaN base semiconductor material with wide forbidden band on substrate (1) forms transition zone (2)；
Second step, the extension GaN base semiconductor material with wide forbidden band on transition zone forms barrier layer (3)；
3rd step, on barrier layer (3) mask is made for the first time, and metal is deposited at the two ends of barrier layer (3) using the mask, then
In N2Rapid thermal annealing is carried out in atmosphere, source electrode (4) and drain electrode (5) are made respectively；
4th step, second making mask on barrier layer (3), using barrier layer of the mask on the left of source electrode, on the right side of drain electrode
On perform etching, and etched area depth be more than barrier layer thickness, formed table top (6)；
5th step, on barrier layer (3) mask is made for the third time, is formed sediment using on mask barrier layer between the source and drain
Product metal, makes grid (7)；
6th step, respectively in source electrode top, drain electrode top, grid top, the barrier layer top between grid and source electrode, and grid
Barrier layer top deposit passivation layer (8) between pole and drain electrode；
7th step, the 4th making mask, the passivation layer (8) using the mask between grid and drain electrode on passivation layer (8)
Inside perform etching, to make depth s as 0.11～8.2 μm, width b is 0.42～6.3 μm of groove (9), groove (9) bottom with
The distance between barrier layer (3) d is 0.057～0.29 μm, and the groove is near the lateral edges of grid one and grid near drain electrode side
The distance between edge a is s × (d)0.5, wherein s is depth of groove, and d is the distance between bottom portion of groove and barrier layer；
8th step, the 5th making mask, blunt and source electrode and drain electrode between in groove using the mask on passivation layer (8)
Change and deposit metal on layer, the metal for being deposited will be filled up completely with groove, to form the T-shaped grid field plate that thickness is 0.11～8.2 μm
(10), groove is 0.62～7.9 μm near the distance between one lateral edges of drain electrode c with T-shaped grid field plate near one lateral edges of drain electrode,
And be electrically connected T-shaped grid field plate (10) and grid (7)；
9th step, in T-shaped grid field plate (10) top and other area top deposit insulating dielectric materials of passivation layer (8), forms
Protective layer (11), completes the making of whole device.
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