CN104393043B - High-electron-mobility transistor of gallium nitride-based right-angle drain field plate - Google Patents
High-electron-mobility transistor of gallium nitride-based right-angle drain field plate Download PDFInfo
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- 229910002601 GaN Inorganic materials 0.000 title abstract description 36
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title abstract description 3
- 239000010410 layer Substances 0.000 claims abstract description 197
- 238000002161 passivation Methods 0.000 claims abstract description 64
- 238000000034 method Methods 0.000 claims abstract description 63
- 230000004888 barrier function Effects 0.000 claims abstract description 57
- 239000011241 protective layer Substances 0.000 claims abstract description 21
- 230000007704 transition Effects 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000002184 metal Substances 0.000 claims description 60
- 229910052751 metal Inorganic materials 0.000 claims description 60
- 239000000463 material Substances 0.000 claims description 27
- 238000005530 etching Methods 0.000 claims description 22
- 239000004065 semiconductor Substances 0.000 claims description 12
- 229910052737 gold Inorganic materials 0.000 claims description 10
- 239000003989 dielectric material Substances 0.000 claims description 6
- 238000004151 rapid thermal annealing Methods 0.000 claims description 6
- 229910052594 sapphire Inorganic materials 0.000 claims description 5
- 239000010980 sapphire Substances 0.000 claims description 5
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 5
- 239000012298 atmosphere Substances 0.000 claims description 4
- 238000009413 insulation Methods 0.000 claims description 3
- 239000002210 silicon-based material Substances 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 abstract description 45
- 230000015556 catabolic process Effects 0.000 abstract description 32
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 230000008569 process Effects 0.000 description 36
- 239000010931 gold Substances 0.000 description 32
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 20
- 238000005566 electron beam evaporation Methods 0.000 description 12
- 238000005229 chemical vapour deposition Methods 0.000 description 11
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 229910021529 ammonia Inorganic materials 0.000 description 9
- 230000004907 flux Effects 0.000 description 9
- 229910052739 hydrogen Inorganic materials 0.000 description 9
- 239000001257 hydrogen Substances 0.000 description 9
- 238000004544 sputter deposition Methods 0.000 description 9
- 230000005684 electric field Effects 0.000 description 8
- 230000008020 evaporation Effects 0.000 description 8
- 238000001704 evaporation Methods 0.000 description 8
- 239000007789 gas Substances 0.000 description 8
- 238000001020 plasma etching Methods 0.000 description 8
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 7
- 229910052593 corundum Inorganic materials 0.000 description 7
- 229910052733 gallium Inorganic materials 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 229910001845 yogo sapphire Inorganic materials 0.000 description 7
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 6
- 238000000231 atomic layer deposition Methods 0.000 description 5
- 229910052681 coesite Inorganic materials 0.000 description 5
- 229910052906 cristobalite Inorganic materials 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 238000001451 molecular beam epitaxy Methods 0.000 description 5
- 238000011160 research Methods 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 229910052682 stishovite Inorganic materials 0.000 description 5
- 229910052905 tridymite Inorganic materials 0.000 description 5
- 230000000903 blocking effect Effects 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 238000001465 metallisation Methods 0.000 description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- 239000012159 carrier gas Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 229910002704 AlGaN Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 150000004678 hydrides Chemical class 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 235000010724 Wisteria floribunda Nutrition 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000004223 radioprotective effect Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- HYXGAEYDKFCVMU-UHFFFAOYSA-N scandium(III) oxide Inorganic materials O=[Sc]O[Sc]=O HYXGAEYDKFCVMU-UHFFFAOYSA-N 0.000 description 1
- 239000013049 sediment Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N titanium dioxide Inorganic materials O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention discloses a high-electron-mobility transistor of a gallium nitride-based right-angle drain field plate in order to mainly solve the problem that a technique for realizing high breakdown voltage is complex in the existing field plate technology. The transistor comprises a substrate (1), a transition layer (2), a barrier layer (3), a source electrode (4), a schottky drain electrode (5), a table surface (6), an insulating dielectric layer (7), a grid electrode (8), a passivation layer (9) and a protective layer (12). A drain groove (10) is engraved in the passivation layer (9); a right-angle drain field plate (11) is deposited between the passivation layer (9) and the protective layer (12); the edge of one side of the right-angle drain field plate (11), close to the schottky drain electrode, is aligned to the edge of one side of the drain groove (10) close to the schottky drain electrode; the right-angle drain field plate (11) is electrically connected with the schottky drain electrode (5), and the lower end of the right-angle drain field plate (11) is totally filled in the drain groove (10). The transistor disclosed by the invention has the advantages of being simple in manufacturing process, good in reverse characteristics and high in rate of finished products, and can be used as a switch element.
Description
Technical field
The invention belongs to microelectronics technology, is related to semiconductor device, the high electricity of gallio right angle leakage field plate is particularly nitrogenized
Transport factor transistor, can be used as the basic device of power electronic system.
Technical background
Power semiconductor is the critical elements of power electronic system, is to carry out electric treatable effective tool.In recent years
Come, with becoming increasingly conspicuous for the energy and environmental problem, research and development novel high-performance, low-loss power device become raising electric energy profit
With one of rate, energy saving, the effective way of alleviating energy crisis.However, in power device research, at a high speed, high pressure with it is low
Serious restricting relation is there is between conducting resistance, rationally, to effectively improve this restricting relation be to improve device globality
The key of energy.As market constantly proposes the requirement of higher efficiency, smaller volume, higher frequency, traditional Si base to power system
Semiconductor power device performance has approached its theoretical limit.In order to be able to further reducing chip area, improving operating frequency, improve
Operating temperature, reduction conducting resistance, raising breakdown voltage, reduction machine volume, raising overall efficiency, with gallium nitride as representative
Semiconductor material with wide forbidden band, drifts about by the electronics saturation of its bigger energy gap, higher critical breakdown electric field and Geng Gao
Speed, and the outstanding advantages such as stable chemical performance, high temperature resistant, radioprotective, show one's talent in terms of high performance power device is prepared,
Application potential is huge.Especially with the HEMT of GaN base heterojunction structure, i.e. GaN base HEMT device, more
It is, because of characteristics such as its low on-resistance, senior engineer's working frequencies, electronics of future generation to be met more high-power to power device, higher
The requirement of frequency, smaller volume and more severe hot operation, has wide and special application prospect in economy and military field.
However, there is inherent shortcoming in conventional GaN base HEMT device structure, device channel electric field intensity can be caused in deformity
, especially there is high peak electric field near vicinity in device grids in distribution.This causes actual GaN base HEMT device to exist
In the case of applying positive drain voltage, i.e., positive OFF state, forward break down voltage be often far below theoretical eapectation, and there is electric current
The integrity problems such as avalanche, inverse piezoelectric effect, seriously constrain application and development in field of power electronics.In order to solve with
Upper problem, domestic and international researchers propose numerous methods, and field plate structure is that wherein effect is the most notable, is most widely used
One kind.Field plate structure is successfully applied to GaN base HEMT power device by N.Q.Zhang of U.S. UCSB in 2000 et al. first
In, overlapping gate power device is developed, saturation output current is 500mA/mm, and up to 570V, this is at that time to breakdown voltage
Reported breakdown voltage highest GaN device, referring to High breakdown GaN HEMT with overlapping gate
structure,IEEE Electron Device Letters,Vol.21,No.9,pp.421-423,2000.Subsequently, various countries
Research institution expands one after another the research work of correlation, and the U.S. and Japan are the main leaders in the field.It is main in the U.S.
If UCSB, Nan Ka university, Cornell University and famous IR companies of power electronic devices manufacturer etc. are engaged in the research.
Japan is relative to start late, but their work to this respect are paid much attention to, fund input great efforts, and it is numerous to be engaged in mechanism, bag
Include：The major companies such as Toshiba, Furukawa, Panasonic, Toyota and Fuji.With going deep into for research, researchers have found correspondingly to increase field
Plate length, can improve device electric breakdown strength.But the increase of field plate length can make field plate efficiency, i.e. breakdown voltage longer than field plate
Degree, constantly reduces, that is, field plate improves the ability of device electric breakdown strength as the increase of field plate length gradually tends to saturation, joins
See Enhancement of breakdown voltage in AlGaN/GaN high electron mobility
transistors using a field plate,IEEE Transactions on Electron Devices,Vol.48,
No.8, pp.1515-1521,2001, and Development and characteristic analysis of a
field-plated Al2O3/AlInN/GaN MOS HEMT,Chinese Physics B,Vol.20,No.1,
pp.0172031-0172035,2011.Therefore, in order to further improve device electric breakdown strength, while field plate efficiency is taken into account, 2004
The H.L.Xing in year UCSB et al. proposes a kind of double-deck field plate structure, the double-layer grid field plate GaN base HEMT device that they develop
The up to breakdown voltage of 900V, maximum output current 700mA/mm, referring to High breakdown voltage can be obtained
AlGaN-GaN HEMTs achieved by multiple field plates,IEEE Electron Device
Letters,Vol.25,No.4,pp.161-163,2004.And this double-deck field plate structure become it is current in the world for
Improve GaN base power device breakdown characteristics, improve the main flow field plate techniques of device overall performance.
In actual applications, researchers also have found to be permitted in electric automobile, power management system, S power-like amplifiers etc.
In many technical fields, power device is generally required with very strong reverse blocking, i.e., reverse OFF state, ability, that is, wish device
Part has very high negative drain breakdown voltage, i.e. breakdown reverse voltage under OFF state.And common monolayer or double-deck field plate are all
It is to be connected with grid or source electrode, therefore when device drain applies low-down backward voltage, device grids positive will be opened,
And by very big gate current, so as to cause component failure.Therefore, in order to improve the reverse blocking capability of power device, 2009
Eldad Bahat-Treidel et al. propose a kind of power device of employing Schottky drain, referring to AlGaN/GaN HEMT
With Integrated Recessed Schottky-Drain Protection Diode,IEEE Electron Device
Letters,Vol.30,No.9,pp.901-903,2009.However, Schottky drain is in terms of device reverse blocking voltage is improved
Ability it is extremely limited, therefore in order to more effectively improve the reverse blocking capability of power device, researchers are by field plate techniques
Device drain has been incorporated into, leakage field plate structure has been defined.Wataru Saito in 2005 et al. propose a kind of using source field plate
With leakage field plate hetero-junctions power device, referring to Design optimization of high breakdown voltage
AlGaN-GaN power HEMT on an insulating substrate for RONA-VB tradeoff
characteristics,IEEE Transactions on Electron Devices,Vol.52,No.1,pp.106-111,
2005.However, due to the ability of the leakage field plate in terms of device electric breakdown strength is improved of monolayer it is still limited, therefore by double-deck field plate
Structure constitutes double-deck leakage field in combination with leakage field plate hetero-junctions power device, that is, using the leakage field plate of double-deck field plate structure
Plate power device, it is possible to achieve the further lifting of device reverse breakdown voltage, this has larger application potential.However, double
The complex process of layer field plate HEMT power devices, manufacturing cost is higher, and the making of each layer of field plate is required for photoetching, deposit gold
The processing steps such as category, deposit dielectric passivation.And it is maximum to realize breakdown voltage to optimize dielectric material thickness under each layer field plate
Change, it is necessary to carry out loaded down with trivial details process debugging and optimization, therefore considerably increase the difficulty of device manufacture, reduce the finished product of device
Rate.
The content of the invention
It is an object of the invention to overcome the shortcomings of above-mentioned prior art, there is provided a kind of simple structure, breakdown reverse voltage
The high nitridation gallio right angle leakage field plate transistor with high electron mobility of high, field plate efficiency high and reliability, to reduce element manufacturing
Difficulty, improves the reverse breakdown characteristics of device, improves device yield.
For achieving the above object, the device architecture that the present invention is provided is different using GaN base semiconductor material with wide forbidden band composition
Matter junction structure, includes from bottom to top：Substrate, transition zone, barrier layer, insulating medium layer, passivation layer and protective layer, barrier layer it is upper
Face is deposited with source electrode and Schottky drain, and table top is carved with the side of barrier layer, and land depth is more than barrier layer thickness, and insulation is situated between
Grid is deposited with matter layer, it is characterised in that：
Bakie is carved with passivation layer；
Leakage field plate in right angle is deposited between passivation layer and protective layer；
The right angle leakage field plate is electrically connected with Schottky drain, and lower end is completely filled in bakie, the right angle leakage field
Plate is near the lateral edges of Schottky drain one and bakie near the side edge-justified calibrations of Schottky drain one.
Preferably, the thickness e of described insulating medium layer is 2～93nm.
Preferably, described bakie depth s is 0.71～13.9 μm, width b is 1.14～12.7 μm.
Preferably, the distance between the bottom of described bakie and insulating medium layer d is 0.122～3.01 μm.
Preferably, described right angle leaks field plate near the lateral edges of grid one and bakie between the lateral edges of grid one
It it is 1.21～14.6 μm apart from c.
Preferably, the bakie near the lateral edges of Schottky drain one and Schottky drain near the lateral edges of grid one it
Between apart from a be s × (d+e × ε2/ε1)0.5, wherein s for bakie depth, d between bakie bottom and insulating medium layer away from
From, e for insulating medium layer thickness, ε1For the relative dielectric constant of insulating medium layer, ε2For the relative dielectric constant of passivation layer.
For achieving the above object, the present invention makes the method that nitridation gallio right angle leaks field plate transistor with high electron mobility,
Including following process：
The first step, the extension GaN base semiconductor material with wide forbidden band on substrate forms transition zone；
Second step, the extension GaN base semiconductor material with wide forbidden band on transition zone forms barrier layer；
3rd step, makes for the first time mask on barrier layer, using the mask barrier layer left end deposit metal, then
N2Rapid thermal annealing is carried out in atmosphere, source electrode is made；
4th step, second making mask on barrier layer deposits metal using right-hand member of the mask in barrier layer, makes
Schottky drain；
5th step, makes for the third time mask on barrier layer, using the mask on the left of source electrode with Schottky drain on the right side of
Barrier layer on perform etching, and etching depth be more than barrier layer thickness, formed table top；
6th step, in other area top deposit dielectrics of source electrode top, Schottky drain top and passivation layer
Material, forms insulating medium layer；
7th step, the 4th making mask on insulating medium layer, using the mask between source electrode and Schottky drain
Insulating medium layer on deposit metal, make grid；
8th step, respectively in grid top and other area top deposit passivation layers of insulating medium layer；
9th step, over the passivation layer the 5th making mask, blunt between grid and Schottky drain using the mask
Change and performed etching in layer, to make bakie, and bakie near the lateral edges of Schottky drain one and Schottky drain near grid one
The distance between lateral edges a is s × (d+e × ε2/ε1)0.5, wherein s is the depth of bakie, and d is bakie bottom and insulating medium layer
The distance between, e for insulating medium layer thickness, ε1For the relative dielectric constant of insulating medium layer, ε2For relative Jie of passivation layer
Electric constant；
Tenth step, makes mask the 6th time over the passivation layer, using the mask is in bakie and grid leaks with Schottky
Metal is deposited on passivation layer between pole, the metal for being deposited is filled up completely with bakie, the metal is near the side of Schottky drain one
Edge, near the side edge-justified calibrations of Schottky drain one, to form the right angle that thickness is 0.71～13.9 μm field plate is leaked with bakie, and will
Leak field plate and be electrically connected with Schottky drain in right angle；
11st step, at right angle other area top deposit insulating dielectric materials of field plate top and passivation layer are leaked, and are formed
Protective layer, completes the making of whole device.
Device of the present invention is compared with advantages below with the HEMT that field plate is leaked using tradition：
1. the breakdown reverse voltage of device is further increased.
The present invention due to using right angle leak field plate structure, make device in reverse OFF state working condition when, barrier layer
Surface potential gradually rises from Schottky drain to grid, so as to increased barrier layer in depletion region, i.e. high resistance area, area,
The distribution of depletion region is improved, promotes the depletion region between grid and Schottky drain in barrier layer to undertake bigger negative drain-source electricity
Pressure, so as to substantially increase the breakdown reverse voltage of device.
2. gate leakage current is further reduced, device reliability in reverse OFF state is improve.
The present invention due to using right angle leak field plate structure, make device in reverse OFF state working condition when, device gesture
The distribution of electric field line in barrier layer depletion region has also obtained more effective modulation, and Schottky drain is near the side of grid one in device
Edge, right angle leakage field plate can all produce a peak electric field near the lateral edges of grid one and bakie near the lateral edges of grid one, and
And by adjusting thickness, bakie depth and width, the bakie of the passivation layer below right angle leakage field plate near Schottky drain side
Edge is with Schottky drain near the distance between lateral edges of grid one and right angle leakage field plate near the lateral edges of grid one and leakage
Groove can cause above-mentioned each peak electric field equal and less than GaN base broad stopband half near the distance between lateral edges of grid one
The breakdown electric field of conductor material, so as to reduce to greatest extent grid near Schottky drain side edge collected by electricity
Field wire, significantly reduces the electric field intensity at this, substantially reduce gate leakage current so that device is in reverse OFF state
Reliability and breakdown characteristics are significantly increased.
3. process is simple, it is easy to accomplish, improve yield rate.
The making of right angle leakage field plate in device architecture of the present invention only needs the step process just can to complete, it is to avoid traditional stack layers
The process complications problem that field plate structure is brought, substantially increases the yield rate of device.
Simulation result shows that the breakdown reverse voltage of device of the present invention is far longer than and is moved using the high electronics of tradition leakage field plate
The breakdown reverse voltage of shifting rate transistor.
The technology contents and effect of the present invention are further illustrated below in conjunction with drawings and Examples.
Description of the drawings
Fig. 1 is the structure chart of the HEMT using tradition leakage field plate；
Fig. 2 is the structure chart that present invention nitridation gallio right angle leaks field plate transistor with high electron mobility；
Fig. 3 is the Making programme figure that present invention nitridation gallio right angle leaks field plate transistor with high electron mobility；
Fig. 4 is to the reverse breakdown curve chart obtained by traditional devices and device simulation of the present invention.
Specific embodiment
With reference to Fig. 2, the present invention is that it includes based on GaN wide bandgap semiconductor heterojunction structures：Substrate 1, transition zone 2, gesture
Barrier layer 3, source electrode 4, Schottky drain 5, table top 6, insulating medium layer 7, grid 8, passivation layer 9, bakie 10, right angle leakage field plate 11 with
Protective layer 12.Substrate 1, transition zone 2 are to be distributed from bottom to top with barrier layer 3；Source electrode 4 is deposited on barrier layer 3 with Schottky drain 5
On；Table top 6 is produced on source electrode left side and Schottky drain right side, and the land depth is more than barrier layer thickness；7 points of insulating medium layer
Other area tops of the top of source electrode 4, the top of Schottky drain 5 and barrier layer are not covered in, the thickness e of insulating medium layer is
2～93nm；Grid 8 is deposited on the insulating medium layer 7 between source electrode and Schottky drain；Passivation layer 9 is respectively overlay in grid
Top and other area tops of insulating medium layer；Bakie 10 is located in the passivation layer 9 between grid and Schottky drain；Bakie
Depth s be 0.71～13.9 μm, width b is 1.14～12.7 μm, and the distance between bakie bottom and insulating medium layer d is
0.122～3.01 μm；Bakie near the lateral edges of Schottky drain one and Schottky drain between the lateral edges of grid one away from
It is s × (d+e × ε from a2/ε1)0.5, wherein s is the depth of bakie, and d is the distance between bakie bottom and insulating medium layer, and e is
The thickness of insulating medium layer, ε1For the relative dielectric constant of insulating medium layer, ε2For the relative dielectric constant of passivation layer；Leak at right angle
Field plate 11 is deposited between passivation layer 9 and protective layer 12, and the right angle leakage field plate 11 is electrically connected with Schottky drain 5, and lower end
It is completely filled in bakie 10, right angle leaks field plate near the lateral edges of Schottky drain one and bakie near the side of Schottky drain one
Edge aligns；Right angle leak field plate near the lateral edges of grid one and bakie near the distance between the lateral edges of grid one c be 1.21～
14.6 μm, protective layer 12 is covered each by the top in the right angle leakage top of field plate 11 and other regions of passivation layer.
The substrate 1 of above-mentioned device is using sapphire or carborundum or silicon materials；If transition zone 2 is identical or different by dried layer
GaN base semiconductor material with wide forbidden band is constituted, and its thickness is 1～5 μm；If barrier layer 3 is prohibited by the identical or different GaN base width of dried layer
Carrying semiconductor material is constituted, and its thickness is 5～50nm；Insulating medium layer 7, passivation layer 9 and protective layer 12 adopt SiO2、SiN、
Al2O3、Sc2O3、HfO2、TiO2In any one or other insulating dielectric materials, the thickness of passivation layer for bakie depth s and
The distance between bakie bottom and insulating medium layer d sums, i.e., 0.832～16.91 μm；The thickness of protective layer is 0.72～9.6 μ
m；Right angle leakage field plate 11 is constituted using the combination of three layers of different metal, and its thickness is 0.71～13.9 μm.
With reference to Fig. 3, the present invention makes the flow process that nitridation gallio right angle leaks field plate transistor with high electron mobility, provides as follows
Three kinds of embodiments：
Embodiment one：Making substrate is sapphire, and insulating medium layer is SiO2, passivation layer is Al2O3, protective layer is SiN,
Right angle leakage field plate leaks field plate transistor with high electron mobility for the nitridation gallio right angle of Ti/Mo/Au metallic combinations.
From bottom to top extension GaN material makes transition zone 2, such as Fig. 3 a to step 1. in Sapphire Substrate 1.
Using metal organic chemical vapor deposition technology, epitaxial thickness is 1 μm of undoped p mistake in Sapphire Substrate 1
Layer 2 is crossed, the transition zone is respectively from bottom to top 30nm and 0.97 μm of GaN material by thickness and is constituted.Extension lower floor GaN material is adopted
Process conditions are：Temperature is 530 DEG C, and pressure is 45Torr, and hydrogen flowing quantity is 4400sccm, and ammonia flow is
4400sccm, gallium source flux is 22 μm of ol/min；The process conditions that extension upper strata GaN material is adopted for：Temperature is 960 DEG C, pressure
It is by force 45Torr, hydrogen flowing quantity is 4400sccm, and ammonia flow is 4400sccm, and gallium source flux is 120 μm of ol/min.
Step 2. deposits unadulterated Al in GaN transition layer 20.5Ga0.5N makes barrier layer 3, such as Fig. 3 b.
Using metal organic chemical vapor deposition technology, deposition thickness is 5nm in GaN transition layer 2, and al composition is
0.5 undoped p Al0.5Ga0.5N barrier layers 3, the process conditions that it is adopted for：Temperature is 980 DEG C, and pressure is 45Torr, hydrogen
Flow is 4400sccm, and ammonia flow is 4400sccm, and gallium source flux is 35 μm of ol/min, and silicon source flow is 7 μm of ol/min.
Step 3. makes source electrode 4, such as Fig. 3 c in the left end deposit metal Ti/Al/Ni/Au of barrier layer 3.
In Al0.5Ga0.5Mask is made on N barrier layers 3 for the first time, using electron beam evaporation technique in its left end deposit gold
Category, then in N2Rapid thermal annealing is carried out in atmosphere, source electrode 4 is made, wherein the metal for being deposited is Ti/Al/Ni/Au metal groups
Close, i.e., be respectively Ti, Al, Ni and Au from bottom to top, its thickness is 0.018 μm/0.135 μm/0.046 μm/0.052 μm.Deposit
The process conditions that metal is adopted for：Vacuum is less than 1.8 × 10-3Pa, power bracket is 200～1000W, and evaporation rate is less thanThe process conditions that rapid thermal annealing is adopted for：Temperature is 850 DEG C, and the time is 35s.
Step 4. makes Schottky drain 5, such as Fig. 3 d in the right-hand member deposit W metal/Au of barrier layer 3.
In Al0.5Ga0.5Second making mask on N barrier layers 3, using electron beam evaporation technique in its right-hand member deposit gold
Category, make Schottky drain 5, wherein the metal for being deposited be Ni/Au metallic combinations, i.e. lower floor be Ni, upper strata be Au, its thickness
For 0.046 μm/0.21 μm.The process conditions that adopt of deposit metal for：Vacuum is less than 1.8 × 10-3Pa, power bracket is 200
～1000W, evaporation rate is less than
Step 5. performs etching making table top 6, such as Fig. 3 e on the barrier layer on the right of the source electrode left side and Schottky drain.
In Al0.5Ga0.5Mask is made on N barrier layers 3 for the third time, using reactive ion etching technology in the source electrode left side and Xiao
Perform etching on barrier layer on the right of Te Ji drain electrodes, form table top 6, etching depth is 10nm.The process conditions that adopt of etching for：
Cl2Flow is 15sccm, and pressure is 10mTorr, and power is 100W.
Other area top deposit SiO of the step 6. on source electrode top, Schottky drain top and barrier layer2Dielectric
Layer 7, such as Fig. 3 f.
Using plasma enhanced CVD technology source electrode top, Schottky drain top and barrier layer its
He is area top deposit SiO2Insulating medium layer 7, its thickness is 2nm, deposit the process conditions that adopt for：Gas is N2O and
SiH4, gas flow is respectively 850sccm and 200sccm, and temperature is 250 DEG C, RF power 25W, and pressure is 1100mTorr.
W metal/Au is deposited on insulating medium layer of the step 7. between source electrode and Schottky drain and makes grid 8, such as schemed
3g。
The 4th making mask on insulating medium layer, using electron beam evaporation technique between source electrode and Schottky drain
Insulating medium layer on deposit metal, make grid 8, wherein the metal for being deposited is Ni/Au metallic combinations, i.e. lower floor be Ni,
Upper strata is Au, and its thickness is 0.046 μm/0.21 μm.The process conditions that adopt of deposit metal for：Vacuum is less than 1.8 × 10- 3Pa, power bracket is 200～1000W, and evaporation rate is less than
Step 8. is in grid top and other area top deposit passivation layers 9 of insulating medium layer, such as Fig. 3 h.
Other area tops of grid top and insulating medium layer are covered each by using atomic layer deposition technology, complete to form sediment
Product thickness is 0.832 μm of Al2O3Passivation layer 9.The process conditions that adopt of deposit passivation layer for：With TMA and H2O is reaction source, is carried
Gas is N2, carrier gas flux is 200sccm, and underlayer temperature is 300 DEG C, and air pressure is 700Pa.
Step 9. is performed etching in the passivation layer between grid 8 and Schottky drain 5, makes bakie 10, such as Fig. 3 i.
The 5th making mask on passivation layer 9, using reactive ion etching technology grid 8 and Schottky drain 5 it
Between passivation layer 9 in perform etching, to make bakie 10, the depth of the bakie is 0.71 μm, and width is 1.14 μm, the bottom of bakie
The distance between portion and insulating medium layer are 0.122 μm, and bakie is close near the lateral edges of Schottky drain one and Schottky drain
The distance between lateral edges of grid one are 0.253 μm.The process conditions that adopt of etching for：CF4Flow is 45sccm, O2Flow is
5sccm, pressure is 15mTorr, and power is 250W.
Passivation layer 9 top deposit metal Ti/ of the step 10. in bakie 10 and between grid 8 and Schottky drain 5
Mo/Au forms right angle leakage field plate 11, such as Fig. 3 j.
The 6th making mask on passivation layer 9, using electron beam evaporation technique in the bakie 10 and grid 8 and Xiao Te
Metal is deposited on passivation layer between base drain electrode 5, the metal leaks near the lateral edges of Schottky drain one and bakie near Schottky
The side edge-justified calibrations of pole one, form right angle leakage field plate 11, and right angle leakage field plate and Schottky drain are electrically connected, the gold for being deposited
Belong to for Ti/Mo/Au metallic combinations, i.e. lower floor be Ti, middle level be Mo, upper strata be Au, its thickness be 0.34 μm/0.27 μm/0.1 μ
m.The metal for wherein being deposited will be filled up completely with bakie 10.Field plate is leaked near the lateral edges of grid one and bakie near grid one in right angle
The distance between lateral edges are 1.21 μm.The process conditions that adopt of deposit metal for：Vacuum is less than 1.8 × 10-3Pa, power model
Enclose for 200～1000W, evaporation rate is less than
Step 11. makes protective layer 12 in other area tops deposit SiN that right angle leaks the top of field plate 11 and passivation layer 9,
Such as Fig. 3 k.
Other regions of the top of field plate 11 and passivation layer 9 are leaked using plasma enhanced CVD technology at right angle
Upper deposit SiN forms protective layer 12, and its thickness is 0.72 μm, so as to complete the making of whole device, deposits what protective layer was adopted
Process conditions are：Gas is NH3、N2And SiH4, gas flow is respectively 2.5sccm, 950sccm and 250sccm, temperature, RF work(
Rate and pressure are respectively 300 DEG C, 25W and 950mTorr.
Embodiment two：Making substrate is carborundum, and insulating medium layer is Al2O3, passivation layer is SiO2, protective layer is SiN,
Right angle leakage field plate leaks field plate transistor with high electron mobility for the nitridation gallio right angle of Ti/Ni/Au metallic combinations.
Step one. from bottom to top extension AlN makes transition zone 2, such as Fig. 3 a with GaN material in silicon carbide substrates 1.
1.1) using metal organic chemical vapor deposition technology, epitaxial thickness is not mixing for 50nm in silicon carbide substrates 1
Miscellaneous AlN materials；The process conditions of its extension are：Temperature is 1000 DEG C, and pressure is 45Torr, and hydrogen flowing quantity is 4600sccm, ammonia
Throughput is 4600sccm, and silicon source flow is 5 μm of ol/min；
1.2) using metal organic chemical vapor deposition technology, epitaxial thickness is 2.45 μm of GaN materials on AlN materials
Material, completes the making of transition zone 2；The process conditions of its extension are：Temperature is 1000 DEG C, and pressure is 45Torr, and hydrogen flowing quantity is
4600sccm, ammonia flow is 4600sccm, and gallium source flux is 120 μm of ol/min.
The extension of this step is not limited to metal organic chemical vapor deposition technology, it would however also be possible to employ molecular beam epitaxy skill
Art or hydride gas-phase epitaxy technology.
Step 2. extension Al from bottom to top on transition zone 20.3Ga0.7N and GaN material make barrier layer 3, such as Fig. 3 b.
2.1) using metal organic chemical vapor deposition technology, deposition thickness is that 27nm, al composition are on transition zone 2
0.3 Al0.3Ga0.7N materials；The process conditions of its extension are：Temperature is 1100 DEG C, and pressure is 45Torr, and hydrogen flowing quantity is
4600sccm, ammonia flow is 4600sccm, and gallium source flux is 16 μm of ol/min, and silicon source flow is 8 μm of ol/min；
2.2) using metal organic chemical vapor deposition technology in Al0.3Ga0.7Epitaxial thickness is the GaN of 3nm on N materials
Material, completes the making of barrier layer 3；The process conditions of its extension are：Temperature is 1100 DEG C, and pressure is 45Torr, hydrogen flowing quantity
For 4600sccm, ammonia flow is 4600sccm, and gallium source flux is 16 μm of ol/min.
The extension of this step is not limited to metal organic chemical vapor deposition technology, it would however also be possible to employ molecular beam epitaxy skill
Art or hydride gas-phase epitaxy technology.
Step 3. make source electrode 4, such as Fig. 3 c in the left end deposit metal Ti/Al/Ni/Au of barrier layer 3.
3.1) mask is made for the first time on barrier layer 3, using electron beam evaporation technique in its left end deposit metal, wherein
The metal for being deposited is Ti/Al/Ni/Au metallic combinations, i.e., be respectively Ti, Al, Ni and Au from bottom to top, and its thickness is 0.018 μ
m/0.135μm/0.046μm/0.052μm.The process conditions that adopt of deposit metal for：Vacuum is less than 1.8 × 10-3Pa, power
Scope is 200～1000W, and evaporation rate is less than
3.2) in N2Rapid thermal annealing is carried out in atmosphere, the making of source electrode 4, the process conditions that rapid thermal annealing is adopted are completed
For：Temperature is 850 DEG C, and the time is 35s.
The Metal deposition of this step is not limited to electron beam evaporation technique, it would however also be possible to employ sputtering technology.
Step 4. make Schottky drain 5, such as Fig. 3 d in the right-hand member deposit W metal/Au of barrier layer 3.
Second making mask on barrier layer 3, using electron beam evaporation technique in its right-hand member deposit metal, makes Xiao Te
Base drain electrode 5, wherein the metal for being deposited be Ni/Au metallic combinations, i.e. lower floor be Ni, upper strata be Au, its thickness be 0.046 μm/
0.21μm.The process conditions that adopt of deposit metal for：Vacuum is less than 1.8 × 10-3Pa, power bracket is 200～1000W, is steamed
Send out speed to be less than
The Metal deposition of this step is not limited to electron beam evaporation technique, it would however also be possible to employ sputtering technology.
Step 5. making table top 6, such as Fig. 3 e are performed etching on the barrier layer on the right of the source electrode left side and Schottky drain.
Mask is made for the third time on barrier layer 3, using reactive ion etching technology in the source electrode left side and Schottky drain
Perform etching on the barrier layer on the right, form table top 6, etching depth is 100nm.The process conditions that adopt of etching for：Cl2Flow
For 15sccm, pressure is 10mTorr, and power is 100W.
The etching of this step is not limited to reactive ion etching technology, it would however also be possible to employ sputtering technology or plasma etching
Technology.
Step 6. in other area tops deposit Al on source electrode top, Schottky drain top and barrier layer2O3Insulation is situated between
Matter layer 7, such as Fig. 3 f.
Deposited using other area tops of atomic layer deposition technology on source electrode top, Schottky drain top and barrier layer
Al2O3Insulating medium layer 7, its thickness is 50nm, deposit the process conditions that adopt for：With TMA and H2O is reaction source, and carrier gas is
N2, carrier gas flux is 200sccm, and underlayer temperature is 300 DEG C, and air pressure is 700Pa.
The deposit of the insulating medium layer of this step is not limited to atomic layer deposition technology, it would however also be possible to employ evaporation technique is waited
Gas ions strengthen chemical vapor deposition techniques or sputtering technology or molecular beam epitaxy technique.
Step 7. W metal/Au is deposited on the insulating medium layer between source electrode and Schottky drain and makes grid 8, such as
Fig. 3 g.
The 4th making mask on insulating medium layer, using electron beam evaporation technique between source electrode and Schottky drain
Insulating medium layer on deposit metal, make grid 8, wherein the metal for being deposited is Ni/Au metallic combinations, i.e. lower floor be Ni,
Upper strata is Au, and its thickness is 0.046 μm/0.21 μm, deposit the process conditions that adopt of metal for：Vacuum is less than 1.8 × 10- 3Pa, power bracket is 200～1000W, and evaporation rate is less than
The Metal deposition of this step is not limited to electron beam evaporation technique, it would however also be possible to employ sputtering technology.
Step 8. in grid top and other area top deposit passivation layers 9 of insulating medium layer, such as Fig. 3 h.
Other of grid top and insulating medium layer are covered each by using plasma enhanced CVD technology
Area top, completes the SiO that deposition thickness is 7.3 μm2Passivation layer 9；The process conditions that it is adopted for：N2O flows are 850sccm,
SiH4Flow is 200sccm, and temperature is 250 DEG C, and RF power is 25W, and pressure is 1100mTorr.
The deposit of the passivation layer of this step is not limited to plasma enhanced CVD technology, it would however also be possible to employ steam
Send out technology or atomic layer deposition technology or sputtering technology or molecular beam epitaxy technique.
Step 9. making bakie 10, such as Fig. 3 i are performed etching in the passivation layer between grid 8 and Schottky drain 5.
The 5th making mask on passivation layer 9, using reactive ion etching technology grid 8 and Schottky drain 5 it
Between passivation layer in perform etching, to make bakie 10, the depth of the bakie is 6.1 μm, and width is 6.7 μm, the bottom of bakie
It it is 1.2 μm with the distance between insulating medium layer, bakie is near the lateral edges of Schottky drain one and Schottky drain near grid
The distance between one lateral edges are 6.742 μm.The process conditions that adopt of etching for：CF4Flow is 45sccm, O2Flow is
5sccm, pressure is 15mTorr, and power is 250W.
The etching of this step is not limited to reactive ion etching technology, it would however also be possible to employ sputtering technology or plasma etching
Technology.
Step 10. metal Ti/Ni/Au is deposited on the passivation layer in bakie 10 and between grid 8 and Schottky drain 5
Make right angle leakage field plate 11, such as Fig. 3 j.
The 6th making mask on passivation layer 9, using electron beam evaporation technique in the bakie 10 and grid 8 and Xiao Te
Metal is deposited on passivation layer between base drain electrode 5, the metal leaks near the lateral edges of Schottky drain one and bakie near Schottky
The side edge-justified calibrations of pole one, form right angle leakage field plate 11, and right angle leakage field plate and Schottky drain are electrically connected, the gold for being deposited
Belong to for Ti/Ni/Au metallic combinations, i.e. lower floor be Ti, middle level be Ni, upper strata be Au, its thickness be 2.8 μm/2.4 μm/0.9 μm.
The metal for wherein being deposited will be filled up completely with bakie 10.Field plate is leaked near the lateral edges of grid one and bakie near grid side in right angle
The distance between edge is 7.4 μm.The process conditions that adopt of deposit metal for：Vacuum is less than 1.8 × 10-3Pa, power bracket
For 200～1000W, evaporation rate is less than
The Metal deposition of this step is not limited to electron beam evaporation technique, it would however also be possible to employ sputtering technology.
Step 11. other area tops deposit SiN for leaking the top of field plate 11 and passivation layer 9 at right angle makes protective layer
12, such as Fig. 3 k.
Other regions of the top of field plate 11 and passivation layer 9 are leaked using plasma enhanced CVD technology at right angle
Top deposit SiN forms protective layer 12, and its thickness is 5.3 μm, so as to complete the making of whole device, its process conditions for adopting
For：Gas is NH3、N2And SiH4, gas flow is respectively 2.5sccm, 950sccm and 250sccm, temperature, RF power and pressure
Respectively 300 DEG C, 25W and 950mTorr.
The deposit of the protective layer of this step is not limited to plasma enhanced CVD technology, it would however also be possible to employ steam
Send out technology or atomic layer deposition technology or sputtering technology or molecular beam epitaxy technique.
Embodiment three：Making substrate is silicon, and insulating medium layer is Al2O3, passivation layer is SiN, and protective layer is SiO2, right angle
Leakage field plate leaks field plate transistor with high electron mobility for the nitridation gallio right angle of Ti/Pt/Au metallic combinations.
From bottom to top extension AlN makes transition zone 2, such as Fig. 3 a to step A. with GaN material on silicon substrate 1.
A1 the use of metal organic chemical vapor deposition technology in temperature it is) 800 DEG C, pressure is 40Torr, hydrogen flowing quantity
For 4000sccm, ammonia flow is 4000sccm, and silicon source flow is under the process conditions of 25 μm of ol/min, on silicon substrate 1 outward
Prolong the AlN materials that thickness is 200nm；
A2 the use of metal organic chemical vapor deposition technology in temperature it is) 980 DEG C, pressure is 45Torr, hydrogen flowing quantity
For 4000sccm, ammonia flow is 4000sccm, and gallium source flux is under the process conditions of 120 μm of ol/min, on AlN materials outward
Prolong the GaN material that thickness is 4.8 μm, complete the making of transition zone 2.
Step B. deposits from bottom to top Al on transition zone0.1Ga0.9N makes barrier layer 3, such as Fig. 3 b with GaN material.
B1 the use of metal organic chemical vapor deposition technology in temperature it is) 1000 DEG C, pressure is 40Torr, hydrogen flowing quantity
For 4000sccm, ammonia flow is 4000sccm, and gallium source flux is 12 μm of ol/min, and silicon source flow is the technique of 12 μm of ol/min
Under the conditions of, epitaxial thickness is 46nm, the Al that al composition is 0.1 on transition zone 20.1Ga0.9N materials；
B2 the use of metal organic chemical vapor deposition technology in temperature it is) 1000 DEG C, pressure is 40Torr, hydrogen flowing quantity
For 4000sccm, ammonia flow is 4000sccm, and gallium source flux is under the process conditions of 3 μm of ol/min, in Al0.1Ga0.9N materials
Upper epitaxial thickness is the GaN material of 4nm, completes the making of barrier layer 3.
Step C. makes source electrode 4, such as Fig. 3 c in the left end deposit metal Ti/Al/Ni/Au of barrier layer 3.
C1) make mask for the first time on barrier layer 3,1.8 × 10 are less than in vacuum using electron beam evaporation technique- 3Pa, power bracket is 200～1000W, and evaporation rate is less thanProcess conditions under, in its left end deposit metal, wherein institute
The metal of deposit be Ti/Al/Ni/Au metallic combinations, i.e., from bottom to top be respectively Ti, Al, Ni and Au, its thickness be 0.018 μm/
0.135μm/0.046μm/0.052μm；
C2) in N2Atmosphere, temperature is 850 DEG C, and the time, to carry out rapid thermal annealing under the process conditions of 35s, completes source electrode 4
Making.
Step D. makes Schottky drain 5, such as Fig. 3 d in the right-hand member deposit W metal/Au of barrier layer 3.
Second making mask, 1.8 × 10 are less than using electron beam evaporation technique in vacuum on barrier layer 3-3Pa, work(
Rate scope is 200～1000W, and evaporation rate is less thanProcess conditions under, barrier layer 3 right-hand member deposit metal, make
Schottky drain 5, wherein it is Au for Ni, upper strata that the metal for being deposited is Ni/Au metallic combinations, i.e. lower floor, its thickness is 0.046
μm/0.21μm。
Step E. performs etching making table top 6, such as Fig. 3 e on the barrier layer on the right of the source electrode left side and Schottky drain.
Mask is made for the third time on barrier layer 3, using reactive ion etching technology in Cl2Flow is 15sccm, pressure
For 10mTorr, under power is for the process conditions of 100W, carved on the barrier layer on the right of the source electrode left side with Schottky drain
Erosion, forms table top 6, and etching depth is 200nm.
Other area top deposit Al of step F. on source electrode top, Schottky drain top and barrier layer2O3, make
Insulating medium layer 7, such as Fig. 3 f.
Using atomic layer deposition technology with TMA and H2O is reaction source, and carrier gas is N2, carrier gas flux is 200sccm, substrate
Temperature be 300 DEG C, air pressure for 700Pa process conditions under, source electrode top, Schottky drain top and barrier layer other
Area top deposits Al2O3Insulating medium layer 7, its thickness is 93nm.
W metal/Au is deposited on insulating medium layer of step G. between source electrode and Schottky drain and makes grid 8, such as schemed
3g。
The 4th making mask, 1.8 × 10 are less than using electron beam evaporation technique in vacuum on insulating medium layer- 3Pa, power bracket is 200～1000W, and evaporation rate is less thanProcess conditions under, between source electrode and Schottky drain
Insulating medium layer on deposit metal, make grid 8, wherein the metal for being deposited is Ni/Au metallic combinations, i.e. lower floor be Ni,
Upper strata is Au, and its thickness is 0.046 μm/0.21 μm.
Step H. is in grid top and other area top deposit passivation layers 9 of insulating medium layer, such as Fig. 3 h.
Using plasma enhanced CVD technology gas be NH3、N2And SiH4, gas flow is respectively
2.5sccm, 950sccm and 250sccm, temperature, RF power and pressure are respectively 300 DEG C, the process conditions of 25W and 950mTorr
Under, other area top deposition thicknesses on grid top and insulating medium layer are 16.91 μm of SiN passivation layers 9.
Making bakie 10, such as Fig. 3 i are performed etching in passivation layer 9 of step I. between grid 8 and Schottky drain 5.
The 5th making mask on passivation layer 9, using reactive ion etching technology in CF4Flow is 45sccm, O2Flow
For 5sccm, pressure is 15mTorr, and power is the passivation layer between grid 8 and Schottky drain 5 under the process conditions of 250W
Inside perform etching, to make bakie 10, the depth of the bakie is 13.9 μm, and width is 12.7 μm, and bottom and the insulation of bakie are situated between
The distance between matter layer is 3.01 μm, and bakie is near the lateral edges of Schottky drain one and Schottky drain near the lateral edges of grid one
The distance between be 24.404 μm.
Step J. deposits metal Ti/Pt/Au on the passivation layer 9 in bakie 10 and between grid 8 and Schottky drain 5
Make right angle leakage field plate 11, such as Fig. 3 j.
The 6th making mask, 1.8 × 10 are less than using electron beam evaporation technique in vacuum on passivation layer 9-3Pa, work(
Rate scope is 200～1000W, and evaporation rate is less thanProcess conditions under, in the bakie 10 and grid leaks with Schottky
Metal is deposited on passivation layer 9 between pole, the metal is near the lateral edges of Schottky drain one and bakie near Schottky drain one
Side edge-justified calibrations, form right angle leakage field plate 11, and right angle leakage field plate and Schottky drain are electrically connected, and the metal for being deposited is
Ti/Pt/Au metallic combinations, i.e. lower floor are Ti, middle level is Pt, upper strata is Au, and its thickness is 6.4 μm/5.8 μm/1.7 μm.Wherein
The metal for being deposited will be filled up completely with bakie 10.Field plate is leaked near the lateral edges of grid one and bakie near the lateral edges of grid one in right angle
The distance between be 14.6 μm.
Step K. deposits SiO on other regions that right angle leaks the top of field plate 11 and passivation layer 92Protective layer 12 is made, such as
Fig. 3 k.
Using plasma enhanced CVD technology in N2O and SiH4, gas flow be respectively 850sccm and
200sccm, temperature is 250 DEG C, and RF power is 25W, under pressure is for the process conditions of 1100mTorr, on right angle leakage field plate 11
SiO is deposited on other regions of portion and passivation layer 92Protective layer 12 is made, its thickness is 9.6 μm, so as to complete whole device
Make.
The effect of the present invention can be further illustrated by following emulation.
In the case of Schottky drain plus negative pressure, to adopting traditional HEMT for leaking field plate and this
The breakdown characteristics of funerary objects part are emulated, as a result such as Fig. 4.
As seen from Figure 4, in the case of Schottky drain plus negative pressure, using the high electron mobility of tradition leakage field plate
Transistor punctures, i.e. Schottky drain electric current increases sharply, when drain-source voltage about in -1120V, and device of the present invention
Drain-source voltage when puncturing is about in -3240V, it was demonstrated that the breakdown reverse voltage of device of the present invention is far longer than using tradition
The breakdown reverse voltage of the HEMT of leakage field plate.
For those skilled in the art, after present invention and principle has been understood, can be without departing substantially from this
In the case of bright principle and scope, the method according to the invention carries out various amendments and change in form and details, but
These amendments and change based on the present invention are still within the claims of the present invention.
Claims (8)
1. a kind of nitridation gallio right angle leakage field plate transistor with high electron mobility, includes from bottom to top：Substrate (1), transition zone
(2), barrier layer (3), insulating medium layer (7), passivation layer (9) and protective layer (12), be deposited with above barrier layer source electrode (4) with
Table top (6) is carved with Schottky drain (5), the side of barrier layer, and land depth is more than barrier layer thickness, insulating medium layer (7)
On be deposited with grid (8), it is characterised in that：
Bakie (10) is carved with passivation layer (9)；
Right angle leakage field plate (11) is deposited between passivation layer (9) and protective layer (12)；
Right angle leakage field plate (11) is electrically connected with Schottky drain (5), and lower end is completely filled in bakie (10), and this is straight
The close lateral edges of Schottky drain one in angle leakage field plate (11) and the close side edge-justified calibrations of Schottky drain one of bakie (10), and bakie
It is s × (d+e × ε near the distance between the lateral edges of grid one a near the lateral edges of Schottky drain one and Schottky drain2/ε1
)0.5, wherein s is the depth of bakie, and d is the distance between bakie bottom and insulating medium layer, and e is the thickness of insulating medium layer,
ε1For the relative dielectric constant of insulating medium layer, ε2For the relative dielectric constant of passivation layer.
2. nitridation gallio right angle according to claim 1 leaks field plate transistor with high electron mobility, it is characterised in that bakie
Depth s be 0.71～13.9 μm, width b be 1.14～12.7 μm；The distance between the bottom of bakie and insulating medium layer d is
0.122～3.01 μm, the thickness e of insulating medium layer is 2～93nm.
3. nitridation gallio right angle according to claim 1 leaks field plate transistor with high electron mobility, it is characterised in that right angle
Leakage field plate is 1.21～14.6 μm near the distance between the lateral edges of grid one c near the lateral edges of grid one and bakie.
4. nitridation gallio right angle according to claim 1 leaks field plate transistor with high electron mobility, it is characterised in that substrate
(1) using sapphire or carborundum or silicon materials.
5. it is a kind of to make the method that nitridation gallio right angle leaks field plate transistor with high electron mobility, comprise the steps：
The first step, the extension GaN base semiconductor material with wide forbidden band on substrate (1) forms transition zone (2)；
Second step, the extension GaN base semiconductor material with wide forbidden band on transition zone forms barrier layer (3)；
3rd step, makes for the first time mask on barrier layer, and using left end of the mask in barrier layer metal is deposited, then in N2Gas
Rapid thermal annealing is carried out in atmosphere, source electrode (4) is made；
4th step, second making mask on barrier layer deposits metal using right-hand member of the mask in barrier layer, makes Xiao Te
Base drains (5)；
5th step, makes for the third time mask on barrier layer, using the mask on the left of source electrode with Schottky drain on the right side of gesture
Barrier layer is performed etching on (3), and etching depth is more than barrier layer thickness, forms table top (6)；
6th step, in other area top deposit insulating dielectric materials of source electrode top, Schottky drain top and passivation layer,
Form insulating medium layer (7)；
7th step, the 4th making mask, exhausted between source electrode and Schottky drain using the mask on insulating medium layer
Metal is deposited on edge dielectric layer, grid (8) is made；
8th step, respectively in grid (8) top and other area tops deposit passivation layer (9) of insulating medium layer；
9th step, makes mask the 5th time, using the mask between grid (8) and Schottky drain (5) over the passivation layer
Perform etching in passivation layer, to make bakie (10), and bakie is close near the lateral edges of Schottky drain one and Schottky drain
The distance between the lateral edges of grid one a is s × (d+e × ε2/ε1)0.5, wherein s is the depth of bakie, and d is bakie bottom and insulation
The distance between dielectric layer, e for insulating medium layer thickness, ε1For the relative dielectric constant of insulating medium layer, ε2For passivation layer
Relative dielectric constant；
Tenth step, makes mask the 6th time over the passivation layer, using the mask is in bakie (10) and grid leaks with Schottky
Passivation layer (9) top deposit metal between pole, the metal for being deposited is filled up completely with bakie (10), and the metal leaks near Schottky
The lateral edges of pole one, near the side edge-justified calibrations of Schottky drain one, to form the right angle that thickness is 0.71～13.9 μm field are leaked with bakie
Plate (11), and right angle leakage field plate and Schottky drain are electrically connected；
11st step, at right angle other area top deposit insulating dielectric materials of field plate top and passivation layer are leaked, and form protection
Layer (12), completes the making of whole device.
6. method according to claim 5, it is characterised in that in the tenth step in bakie (10) and grid and Xiao
The metal deposited on passivation layer (9) between Te Ji drain electrodes, using three-layer metal combination, Ti/Mo/Au, i.e. lower floor are Ti, middle level
It is Au for Mo, upper strata, its thickness is 0.34～6.4 μm/0.27～5.8 μm/0.1～1.7 μm.
7. method according to claim 5, it is characterised in that in the tenth step in bakie (10) and grid and Xiao
The metal deposited on passivation layer (9) between Te Ji drain electrodes, using three-layer metal combination, Ti/Ni/Au, i.e. lower floor are Ti, middle level
It is Au for Ni, upper strata, its thickness is 0.34～6.4 μm/0.27～5.8 μm/0.1～1.7 μm.
8. method according to claim 5, it is characterised in that in the tenth step in bakie (10) and grid and Xiao
The metal deposited on passivation layer (9) between Te Ji drain electrodes, be using three-layer metal combination Ti/Pt/Au, i.e. lower floor further
Ti, middle level are Pt, upper strata is Au, and its thickness is 0.34～6.4 μm/0.27～5.8 μm/0.1～1.7 μm.
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| CN103745992A (en) * | 2014-01-22 | 2014-04-23 | 西安电子科技大学 | Composite drain-based AlGaN/GaN MIS-HEMT (Metal-Insulator-Semiconductor High-Electron-Mobility Transistor) high-voltage device and fabrication method thereof |
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| CN103745992A (en) * | 2014-01-22 | 2014-04-23 | 西安电子科技大学 | Composite drain-based AlGaN/GaN MIS-HEMT (Metal-Insulator-Semiconductor High-Electron-Mobility Transistor) high-voltage device and fabrication method thereof |
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