CN107369709A - 半导体结构的形成方法 - Google Patents

半导体结构的形成方法 Download PDF

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CN107369709A
CN107369709A CN201610315837.4A CN201610315837A CN107369709A CN 107369709 A CN107369709 A CN 107369709A CN 201610315837 A CN201610315837 A CN 201610315837A CN 107369709 A CN107369709 A CN 107369709A
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stressor layers
coating
substrate
forming method
forming
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CN107369709B (zh
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金兰
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to EP17169812.9A priority patent/EP3244441B1/en
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Abstract

一种半导体结构的形成方法，包括：提供衬底，衬底包括用于形成第一晶体管的第一区域和用于形成第二晶体管的第二区域；形成第一应力层和第二应力层，第一应力层和第二应力层的顶部表面高于衬底的表面；形成覆盖层；去除第一应力层和第二应力层相对面上部分厚度的覆盖层。本发明通过在形成覆盖层之后，去除第一应力层和第二应力层相对表面上部分厚度的覆盖层，以扩大隔离结构两侧第一应力层和第二应力层之间的距离，有效的改善相邻应力层之间距离太近而引起的器件性能问题，减少了器件短接现象的出现。此外，去除部分厚度的覆盖层还可以去除位于第一应力层和第二应力层相对表面上覆盖层表面所形成的堆叠缺陷，从而提高所形成半导体器件的性能。

Description

半导体结构的形成方法
技术领域
本发明涉及半导体制造领域，特别涉及一种半导体结构的形成方法。
背景技术
随着半导体技术的不断发展，半导体器件的尺寸不断减小。随着半导体器件尺寸的减小，MOS晶体管的接触电阻对于MOS晶体管性能以及对整个半导体芯片性能的影响逐渐增大。为了提高半导体芯片的性能，需要降低MOS晶体管的接触电阻。而随着半导体器件尺寸的减小，源区、漏区的面积越来越小。因此源区、漏区与金属插塞之间的接触电阻随着器件尺寸的减小而增大。源区、漏区与金属插塞之间较大的接触电阻，影响了MOS晶体管的性能，限制了半导体器件的运行速度。
在源区、漏区上形成自对准硅化物(Salicide)能够有效减小源区、漏区与金属插塞之间的接触电阻。现有技术中自对准硅化物的形成过程主要包括：首先通过蒸发或溅射工艺在硅层表面形成金属层；然后进行退火处理，使金属与硅发生反应形成金属硅化物；最后去除未与硅发生反应的金属层。
此外，为了提高芯片运行速度，提高MOS晶体管的性能，现有技术通过在MOS晶体管的源区、漏区引入应力层，以提高沟道内载流子的迁移率。由锗硅材料或碳硅材料的形成MOS晶体管源区、漏区，能够在MOS晶体管的沟道区域引入压应力或拉应力，从而改善MOS晶体管的性能。
然而，随着半导体器件尺寸的缩小，MOS晶体管的尺寸也相应缩小，提高了形成自对准硅化物的难度增大，致使MOS晶体管的性能下降。
发明内容
本发明解决的问题是提供一种半导体结构的形成方法，以改善所形成半导体结构的性能。
为解决上述问题，本发明提供一种半导体结构的形成方法，包括：
提供衬底，所述衬底包括用于形成第一晶体管的第一区域和用于形成第二晶体管的第二区域；在所述第一区域衬底中形成第一应力层，并在第二区域衬底中形成第二应力层，所述第一应力层和所述第二应力层的顶部表面高于所述衬底的表面；在所述第一应力层和所述第二应力层表面形成覆盖层；去除所述第一应力层和所述第二应力层相对面上部分厚度的覆盖层。
可选的，去除所述第一应力层和所述第二应力层相对面上部分厚度的覆盖层的步骤包括：采用刻蚀气体对所述第一应力层与第二应力层相对表面上的覆盖层进行刻蚀处理，去除所述第一应力层和所述第二应力层相对面上部分厚度的覆盖层。
可选的，进行刻蚀处理时，所述刻蚀气体包括氯化氢气体、六氟化硫气体、溴化氢气体或氯气中的一种或多种。
可选的，进行刻蚀处理时，所述刻蚀气体的流速在0sccm到50sccm。
可选的，进行刻蚀处理时，所述刻蚀气体的流速在所述刻蚀气体压强在0Torr到50Torr范围内，温度在550℃到750℃范围内。
可选的，进行刻蚀处理时，所述刻蚀处理为原位刻蚀处理。
可选的，所述覆盖层为硅层。
可选的，形成所述覆盖层的步骤中，工艺温度在600℃到800℃范围内。
可选的，形成所述覆盖层的步骤中，所采用工艺气体包括甲硅烷和乙硅烷。
可选的，提供衬底的步骤包括：在所述衬底中形成隔离结构，用于将所述衬底分为所述第一区域和所述第二区域；在所述第一区域衬底中形成的第一应力层，并在第二区域衬底中形成第二应力层的步骤包括：在第一区域衬底中形成第一开口并在第二区域衬底中形成第二开口；分别向所述第一开口和第二开口填充应力材料，以形成所述第一应力层和所述第二应力层。
可选的，填充应力材料的步骤包括：通过化学气相沉积的方式向所述第一开口和所述第二开口内填充应力材料形成第一应力层和第二应力层。
可选的，通过化学气相沉积的方式填充应力材料层的步骤包括：通过减压化学气相沉积的方式填充所述应力材料。
可选的，所述第一应力层和所述第二应力层的材料为锗硅，通过化学气相沉积的方式填充应力材料层的步骤中，工艺温度在550℃到750℃范围内；工艺气体包括甲硅烷、乙硅烷、二氯硅烷以及锗烷；工艺气体压强在0Torr到50Torr范围内。
可选的，所述第一应力层和所述第二应力层为P型掺杂应力层，所述工艺气体还包括：乙硼烷。
可选的，所述衬底用于形成P型晶体管，形成第一开口和第二开口的步骤包括：形成西格玛形的第一开口和第二开口。
可选的，在去除所述第一应力层和所述第二应力层相对表面上部分厚度的覆盖层之后，还包括：在所述覆盖层表面形成金属层。
可选的，所述金属层材料包括镍。
与现有技术相比，本发明的技术方案具有以下优点：
本发明通过在形成覆盖层之后，去除所述第一应力层和所述第二应力层相对表面上部分厚度的覆盖层，以扩大隔离结构两侧第一应力层和第二应力层之间的距离，从而有效的改善相邻应力层之间距离太近而引起的器件性能问题，减少了器件短接现象的出现。此外，去除所述部分厚度的覆盖层还可以去除位于所述第一应力层和所述第二应力层相对表面上覆盖层表面所形成的堆叠缺陷，从而提高所形成半导体器件的性能。
附图说明
图1是现有技术中一种半导体结构的剖面示意图；
图2至图7是本发明半导体结构形成方法一实施例中间结构的剖面示意图。
具体实施方式
由背景技术可知，现有技术中的在应力层上形成自对准硅化物的MOS晶体管存在不同晶体管之间短路的的问题。现结合现有技术中的MOS晶体管结构分析短路问题的原因：
参考图1，示出了现有技术中一种半导体结构形成方法中中间结构的剖面示意图。
如图1所示，所述半导体结构包括：衬底10，所述衬底10内形成有隔离结构11；所述隔离结构11两侧的所述衬底10内形成有第一应力层12a和第二应力层12b，所述第一应力层12a和所述第二应力层12b的顶部表面高于所述隔离结构11的顶部表面。
为了减小源区、漏区与金属插塞之间的接触电阻，在用作源区、漏区的第一应力层12a和第二应力层12b表面形成自对准硅化物。具体的，首先在第一应力层12a和第二应力层12b表面形成覆盖层13；接着在覆盖层13表面形成金属层；之后退火处理，以使金属与硅发生反应形成硅化物。
由于第一应力层12a和第二应力层12b的顶部表面高于所述隔离结构11的顶部表面，因此第一应力层12a和第二应力层12b在隔离结构11上方具有相对的表面。第一应力层12a和第二应力层12b表面覆盖层13的形成使第一应力层12a和第二应力层12b在隔离结构上方的间距d减小。
随着半导体器件尺寸的减小，第一应力层12a和第二应力层12b之间的距离随着减小，因此所述覆盖层13形成后，第一应力层12a和第二应力层12b相对表面上覆盖层13之间的间距更小。所以容易造成第一应力层12a和第二应力层12b相对表面上覆盖层13相连。之后再在覆盖层13上形成金属层，经退火后形成的金属硅化物也容易相连，造成不同晶体管之间的短路问题。
为解决所述技术问题，本发明提供一种半导体结构的形成方法，包括：
提供衬底，所述衬底包括用于形成第一晶体管的第一区域和用于形成第二晶体管的第二区域；在所述第一区域衬底中形成第一应力层，并在第二区域衬底中形成第二应力层，所述第一应力层和所述第二应力层的顶部表面高于所述衬底的表面；在所述第一应力层和所述第二应力层表面形成覆盖层；去除所述第一应力层和所述第二应力层相对面上部分厚度的覆盖层。
本发明通过在形成覆盖层之后，去除所述第一应力层和所述第二应力层相对表面上部分厚度的覆盖层，以扩大隔离结构两侧第一应力层和第二应力层之间的距离，从而有效的改善相邻应力层之间距离太近而引起的器件性能问题，减少了器件短接现象的出现。此外，去除所述部分厚度的覆盖层还可以去除位于所述第一应力层和所述第二应力层相对表面上覆盖层表面所形成的堆叠缺陷，从而提高所形成半导体器件的性能。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
参考图2至图7，示出了本发明半导体结构形成方法一实施例各个步骤中间结构的剖面示意图。
需要说明的是，本实施例中，以用于形成PMOS器件的半导体结构为例进行说明。但是本发明技术方案也可以应用于NMOS器件半导体结构的形成。
如图2和图3所示，提供衬底100，所述衬底100包括用于形成第一晶体管的第一区域100a和用于形成第二晶体管的第二区域100b。
所述衬底100用于为后续工艺提供操作平台。所述衬底100的材料选自单晶硅、多晶硅或者非晶硅；所述衬底100也可以选自硅、锗、砷化镓或锗硅等化合物；所述衬底100还可以是其他半导体材料。此外，所述衬底100还可以选自具有外延层或外延层上硅材料。本实施例中，以形成平面晶体管的栅极结构为例进行说明，因此，所述衬底100为单晶硅衬底。
本实施例中，提高衬底100的步骤包括：在所述衬底100中形成隔离结构110。所述隔离结构110，用于将所述衬底100分为所述第一区域100a和所述第二区域100b，也就是说，所述隔离结构110位于所述第一区域100a和第二区域100b之间的衬底100内。具体的，所述隔离结构110由氧化物形成。
形成所述隔离结构110的步骤包括：在所述衬底100表面形成第一图形化层，所述第一图形化层用于定义所述隔离结构110的尺寸和位置；以所述第一图形化层为掩膜，刻蚀所述衬底100，在所述衬底100内形成沟槽；向所述沟槽内填充绝缘材料以形成所述隔离结构110。
所述图形化层可以是图形化的光刻胶层，采用涂布工艺和光刻工艺形成。此外，为了缩小后续所形成金属栅极结构的尺寸，缩小所形成半导体器件的尺寸，所述图形化层还可以采用多重图形化掩膜工艺形成。所述多重图形化掩膜工艺包括：自对准双重图形化(Self-aligned Double Patterned，SaDP)工艺、自对准三重图形化(Self-aligned Triple Patterned)工艺或自对准四重图形化(Self-aligned Double Double Patterned,SaDDP)工艺。
继续参考图2，结合参考图3，在所述第一区域100a的衬底100中形成第一应力层121，并在所述第二区域100b的衬底100中形成第二应力层122，所述第一应力层121和所述第二应力层122的顶部表面高于所述衬底100的表面。
具体的，如图2所示，形成所述第一应力层121和所述第二应力层122的步骤包括：首先，在第一区域100a衬底100中形成第一开口121p，并在所述第二区域100b衬底100中形成第二开口122p。
具体的，所述第一开口121p和所述第二开口122p用于形成第一应力层121和第二应力层122。
本实施例中，所述衬底用于形成PMOS器件，也就是说，所述半导体结构中的MOS晶体管沟道是靠空穴流动实现电流运送。因此所形成MOS晶体管的沟道内需要引入压应力。为了引入更大的压应力，需要形成“∑”形的应力层。所以，形成所述第一开口121p和第二开口122p的步骤包括：形成西格玛形(“∑”)的所述第一开口121p和所述第二开口122p。
形成所述第一开口121p和第二开口122p的步骤包括：在所述衬底100表面形成第二图形化层，所述第二图形化层用于定义所述第一开口121p和所述第二开口122p的尺寸和位置；以所述第二图形化层为掩膜，刻蚀所述衬底100，在所述衬底100内形成所述第一开口121p和所述第二开口122p。
所述图形化层可以是图形化的光刻胶层，也可以是多重掩膜工艺形成的掩膜层。
如图3所示，在形成所述第一开口121p和第二开口122p之后，分别向所述第一开口121p和第二开口122p填充应力材料，以形成所述第一应力层121和所述第二应力层122。
具体的，可以通过化学气相沉积的方式向所述第一开口121p和所述第二应力层122p内填充应力材料。本实施例中，采用反应等离子体化学气相沉积的方式填充所述应力材料。
因为所述衬底100用于形成PMOS器件，需要在沟道内引入压应力，因此所述应力材料为锗硅材料。也就是说，所述第一应力层121和所述第二应力层122为锗硅应力层。
具体的，在通过反应等离子体化学气相沉积的方式填充锗硅材料的过程中，所采用的工艺温度在550℃到750℃范围内，工艺气体的压强在0T到50T范围内。所采用的工艺气体包括作为硅源的甲硅烷、乙硅烷和二氯硅烷以及作为锗源的锗烷气体。
此外，所述衬底100用于形成PMOS器件，因此在形成所述第一应力层121和所述第二应力层122的过程中，还可以原位在应力层内掺杂P型离子，形成P型掺杂应力层。也就是说，所述第一应力层121和所述第二应力层122为P型掺杂应力层。例如，所述P型离子可以为硼离子。所以，本实施例中，在通过反应等离子体化学气相沉积的方式填充锗硅材料的过程中，所采用的工艺气体还可以包括作为硼源的乙硼烷。
需要说明的是，为了增大沟道区域引入的压应力，本实施例中，所述第一应力层121和所述第二应力层122为“∑”形的应力层。“∑”形的应力层具有指向沟道区域的凸出尖端，在凸出尖端处的锗硅材料根靠近沟道区域，能够在沟道区域引入更大的压应力。
需要说明的是，所述第一应力层121和所述第二应力层122位于所述隔离结构110的两侧。所述隔离结构110的顶部表面与所述衬底100的表面齐平。所以所述第一应力层121和所述第二应力层122的顶部表面高于所述隔离结构110的顶部表面。
为了引入足够的压应力，所述第一开口121p(如图2所示)和所述第二开口122p(如图2所示)被过量填充，也就是说，所述第一应力层121和所述第二应力层122的顶部表面高于所述隔离结构110的顶部表面，从而使所述隔离结构110上方，所述第一应力层121和所述第二应力层122相对表面之间的距离较小。
参考图4，在所述第一应力层121和所述第二应力层122表面形成覆盖层130。
具体的，所述覆盖层130后续用于形成自对准硅化物。因此所述覆盖层130为硅层。
由于所述第一应力层121和所述第二应力层122的材料为锗硅。因此所述第一应力层121和所述第二应力层122顶部表面和侧壁的晶面是不同的。因此如果形成所述覆盖层130的工艺温度太低，形成所述覆盖层130的过程中原子对晶面的选择性较强。本实施例中，所形成的覆盖层130难以覆盖所述第一应力层121和所述第二应力层122的侧壁，从而影响后续自对准硅化物的形成。因此，本实施例中，形成所述覆盖层130的工艺温度在600℃到800℃范围内，工艺气体包括甲硅烷和乙硅烷。
所述覆盖层130的形成，进一步缩小了所述第一应力层121和所述第二应力层122相对表面之间的距离D。当所述第一应力层121和所述第二应力层122相对表面上的所述覆盖层130之间的距离D太近，后续通过所述覆盖层130在所述第一应力层121和所述第二应力层122表面所形成的硅化物会有相连的可能，从而引起所述隔离结构110两侧不同有源区内器件出现短路的问题。
参考图5，在形成覆盖层130之后，去除所述第一应力层121和所述第二应力层122相对面上部分厚度的覆盖层130。
具体的，可以采用刻蚀气体对所述第一应力层121与所述第二应力层122相对表面上的覆盖层130进行刻蚀处理，以去除所述第一应力层121和所述第二应力层122相对面上部分厚度的覆盖层130。
所述刻蚀处理用于去除所述第一应力层121和所述第二应力层122相对面上覆盖层130的部分厚度，从而扩大所述第一应力层121和所述第二应力层122相对面上覆盖层130之间的距离，降低所述第一应力层121和所述第二应力层122上覆盖层130相连的可能，降低后续通过所述覆盖层130形成硅化物相连的可能，改善器件短路的问题。
在刻蚀处理过程中，所述刻蚀处理所采用的刻蚀气体为能够实现硅干法刻蚀的刻蚀气体，具体包括氯化氢气体、六氟化硫气体、溴化氢气体或氯气中的一种或多种。本实施例中，所述刻蚀气体包括氯化氢气体。
此外，在形成所述覆盖层130的过程中，所述第一应力层121、所述第二应力层122以及所述隔离结构110表面和相连角落中很容易形成非晶材料，也就是说，在所述第一应力层121、所述第二应力层122以及所述隔离结构110表面和相连角落容易堆积非晶硅。所述刻蚀处理还可以去除所堆积的非晶硅。
具体的，结合参考图6，不同流速氯化氢气体非晶硅的刻蚀速率与晶体硅刻蚀速率的比值。其中横轴表示氯化氢气体的流速；纵轴表示非晶硅刻蚀速率与多晶硅刻蚀速率的比值。
从图中可以看到，随着氯化氢气体流速的增大，非晶硅刻蚀速率与晶体硅刻蚀速率的比值越来越大，也就是说，氯化氢气体对非晶硅材料的去除速率越来越快于其对晶体硅材料的去除速率。所以采用氯化氢气体进行刻蚀处理还可以去除堆叠在表面或者拐角处的非晶缺陷。
如果刻蚀气体的流速太大，则可能造成覆盖层130去除厚度太多，容易影响后续通过所述覆盖层130形成的硅化物的厚度，影响所述第一应力层121和所述第二应力层122与金属插塞之间的接触电阻的大小；如果刻蚀气体的流速太小，则无法去除所述覆盖层130以及非晶缺陷。
此外，所述刻蚀气体的压强如果太小，则无法对所述第一应力层121和所述第二应力层122相对表面上覆盖层130形成冲击，无法有效去除所述覆盖层130的部分厚度；如果所述刻蚀气体的压强过大，则会造成所述覆盖层130的受损甚至造成所述第一应力层121和所述第二应力层122的受损。
本实施例中，在进行刻蚀处理时，所述刻蚀气体的流速在0sccm到50sccm；所述刻蚀气体压强在0T到50T范围内，刻蚀温度在550℃到750℃。但是需要说明的是，这种刻蚀处理的工艺参数仅为一示例。刻蚀处理过程中的具体工艺参数需要根据所形成半导体结构的具体设计、要求而定。
类似的，刻蚀处理所去除所述覆盖层的厚度也是根据所形成半导体结构对有源区之间距离的要求而定的。当设计要求有源区之间距离较大时，则需要去除所述覆盖层的厚度较多；当设计要求有源区之间距离较小时，则需要去除所述覆盖层的厚度较少。
需要说明的是，在进行刻蚀处理时，所述刻蚀处理还可以为原位刻蚀处理，也就是说，在完成最后一次膜层沉积之后，在同一工艺腔室内进行原位刻蚀处理。这种做法的好处在于无需更换机台或更换腔室，减少了工艺步骤和工艺难度，提高了工艺效率。
参考图7，之后，所述形成方法还包括：在所述覆盖层130表面形成金属层140。
所述金属层140覆盖所述覆盖层130表面，后续通过退火处理使所述金属层140与所述覆盖层130反应形成硅化物，以降低所述第一应力层121和所述第二应力层122与金属插塞之间的接触电阻。具体的，所述金属层140的材料为金属镍，可以通过化学气相沉积、物理气相沉积或者原子层沉积等方式在所述覆盖层130表面形成。
需要说明的是，所述金属层140还可以覆盖所述隔离结构110表面(图中未示出)。由于所述隔离结构110的材料为氧化物，因此可以通过退火工艺的控制，使所述金属层140与所述隔离结构110不反应，因此硅化物的形成是一种自对准的过程。在退火处理后，还可以刻蚀的方法去除不需要的金属层，使所形成的硅化物仅覆盖所述第一应力层121和所述第二应力层122。
综上，本发明通过在形成覆盖层之后，去除所述第一应力层和所述第二应力层相对表面上部分厚度的覆盖层，以扩大隔离结构两侧第一应力层和第二应力层之间的距离，从而有效的改善相邻应力层之间距离太近而引起的器件性能问题，减少了器件短接现象的出现。此外，去除所述部分厚度的覆盖层还可以去除位于所述第一应力层和所述第二应力层相对表面上覆盖层表面所形成的堆叠缺陷，从而提高所形成半导体器件的性能。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (17)

1.一种半导体结构的形成方法，其特征在于，包括：
提供衬底，所述衬底包括用于形成第一晶体管的第一区域和用于形成第二晶体管的第二区域；
在所述第一区域衬底中形成第一应力层，并在第二区域衬底中形成第二应力层，所述第一应力层和所述第二应力层的顶部表面高于所述衬底的表面；
在所述第一应力层和所述第二应力层表面形成覆盖层；
去除所述第一应力层和所述第二应力层相对面上部分厚度的覆盖层。
2.如权利要求1所述的形成方法，其特征在于，去除所述第一应力层和所述第二应力层相对面上部分厚度的覆盖层的步骤包括：采用刻蚀气体对所述第一应力层与第二应力层相对表面上的覆盖层进行刻蚀处理，去除所述第一应力层和所述第二应力层相对面上部分厚度的覆盖层。
3.如权利要求2所述的形成方法，其特征在于，进行刻蚀处理时，所述刻蚀气体包括氯化氢气体、六氟化硫气体、溴化氢气体或氯气中的一种或多种。
4.如权利要求2所述的形成方法，其特征在于，进行刻蚀处理时，所述刻蚀气体的流量在0sccm到50sccm。
5.如权利要求2所述的形成方法，其特征在于，进行刻蚀处理时，所述刻蚀气体的流速在所述刻蚀气体压强在0Torr到50Torr范围内，温度在550℃到750℃范围内。
6.如权利要求2所述的形成方法，其特征在于，进行刻蚀处理时，所述刻蚀处理为原位刻蚀处理。
7.如权利要求1所述的形成方法，其特征在于，所述覆盖层为硅层。
8.如权利要求1所述的形成方法，其特征在于，形成所述覆盖层的步骤中，工艺温度在600℃到800℃范围内。
9.如权利要求1所述的形成方法，其特征在于，形成所述覆盖层的步骤中，所采用工艺气体包括甲硅烷和乙硅烷。
10.如权利要求1所述的形成方法，其特征在于，提供衬底的步骤包括：在所述衬底中形成隔离结构，用于将所述衬底分为所述第一区域和所述第二区域；
在所述第一区域衬底中形成的第一应力层，并在第二区域衬底中形成第二应力层的步骤包括：
在第一区域衬底中形成第一开口并在第二区域衬底中形成第二开口；
分别向所述第一开口和第二开口填充应力材料，以形成所述第一应力层和所述第二应力层。
11.如权利要求10所述的形成方法，其特征在于，填充应力材料的步骤包括：通过化学气相沉积的方式向所述第一开口和所述第二开口内填充应力材料形成第一应力层和第二应力层。
12.如权利要求11所述的形成方法，其特征在于，通过化学气相沉积的方式填充应力材料层的步骤包括：通过减压化学气相沉积的方式填充所述应力材料。
13.如权利要求12所述的形成方法，其特征在于，所述第一应力层和所述第二应力层的材料为锗硅，通过化学气相沉积的方式填充应力材料层的步骤中，工艺温度在550℃到750℃范围内；工艺气体包括甲硅烷、乙硅烷、二氯硅烷以及锗烷；工艺气体压强在0Torr到50Torr范围内。
14.如权利要求13所述的形成方法，其特征在于，所述第一应力层和所述第二应力层为P型掺杂应力层，所述工艺气体还包括：乙硼烷。
15.如权利要求10所述的形成方法，其特征在于，所述衬底用于形成P型晶体管，形成第一开口和第二开口的步骤包括：形成西格玛形的第一开口和第二开口。
16.如权利要求1所述的形成方法，其特征在于，在去除所述第一应力层和所述第二应力层相对表面上部分厚度的覆盖层之后，还包括：在所述覆盖层表面形成金属层。
17.如权利要求16所述的形成方法，其特征在于，所述金属层材料包括镍。
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