CN107342316B - 一种矩阵排列的环形fet器件 - Google Patents
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- 239000002184 metal Substances 0.000 claims abstract description 38
- 229910052751 metal Inorganic materials 0.000 claims abstract description 38
- 238000002955 isolation Methods 0.000 claims abstract description 16
- 238000003491 array Methods 0.000 claims abstract description 13
- 239000011148 porous material Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 230000004888 barrier function Effects 0.000 claims abstract description 7
- 150000002739 metals Chemical class 0.000 claims abstract description 4
- 238000005036 potential barrier Methods 0.000 claims abstract description 4
- 230000015556 catabolic process Effects 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000007363 ring formation reaction Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 1
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- 230000017525 heat dissipation Effects 0.000 description 1
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- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Abstract
本发明涉及半导体器件技术领域，具体涉及一种矩阵排列的环形FET器件，从下至上包括衬底、缓冲层及势垒层；环形隔离区形成于势垒层表面且延伸至缓冲层内部；源极由若干个呈矩阵排列的源极金属组成；栅极的第一环绕部由若干个呈矩阵排列的闭合环组成，闭合环环绕对应的源极金属；第一延伸部从每一行位于边缘的闭合环沿第一直线方向延伸覆盖至环形隔离区；漏极的第二环绕部具有若干个呈矩阵排列的通孔，闭合环位于对应的通孔内；第二延伸部从第二环绕部沿第二直线方向延伸覆盖至环形隔离区；从衬底底部向上开设若干背孔至源极金属，每个源极金属经对应的背孔通过连接金属与背面金属相连。本发明可以降低栅延迟、提高器件击穿电压。
Description
技术领域
本发明属于半导体器件技术领域，具体涉及一种矩阵排列的环形FET器件。
背景技术
管芯的结构设计对于器件的性能影响严重，目前常用的场效应晶体管(FET)采用条形栅结构，源极和漏极分列栅极的两边。这种管芯设计，同样栅宽下，面积更大，栅延迟严重，并且由于电场的不均匀分布极易导致器件击穿。
发明内容
本发明的目的在于提供一种可以降低栅延迟、提高击穿电压的矩阵排列的环形FET器件。
为达到上述要求，本发明采取的技术方案是：提供一种矩阵排列的环形FET器件，从下至上包括衬底、缓冲层及势垒层；还包括环形隔离区、栅极、源极及漏极，环形隔离区形成于势垒层表面且延伸至缓冲层内部；源极由若干个呈矩阵排列的源极金属组成，每个源极金属形成于势垒层上且底部延伸至缓冲层；栅极包括第一环绕部和第一延伸部，第一环绕部由若干个呈矩阵排列的闭合环组成，闭合环与源极金属一一对应，且闭合环环绕对应的源极金属，每个闭合环与同一行相邻的闭合环连接；第一延伸部从每一行位于边缘的闭合环引出，并沿第一直线方向延伸覆盖至环形隔离区；漏极包括第二环绕部和第二延伸部，第二环绕部具有若干个呈矩阵排列的通孔，每个通孔与同一行相邻的通孔连通，通孔与闭合环一一对应，且闭合环位于对应的通孔内；第二延伸部从第二环绕部沿第二直线方向延伸覆盖至环形隔离区；从衬底底部向上开设若干背孔至源极金属，背孔与源极金属一一对应，且每个源极金属经对应的背孔通过连接金属与衬底底面的背面金属相连。
与现有技术相比，本发明具有以下优点：源极做成圆柱形，通过背面通孔接地，并呈矩阵结构排列；栅极做成环状，包裹住矩阵位置上的每一个源极，漏极为一大片金属，源极和栅极被漏极所包围；该管芯结构设计使得器件面积更小，可实现更高的功率密度；栅上电压分布均匀，可以有效提高栅对沟道的调制能力；有效降低栅的寄生电阻，减小栅延迟，提升器件工作速度；电流、电场分布更加均匀，更加适合高功率输出；漏金属面积更大，更加利于散热。
附图说明
此处所说明的附图用来提供对本申请的进一步理解，构成本申请的一部分，在这些附图中使用相同的参考标号来表示相同或相似的部分，本申请的示意性实施例及其说明用于解释本申请，并不构成对本申请的不当限定。在附图中：
图1为本发明实施例1的俯视图；
图2为本发明实施例2的俯视图；
图3为图1沿A-A方向的剖视图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，以下结合附图及具体实施例，对本申请作进一步地详细说明。为简单起见，以下描述中省略了本领域技术人员公知的某些技术特征。
实施例1
如图1和图3所示，本实施例提供一种矩阵排列的环形FET器件，从下至上包括衬底2、缓冲层3及势垒层6；还包括环形隔离区4、栅极7、源极8及漏极5，环形隔离区4形成于势垒层6表面且延伸至缓冲层3内部，如图1所示，两条虚线之间为环形隔离区4；源极8由16个呈矩阵排列的圆柱形的源极金属81组成，阵列大小为4×4，每个源极金属81形成于势垒层6上且底部延伸至缓冲层3。栅极7包括第一环绕部71和第一延伸部72，第一环绕部71由16个呈矩阵排列的闭合环711组成，闭合环711为闭合圆环，闭合环711与源极金属81一一对应，且闭合环711环绕对应的源极金属81，每个闭合环711与同一行相邻的闭合环711连接；第一延伸部72从每一行位于边缘的闭合环711引出，并沿第一直线方向延伸覆盖至环形隔离区4。漏极5包括第二环绕部51和第二延伸部52，第二环绕部51具有16个呈矩阵排列的通孔53，通孔53为圆孔；每个通孔53与同一行相邻的通孔53连通，通孔53与闭合环711一一对应，且闭合环711位于对应的通孔53内；第二环绕部51的外边缘为非闭合矩形，第二环绕部51一侧开设有4个开口，开口与每一行边缘的通孔一一对应且连通，第一延伸部72从每个开口处穿出。第二延伸部52从第二环绕部51沿第二直线方向延伸覆盖至环形隔离区4；从衬底2底部向上开设16个背孔9至源极金属81，背孔9与源极金属81一一对应，且每个源极金属81经对应的背孔9通过连接金属与衬底2底面的背面金属1相连。
第一直线方向和所述第二直线方向位于同一直线上。
实施例2
如图2所示，本实施例源极8由4个呈矩阵排列的圆柱形的源极金属81组成，阵列大小为2×2；栅极7的第一环绕部71由4个呈矩阵排列的闭合环711组成，闭合环711的横截面为正八边形；漏极5的第二环绕部51具有4个呈矩阵排列的通孔53，通孔53为正八边形孔；第二环绕部51的外边缘为非闭合八边形，第二环绕部51一侧开设有2个开口；从衬底2底部向上开设4个背孔9至源极金属81。其他结构与实施例1相同。
以上实施例仅表示本发明的几种实施方式，其描述较为具体和详细，但并不能理解为对本发明范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明保护范围。因此本发明的保护范围应该以权利要求为准。
Claims (5)
1.一种矩阵排列的环形FET器件，从下至上包括衬底、缓冲层及势垒层，其特征在于，还包括环形隔离区、栅极、源极及漏极，环形隔离区形成于势垒层表面且延伸至缓冲层内部；源极由若干个呈矩阵排列的源极金属组成，每个源极金属形成于势垒层上且底部延伸至缓冲层；栅极包括第一环绕部和第一延伸部，第一环绕部由若干个呈矩阵排列的闭合环组成，闭合环与源极金属一一对应，且闭合环环绕对应的源极金属，每个闭合环与同一行相邻的闭合环连接；第一延伸部从每一行位于边缘的闭合环引出，并沿第一直线方向延伸覆盖至环形隔离区；漏极包括第二环绕部和第二延伸部，第二环绕部具有若干个呈矩阵排列的通孔，每个通孔与同一行相邻的通孔连通，通孔与闭合环一一对应，且闭合环位于对应的通孔内；第二延伸部从第二环绕部沿第二直线方向延伸覆盖至环形隔离区；从衬底底部向上开设若干背孔至源极金属，背孔与源极金属一一对应，且每个源极金属经对应的背孔通过连接金属与衬底底面的背面金属相连，源极通过背面通孔接地。
2.根据权利要求1所述的矩阵排列的环形FET器件，其特征在于，所述源极金属为圆柱形，所述闭合环为闭合圆环，所述通孔为圆孔。
3.根据权利要求1所述的矩阵排列的环形FET器件，其特征在于，所述源极金属的横截面为多边形，所述第一环绕部为闭合的多边环形，所述通孔为为非闭合的多边形，且源极金属、第一环绕部及通孔的边数相同。
4.根据权利要求2或3所述的矩阵排列的环形FET器件，其特征在于，所述第二环绕部的外边缘为非闭合圆形或多边形，第二环绕部一侧开设有若干个开口，开口与每一行边缘的通孔一一对应且连通，第一延伸部从每个开口处穿出。
5.根据权利要求1所述的矩阵排列的环形FET器件，其特征在于，所述第一直线方向和所述第二直线方向位于同一直线上。
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