CN107275317B - 一种薄膜陶瓷电路三维堆叠结构 - Google Patents

一种薄膜陶瓷电路三维堆叠结构 Download PDF

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CN107275317B
CN107275317B CN201710371900.0A CN201710371900A CN107275317B CN 107275317 B CN107275317 B CN 107275317B CN 201710371900 A CN201710371900 A CN 201710371900A CN 107275317 B CN107275317 B CN 107275317B
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秦跃利
王春富
李彦睿
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CETC 2 Research Institute
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Abstract

本发明提供了一种薄膜陶瓷电路三维堆叠结构，在相邻两层薄膜陶瓷基板之间，通过植球焊接或预制焊盘焊接，从而实现三层以上薄膜陶瓷电路基板的堆叠；采用实心金属通孔实现任意层导电连接；包括芯片和/或无源元器件的局部电磁自屏蔽结构；所述局部电磁自屏蔽结构包括上下两层金属层和侧面实心金属通孔。能够实现薄膜陶瓷电路堆叠，使有源芯片、射频、大功率、宽带转接等结构在三维方向一体化集成，减少功能核心平面面积70%以上，有效提高产品的集成度，并同步实现气密封装和电磁自屏蔽，提高产品适应性。可替代60~70%同类型产品，节约成本60%以上，提高生产效率40%以上。

Description

一种薄膜陶瓷电路三维堆叠结构
技术领域
本发明涉及一种薄膜陶瓷电路三维堆叠结构，特别是涉及一种无源元器件集成领域的薄膜陶瓷电路三维堆叠结构。
背景技术
现有高密度集成工艺主要采用多芯片组件（SIP）技术，其将MMIC /ASIC 等芯片和微小型片式元件组装在LTCC或多层PCB基板上，采用金丝键合等方式实现元器件和多功能基板的级联。其不足之处主要在于：一方面所有功能单元都在基板二维方向上平铺安装，嵌入器件的互连设计较为复杂，产品体积较大，成本较高，不便于独立测试；另一方面LTCC或PCB基板工艺在图形线宽/线距、任意层互连、无源器件集成等方面限制较大，其无法一体化集成部分高性能单元。
发明内容
本发明要解决的技术问题是提供一种实现薄膜陶瓷电路立体互联的薄膜陶瓷电路三维堆叠结构。
本发明采用的技术方案如下：一种薄膜陶瓷电路三维堆叠结构，在相邻两层薄膜陶瓷基板之间，通过植球焊接或预制焊盘焊接，从而实现三层以上薄膜陶瓷电路基板的堆叠；采用实心金属通孔实现任意层导电连接；包括芯片和/或无源元器件的局部电磁自屏蔽结构；所述局部电磁自屏蔽结构包括上下两层金属层和侧面实心金属通孔。
进一步地，包括支撑层，所述支撑层和支撑层上下层之间形成一个盲腔结构，实现对芯片和/或无源元器件的内埋。
进一步地，根据每一层薄膜陶瓷电路的电路特性，设置各层薄膜陶瓷电路基板的基材。
进一步地，还包括堆叠结构封装结构。
进一步地，所述封装结构采用气密转接板实现气密封装。
进一步地，所述气密转接板采用实心气密孔实现气密封装。
进一步地，所述封装结构采用植球焊接实现对外互联，形成标准化端口。
进一步地，所述封装结构采用金属屏蔽腔实现对内部薄膜陶瓷电路三维堆叠结构的电磁屏蔽。
与现有技术相比，本发明的有益效果是：设计可以实现薄膜陶瓷电路堆叠，使有源芯片、射频、大功率、宽带转接等结构在三维方向一体化集成，减少功能核心平面面积70%以上，有效提高产品的集成度，并同步实现气密封装和电磁自屏蔽，提高产品适应性。可替代60~70%同类型产品，节约成本60%以上，提高生产效率40%以上。
附图说明
图1为本发明其中一具体实施例的三维堆叠电路总体封装结构图。
图2为本发明其中一具体实施例三维堆叠电路多层陶瓷板结构图。
图3为本发明其中一具体实施例三维堆叠电路多层陶瓷板结构分解图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本发明，并不用于限定本发明。
本说明书（包括摘要和附图）中公开的任一特征，除非特别叙述，均可被其他等效或者具有类似目的的替代特征加以替换。即，除非特别叙述，每个特征只是一系列等效或类似特征中的一个例子而已。
具体实施例1
一种薄膜陶瓷电路三维堆叠结构，在相邻两层薄膜陶瓷基板之间，通过植球焊接或预制焊盘3-1焊接，从而实现三层以上薄膜陶瓷电路基板的堆叠；采用实心金属通孔实现任意层导电连接；包括芯片2-4和/或无源元器件的局部电磁自屏蔽结构；所述局部电磁自屏蔽结构包括上下两层金属层和侧面实心金属通孔。
相邻两层之间通过植球焊接或预制焊盘焊接，在图3所示的具体实施例中，相邻两层之间通过预制焊盘焊接实现基板的堆叠，同样的，也可以选择使用植球（如BGA植球）焊接实现基板的堆叠，本领域技术人员可以根据实习需求选择设置。
如图2和图3所示，需要导电连接的薄膜陶瓷电路板设置有通孔2-1，3-7；所述通孔为实心金属通孔，在本具体实施例中所述实心金属通孔为实心铜通孔，然而，本领域技术人员能够根据实际需求，选择通孔中的金属的类型，实现任意层高速互联传输。
在本发明方案中，在堆叠结构中，实现对芯片和/或无源元器件的局部电磁自屏蔽结构，本具体实施例中，对芯片2-4和/或无源元器件（如滤波器3-5、电阻3-6以及电容等）所在层的上面相邻层和下面相邻层各设置金属层，以及侧面的实现金属通孔，实现对芯片和/或无源元器件的局部电磁自屏蔽结构。
本发明申请方案实现了薄膜陶瓷电路的三维堆叠结构，使电路体积向三维延伸，提高了结构密度，实现射频、功率和转换等单元的一体化集成，降低了电路成本。
在本具体实施例中互联采用AuSn预制焊盘焊接集成。
具体实施例2
在具体实施例1的基础上，包括支撑层2-2，所述支撑层和支撑层上下层之间形成一个盲腔结构2-3，实现对芯片和/或无源元器件（如滤波器3-5、电阻3-6以及电容等）的内埋。在本具体实施例中，控制单元层3-2和功率单元层3-4采用金丝键合和倒装焊方式集成芯片。
具体实施例3
在具体实施例1或2的基础上，根据每一层薄膜陶瓷电路的电路特性，设置各层薄膜陶瓷电路基板的基材。能够根据每一层薄膜陶瓷电路的电路特性，设置各层薄膜陶瓷电路基板的基材，如射频滤波单元层3-3采用铁氧体基材（在本具体实施例中采用介电常数大于等于20，小于等于40的高介电铁氧体），控制单元层3-2采用氧化铝基材，功率单元层3-4采用氮化铝基材；这样，各层薄膜陶瓷电路基板能够采用不同的基材，实现各层结构性能的优化组合。本具体实施例多个单元层选用的基材只是一种举例，本领域技术人员能够根据电路特性和实际需求，选择不同的基材，从而实现这个三维结构整体性能的优化组合。
具体实施例4
在具体实施例1到3之一的基础上，如图1所示，还包括堆叠结构封装结构。在本发明方案中，对单个多层陶瓷板堆叠结构1-3进行封装，形成独立功能核心。
具体实施例5
在具体实施例4的基础上，所述封装结构采用气密转接板1-2实现气密封装。如图1所示，，实现功能核心整体气密。
具体实施例6
在具体实施例5的基础上，如图1所示，所述气密转接板采用实心气密孔1-5实现气密封装。
具体实施例7
在具体实施例4到6之一的基础上，所述封装结构采用植球焊接1-4实现对外互联，形成标准化端口。如图1所示，在本具体实施例中，封装结构采用在气密转接板上采用BGA方式实现对外互联，形成标准化端口，便于测试。
具体实施例8
在具体实施例4到7之一的基础上，如图1所示，在本具体实施例中，所述封装结构采用金属屏蔽腔1-1实现对内部薄膜陶瓷电路三维堆叠结构的电磁屏蔽，从而实现对单个多层陶瓷板堆叠结构1-3的电磁屏蔽。
内部自屏蔽及单个堆叠结构电磁屏蔽的情况下，则不再需要对多个堆叠结构构成的整个电路结构进行再次屏蔽。

Claims (8)

1.一种薄膜陶瓷电路三维堆叠结构，其特征在于：在相邻两层薄膜陶瓷基板之间，通过植球焊接或预制焊盘焊接，从而实现三层以上薄膜陶瓷电路基板的堆叠；采用实心金属通孔实现任意层导电连接；包括芯片和/或无源元器件的局部电磁自屏蔽结构；所述局部电磁自屏蔽结构包括芯片和/或无源元器件所在层的上下两层金属层和侧面实心金属通孔。
2.根据权利要求1所述的薄膜陶瓷电路三维堆叠结构，其特征在于：包括支撑层，所述支撑层和支撑层上下层之间形成一个盲腔结构，实现对芯片和/或无源元器件的内埋。
3.根据权利要求1所述的薄膜陶瓷电路三维堆叠结构，其特征在于：根据每一层薄膜陶瓷电路的电路特性，设置各层薄膜陶瓷电路基板的基材。
4.根据权利要求1所述的薄膜陶瓷电路三维堆叠结构，其特征在于：还包括堆叠结构封装结构。
5.根据权利要求4所述的薄膜陶瓷电路三维堆叠结构，其特征在于：所述封装结构采用气密转接板实现气密封装。
6.根据权利要求5所述的薄膜陶瓷电路三维堆叠结构，其特征在于：所述气密转接板采用实心气密孔实现气密封装。
7.根据权利要求4所述的薄膜陶瓷电路三维堆叠结构，其特征在于：所述封装结构采用植球焊接实现对外互联，形成标准化端口。
8.根据权利要求4到7之一所述的薄膜陶瓷电路三维堆叠结构，其特征在于：所述封装结构采用金属屏蔽腔实现对内部薄膜陶瓷电路三维堆叠结构的电磁屏蔽。
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