CN107258017B - 共享鳍或纳米线的场效应器件的器件隔离 - Google Patents

共享鳍或纳米线的场效应器件的器件隔离 Download PDF

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CN107258017B
CN107258017B CN201680011904.1A CN201680011904A CN107258017B CN 107258017 B CN107258017 B CN 107258017B CN 201680011904 A CN201680011904 A CN 201680011904A CN 107258017 B CN107258017 B CN 107258017B
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transistor
fin
effective
isolated
work function
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CN107258017A (zh
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V·马赫卡奥特桑
M·巴达罗格鲁
J·J·徐
S·S·宋
C·F·耶普
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Qualcomm Inc
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Qualcomm Inc
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Abstract

一种集成电路(IC)器件包括在第一类型区域中的第一类型(N型)的第一纳米线GAA有效晶体管(810)。第一有效晶体管可具有在有源部分中的第一类型功函数材料(824，NWFM)和低沟道掺杂剂浓度。该集成电路还包括第二纳米线GAA有效晶体管(810)，其使用与第一有效晶体管相同的纳米线沟道。该IC器件还包括在第一类型区域中的第一类型的第一隔离晶体管(结扎840)，其共享第一和第二有效纳米线GAA晶体管的纳米线。第一隔离晶体管(结扎840)被安排在第一和第二有效晶体管之间并且具有与相同纳米线上的有效晶体管的功函数相反的功函数(832PWFM)。此外，有效晶体管(P型)可使用并行纳米线来安排并且可具有第二类型功函数材料(834)。

Description

共享鳍或纳米线的场效应器件的器件隔离
背景
领域
本公开的各方面涉及半导体器件，尤其涉及毗邻器件之间的隔离。
背景技术
随着集成电路(IC)技术的进步，器件几何形状减小。减小几何形状和器件之间的“节距”(间隔)可使得器件在恰当操作方面相互干扰。
基于鳍的器件是半导体基板的表面上的三维结构。基于鳍的晶体管(其可以是基于鳍的金属氧化物半导体场效应晶体管(MOSFET))可被称为FinFET。纳米线场效应晶体管(FET)也是半导体基板的表面上的三维结构。纳米线FET包括纳米线的掺杂部分，这些掺杂部分接触沟道区并且用作该器件的源极和漏极区。纳米线FET也是MOSFET器件的示例。
MOSFET器件的性能可被众多因素影响，包括沟道长度、应变和外部电阻。对MOSFET器件的性能作出贡献的一个显著因素是毗邻器件之间的干扰。毗邻器件之间的干扰是先进技术节点(其中几何形状和器件之间的节距大为减小)的器件性能和缩放限制因素。
概述
一种集成电路(IC)器件可包括在第一类型区域中的第一类型的第一有效晶体管。第一有效晶体管可具有在第一有效晶体管的有源部分中的第一类型功函数材料和低沟道掺杂剂浓度。该IC器件还可包括在第一类型区域中的第一类型的第一隔离晶体管。第二有效晶体管可具有在第一隔离晶体管的有源部分中的第二类型功函数材料和低沟道掺杂剂浓度。第一隔离晶体管可被安排成毗邻第一有效晶体管。
描述了一种用于更改集成电路(IC)器件内的隔离晶体管的功函数材料的方法。该方法可包括暴露第一类型区域中毗邻第一类型有效晶体管布置的隔离晶体管的第一类型功函数材料。该方法还可包括蚀刻该隔离晶体管的第一类型功函数材料以在第一类型区域内形成该隔离晶体管的第二类型功函数材料。该方法可进一步包括在该隔离晶体管的第二类型功函数材料上沉积导电填充材料。
一种集成电路(IC)器件可包括在第一类型区域中的第一类型的第一有效晶体管。第一有效晶体管可具有在第一有效晶体管的有源部分中的第一类型功函数材料和低沟道掺杂剂浓度。该IC器件还可包括用于隔离第一有效晶体管的第一装置。第一隔离装置可被安排成毗邻第一有效晶体管。
这已较宽泛地勾勒出本公开的特征和技术优势以便下面的详细描述可以被更好地理解。本公开的附加特征和优点将在下文描述。本领域技术人员应该领会，本公开可容易地被用作修改或设计用于实施与本公开相同的目的的其他结构的基础。本领域技术人员还应认识到，这样的等效构造并不脱离所附权利要求中所阐述的本公开的教导。被认为是本公开的特性的新颖特征在其组织和操作方法两方面连同进一步的目的和优点在结合附图来考虑以下描述时将被更好地理解。然而，要清楚理解的是，提供每一幅附图均仅用于解说和描述目的，且无意作为对本公开的限定的定义。
附图简述
为了更全面地理解本公开，现在结合附图参阅以下描述。
图1解说了本公开的一方面中的半导体晶片的立体图。
图2解说了根据本公开的一方面的管芯的横截面视图。
图3解说了本公开的一方面中的金属氧化物半导体场效应晶体管(MOSFET)器件的横截面视图。
图4解说了根据本公开的一方面的鳍式场效应晶体管(FinFET)。
图5解说了根据本公开的一方面的其中通过更改隔离器件的功函数材料来隔离毗邻器件的集成电路(IC)器件的立体视图。
图6A-6J是解说根据本公开的一方面的图5的IC器件的鳍下区域隔离的横截面视图。
图7A-7I解说了示出本公开的一方面的更改图5的IC器件中的隔离器件的功函数材料的横截面视图。
图8解说了根据本公开的一方面的其中通过更改隔离器件的功函数材料来隔离毗邻器件的集成电路(IC)器件的立体视图。
图9解说了根据本公开的一方面的其中通过更改隔离器件的功函数材料来隔离毗邻器件的IC器件的布局视图。
图10A和10B解说了根据本公开的一方面的用于制造其中通过更改隔离器件的功函数材料来隔离毗邻器件的IC器件的方法。
图11是示出其中可有利地采用本公开的一方面的示例性无线通信系统的框图。
图12是解说根据一种配置的用于基于鳍的结构的电路、布局、以及逻辑设计的设计工作站的框图。
详细描述
以下结合附图阐述的详细描述旨在作为各种配置的描述，而无意表示可实践本文中所描述的概念的仅有的配置。本详细描述包括具体细节以便提供对各种概念的透彻理解。然而，对于本领域技术人员将显而易见的是，没有这些具体细节也可实践这些概念。在一些实例中，以框图形式示出众所周知的结构和组件以避免湮没此类概念。如本文所述的，术语“和/或”的使用旨在代表“可兼性或”，而术语“或”的使用旨在代表“排他性或”。
半导体制造工艺通常被分为三个部分：前端制程(FEOL)、中部制程(MOL)以及后端制程(BEOL)。前端制程包括晶片制备、隔离、阱形成、栅极图案化、分隔件、和掺杂植入。中部制程包括栅极和端子触点形成。然而，中部制程的栅极和端子触点形成是制造流程的越发有挑战的部分，尤其是对于光刻图案化而言。后端制程包括形成互连和电介质层以用于耦合到FEOL器件。FEOL器件的形成可涉及隔离毗邻器件以减少邻器件干扰。
随着集成电路(IC)技术的进步，器件几何形状减小。在先进的逻辑技术中，几何形状和器件之间的“节距”(间隔)已经显著地减小。例如，在七(7)纳米逻辑技术中，鳍节距被高度缩小(例如，21到24纳米)且接触的栅极节距也大为减小(例如，39至45纳米)。
基于鳍的器件代表IC技术中的显著进步。基于鳍的器件是半导体基板的表面上的三维结构。基于鳍的晶体管(其可以是基于鳍的金属氧化物半导体场效应晶体管(MOSFET))可被称为FinFET。纳米线场效应晶体管(FET)也代表IC技术中的显著进步。基于栅极全包围(GAA)纳米线的器件也是半导体基板的表面上的三维结构。基于GAA纳米线的器件包括纳米线的掺杂部分，这些掺杂部分接触沟道区并且用作该器件的源极和漏极区。基于GAA纳米线的器件也是MOSFET器件的示例。
MOSFET器件的性能可被众多因素影响，包括沟道长度、应变和外部电阻。例如，半导体器件操作通常涉及将一个器件与另一器件隔离。结果，毗邻器件之间的干扰是可造成MOSFET器件性能降级的一种显著因素。具体而言，毗邻器件之间的干扰是先进技术节点(其中几何形状和器件之间的间隔大为减小)的器件性能和缩放限制因素。
在平面结构、基于鳍的结构、基于GAA纳米线的结构或其他类似三维结构中，毗邻器件(诸如晶体管)可以在物理上隔离和/或电隔离。可执行毗邻有源区之间的物理断开，以断开毗邻晶体管的有源区。该断开可涉及使用例如切割步骤来分裂有源区，以断开毗邻晶体管的有源区或两个毗邻器件之间的某种其他物理障碍。虽然此类办法可以提供完全电隔离，但物理断开(例如，切割步骤)不是自对准的。物理断开中缺乏自对准可导致性能可变性，同时涉及计及这两个毗邻器件之间所创建的物理障碍的器件面积惩罚。
可执行毗邻有源区之间的电断开，以电断开毗邻隔离器件的有源区。在这种电隔离中，近旁(或毗邻)晶体管可被用作隔离器件。此类隔离器件可被称为“结扎(tie-off)”器件，其中结扎器件的有源区被设置成截止状态。截止状态可取决于电荷承载器件的类型而有所不同。例如，在n型器件中，结扎器件可将栅极绑定至低电势，而对于p型器件，结扎器件可将栅极绑定至高电势。可以偏置隔离晶体管(例如，结扎器件)的栅极以将该隔离晶体管置于截止状态并且提供对毗邻有效器件的隔离。
在相关技术办法中，结扎器件(例如，晶体管的栅极)可以有与期望有效器件相同的电荷载流子。在此类情形中，结扎器件可使用与用于制造有效器件的处理步骤类似的处理步骤来制造。即，用于制造结扎器件的栅极、源极和漏极、以及栅极触点的处理步骤、以及结扎器件的特性(例如，阈值电压(Vt)、漏泄电流I截止、栅极长度等)将类似于用于制造有效器件的处理步骤、以及有效器件的特性。例如，如果有效器件是高性能器件，则有效器件的阈值电压(Vt)可能较低。结果，隔离器件也被制造成具有低阈值电压。在没有物理断开的情况下，不可忽视的漏泄电流I截止将由于低阈值电压(例如，在高于该电压的情况下器件被激活)而跨隔离器件存在。
本公开的各个方面提供了用于通过更改隔离器件的功函数材料来隔离毗邻器件的技术。用于更改有效器件或隔离器件的功函数材料的工艺流程可包括前端制程(FEOL)工艺、中部制程(MOL)工艺和后端制程(BEOL)工艺。将理解，术语“层”包括膜且不应被解读为指示纵向或横向厚度，除非另外声明。如本文中所描述的，术语“基板”或者可指代已切割晶片的基板或者可指代尚未切割的晶片的基板。类似地，术语晶片和管芯可互换使用，除非这种互换将难以置信。
本公开的诸方面包括用于更改布置在基于鳍的有效器件或基于鳍的隔离器件的有源源极区/漏极区上的功函数材料的创新集成流程。本公开的附加方面可更改布置在基于栅极全包围(GAA)纳米线的器件和其他类似三维结构的有源源极区/漏极区上的功函数材料以减少隔离器件内的漏泄电流。使用经更改功函数材料的毗邻器件隔离可使得能够在先进逻辑技术(诸如七(7)纳米逻辑技术以及之后的逻辑技术)的减小的器件几何形状内进行操作。功函数更改对于有效器件而言是自对准的并且可使用现有材料和工艺能力来执行，而没有附加步骤。本公开的此方面还提供了用于在有效电路区域内形成隔离器件的制造惩罚的减少。
本公开的一个方面更改了有效器件或结扎器件的功函数材料，以使得有效器件和相应的结扎器件具有不同的功函数材料。对于高性能有效器件(其具有低阈值电压)而言，在相应的结扎器件中具有相似的功函数材料(例如，p型功函数金属(PWFM)或n型功函数金属(NWFM))增大了漏泄电流的可能性。通过更改有效器件或结扎器件的功函数材料(这可以在栅极堆叠中完成)，结扎器件的阈值从较低阈值电压改变成较高阈值电压。这可以改变漏泄电流，并且还可以提供该有效器件与其他有效器件(诸如集成电路上的毗邻有效器件)之间的隔离。
图1解说了本公开的一方面中的半导体晶片的立体视图。晶片100可以是半导体晶片，或者可以是在晶片100的表面上具有一层或多层半导体材料的基板材料。当晶片100是半导体材料时，其可使用切克劳斯基(Czochralski)工艺从籽晶生长，其中籽晶被浸入半导体材料的熔池中，并且缓慢旋转并从池中被移除。熔融材料随后在晶体的取向上结晶到籽晶上。
晶片100可以是复合材料，诸如砷化镓(GaAs)或氮化镓(GaN)、诸如砷化铟镓(InGaAs)之类的三元材料、四元材料、或者可以是用于其他半导体材料的基板材料的任何材料。虽然许多材料本质上可以是晶体，但是多晶或非晶材料也可用于晶片100。
晶片100或者耦合到晶片100的各层可被提供有使晶片100更具导电性的材料。作为示例而非限定，硅晶片可具有添加到晶片100的磷或硼以允许电荷在晶片100中流动。这些添加剂被称为掺杂剂，并且在晶片100或晶片100的各部分内提供额外的电荷载流子(电子或空穴)。通过选择提供额外的电荷载流子的区域、提供哪种类型的电荷载流子、以及晶片100中附加的电荷载流子的量(密度)，可在晶片100中或晶片100上形成不同类型的电子器件。
晶片100具有指示该晶片100的晶向的取向102。取向102可以是如图1中所示的晶片100的平坦边缘，或者可以是槽口或其他标记以解说晶片100的晶向。取向102可指示晶片100中晶格的平面的米勒指数。
米勒指数形成晶格中结晶平面的标记系统。晶格平面可以由三个整数h、k和指示，这些整数是晶体中平面()的米勒指数。每个指数表示基于倒易晶格矢量与方向()正交的平面。这些整数通常以最低项写出(例如，它们的最大公约数应为1)。米勒指数100表示与方向h正交的平面；指数010表示与方向k正交的平面，并且指数001表示与正交的平面。对于一些晶体，使用负数(被写为指数上方的横条)，并且对于一些晶体(诸如氮化镓)，可以采用三个以上数字以充分描述不同的结晶平面。
一旦按期望处理了晶片100，就沿着切割线104分割晶片100。切割线104指示晶片100将在何处被分离或分开成多片。切割线104可限定已在晶片100上制造的各种集成电路的轮廓。
一旦限定了切割线104，晶片100就可被锯成或以其他方式分成多片以形成管芯106。每个管芯106可以是具有许多器件的集成电路或者可以是单个电子器件。管芯106(其也可被称为芯片或半导体芯片)的物理尺寸至少部分地取决于将晶片100分成特定大小的能力、以及管芯106被设计成包含个体器件的数量。
一旦晶片100已被分成一个或多个管芯106，管芯106就可被安装到封装中，以允许访问在管芯106上制造的器件和/或集成电路。封装可包括单列直插封装、双列直插封装、母板封装、倒装芯片封装、铟点/凸点封装、或者提供对管芯106的访问的其他类型的器件。还可通过线焊、探针、或者其他连接来直接访问管芯106，而无需将管芯106安装到分开的封装中。
图2解说了根据本公开的一方面的管芯106的横截面视图。在管芯106中，可存在基板200，其可以是半导体材料和/或可充当对电子器件的机械支持。基板200可以是掺杂的半导体基板，其具有存在于基板200中各处的电子(指定为N沟道)或空穴(指定为P沟道)电荷载流子。用电荷载流子离子/原子对基板200的后续掺杂可改变基板200的电荷携带能力。
在基板200(例如，半导体基板)内，可存在阱202和204，这些阱可以是场效应晶体管(FET)的源极和/或漏极，或者阱202和/或204可以是具有鳍结构的FET(FinFET)的鳍结构。取决于阱202和/或204的结构和其他特性以及基板200的外围结构，阱202和/或204还可以是其他器件(例如，电阻器、电容器、二极管、或其他电子器件)。
半导体基板还可具有阱206和阱208。阱208可完全在阱206内，并且在一些情形中，可形成双极结型晶体管(BJT)。阱206还可被用作隔离阱，以将阱208与管芯106内的电场和/或磁场隔离。
可将各层(例如，210到214)添加到管芯106。层210可以是例如氧化物或绝缘层，其可将阱(例如，202-208)彼此隔离或者与管芯106上的其他器件隔离。在此类情形中，层210可以是二氧化硅、聚合物、电介质、或者另一电绝缘层。层210也可以是互连层，在该情形中，层210可包括导电材料，诸如铜、钨、铝、合金、或者其他导电或金属材料。
取决于期望的器件特性和/或各层(例如，210和214)的材料，层212也可以是电介质或导电层。层214可以是封装层，其可保护各层(例如，210和212)、以及阱202-208和基板200免受外力。作为示例而非限定，层214可以是保护管芯106免受机械损害的层，或者层214可以是保护管芯106免受电磁或辐射损害的材料层。
在管芯106上设计的电子器件可包括许多特征或结构组件。例如，管芯106可暴露于任何数量的方法以将掺杂剂传递到基板200、阱202-208中，并且如果期望，传递到层(例如，210-214)中。作为示例而非限定，管芯106可暴露于离子注入、掺杂剂原子的沉积，这些掺杂剂原子通过扩散工艺、化学气相沉积、外延生长、或其他方法被驱入晶格中。通过各层(例如，210-214)的诸部分的选择性生长、材料选择以及移除，并且通过基板200和阱202-208的选择性移除、材料选择以及掺杂剂浓度，可在本公开的范围内形成许多不同的结构和电子器件。
此外，基板200、阱202-208、以及各层(例如，210-214)可通过各种工艺被选择性地移除或添加。化学湿法蚀刻、化学机械平坦化(CMP)、等离子体蚀刻、光致抗蚀剂掩模、镶嵌工艺、以及其他方法可创建本公开的结构和器件。
图3解说了本公开的一方面中的金属氧化物半导体场效应晶体管(MOSFET)器件300的横截面视图。MOSFET器件300可具有四个输入端子。这四个输入是源极302、栅极304、漏极306和基板308。源极302和漏极306可制造为基板308中的阱202和204，或者可制造为基板308上方的区域，或者制造为管芯106上的其它层的一部分。此类其他结构可以是鳍或者从基板308的表面突出的其他结构。此外，基板308可以是管芯106上的基板200，但是基板308也可以是耦合到基板200的各层(例如，210-214)中的一层或多层。
MOSFET器件300是单极器件，这是因为取决于MOSFET的类型，电流仅由一种类型的电荷载流子(例如，电子或空穴)产生。MOSFET器件300通过控制在源极302与漏极306之间的沟道310中的电荷载流子的量来操作。电压V源极312施加于源极302，电压V栅极314施加于栅极304，并且电压V漏极316施加于漏极306。分开的电压V基板318也可施加于基板308，尽管电压V基板318可耦合到电压V源极312、电压V栅极314或电压V漏极316中的一者。
为了控制沟道310中的电荷载流子，当栅极304累积电荷时，电压V栅极314在沟道310中创建电场。与在栅极304上累积的电荷相反的电荷开始在沟道310中累积。栅极绝缘体320将在栅极304上累积的电荷与源极302、漏极306以及沟道310绝缘。栅极304和沟道310(两者之间具有栅极绝缘体320)创建电容器，并且当电压V栅极314增加时，充当该电容器的一个极板的栅极304上的电荷载流子开始累积。栅极304上的这种电荷累积将相反的电荷载流子吸引到沟道310中。最终，足够的电荷载流子在沟道310中累积，以提供源极302与漏极306之间的导电路径。该状况可被称为打开FET的沟道。
通过改变电压V源极312和电压V漏极316、以及它们与电压V栅极314的关系，施加于栅极304以打开沟道310的电压量可以变化。例如，电压V源极312通常具有比电压V漏极316的电位高的电位。使电压V源极312与电压V漏极316之间的电压差更大将改变用于打开沟道310的电压V栅极314的量。此外，较大的电压差将改变使电荷载流子移动通过沟道310的电动势的量，从而创建通过沟道310的较大电流。
栅极绝缘体320材料可以是氧化硅，或者可以是电介质或者具有与氧化硅不同的介电常数(k)的其他材料。此外，栅极绝缘体320可以是材料的组合或者不同的材料层。例如，栅极绝缘体320可以是氧化铝、氧化铪、氮氧化铪、氧化锆、或者这些材料的层叠和/或合金。可使用用于栅极绝缘体320的其他材料，而不会脱离本公开的范围。
通过改变用于栅极绝缘体320的材料、以及栅极绝缘体320的厚度(例如，栅极304与沟道310之间的距离)，栅极304上用于打开沟道310的电荷量可以变化。还解说了示出MOSFET器件300的各端子的符号322。对于N沟道MOSFET(使用电子作为沟道310中的电荷载流子)，向符号322中的基板308端子应用远离栅极304端子的箭头。对于p型MOSFET(使用空穴作为沟道310中的电荷载流子)，向符号322中的基板308端子应用指向栅极304端子的箭头。
栅极304也可由不同的材料制成。在一些设计中，栅极304由多结晶硅(polycrystalline silicon)制成，多结晶硅也被称为多晶硅(polysilicon)或多晶(poly)，其是硅的导电形式。虽然本文中被称为“多晶”或“多晶硅”，但金属、合金或其他导电材料也被构想为用于如本公开中所描述的栅极304的恰适材料。
在一些MOSFET设计中，在栅极绝缘体320中可能期望高k值材料，并且在此类设计中，可采用其他导电材料。作为示例而非限定，“高k金属栅极”设计可将金属(诸如铜)用于栅极304端子。虽然被称为“金属”，但多结晶材料、合金或其他导电材料也被构想为用于如本公开中所描述的栅极304的恰适材料。
为了互连到MOSFET器件300，或者为了互连到管芯106中的其他器件(例如，半导体)，使用互连迹线或互连层。这些互连迹线可在各层(例如，210-214)中的一层或多层中，或者可以在管芯106的其他层中。
图4解说了根据本公开的一方面的晶体管。具有鳍结构的FET(FinFET 400)以与针对图3所描述的MOSFET器件300类似的方式来操作。然而，FinFET 400中的鳍410生长或者以其它方式耦合到基板308。基板308可以是半导体基板或者例如包括氧化物层、氮化物层、金属氧化物层或硅层的其他类似的支承层。鳍410包括源极302和漏极306。栅极304通过栅极绝缘体320来布置在鳍410上以及基板308上。高度H鳍、宽度W鳍和长度L鳍表示该鳍的维度。在FinFET结构中，FinFET 400的物理尺寸可小于图3中所示的MOSFET器件300结构。物理尺寸的这种减小允许在管芯106上每单位面积更多的器件。
具有经调整功函数的毗邻器件隔离
随着集成电路(IC)技术的进步，器件几何形状减小。在先进的逻辑技术中，几何形状和器件之间的“节距”(间隔)已经显著地减小。例如，在七(7)纳米逻辑技术中，鳍节距被高度缩小(例如，21到24纳米)且接触的栅极节距也大为减小(例如，39至45纳米)。
基于鳍的器件代表IC技术中的显著进步。基于鳍的器件是半导体基板的表面上的三维结构。基于鳍的晶体管(其可以是基于鳍的金属氧化物半导体场效应晶体管(MOSFET))可被称为FinFET。纳米线场效应晶体管(FET)也代表IC技术中的显著进步。基于栅极全包围(GAA)纳米线的器件也是半导体基板的表面上的三维结构。基于GAA纳米线的器件包括纳米线的掺杂部分，这些掺杂部分接触沟道区并且用作该器件的源极和漏极区。基于GAA纳米线的器件也是MOSFET器件的示例。
MOSFET器件的性能可被众多因素影响，包括沟道长度、应变和外部电阻。例如，半导体器件操作通常涉及将一个器件与另一器件隔离。结果，毗邻器件之间的干扰是可造成MOSFET器件性能降级的一种显著因素。具体而言，毗邻器件之间的干扰是先进技术节点(其中几何形状和器件之间的间隔大为减小)的器件性能和缩放限制因素。
在平面结构、基于鳍的结构、基于GAA纳米线的结构或其他类似三维结构中，毗邻器件(诸如晶体管)可以在物理上隔离和/或电隔离。可执行毗邻有源区之间的物理断开以断开毗邻晶体管的有源区。该断开可涉及使用例如切割步骤来分裂有源区，以断开毗邻晶体管的有源区或两个毗邻器件之间的某种其他物理障碍。虽然此类办法可以提供完全电隔离，但物理断开(例如，切割步骤)不是自对准的。物理断开中缺乏自对准可导致性能可变性，同时避免了计及这两个毗邻器件之间所创建的物理障碍的器件面积惩罚。
可执行毗邻有源区之间的电断开，以电断开毗邻隔离器件的有源区。在这种电隔离中，近旁(或毗邻)晶体管可被用作隔离器件。此类隔离器件可被称为“结扎”器件，其中结扎器件的有源区被设置成截止状态。截止状态可取决于电荷承载器件的类型而有所不同。例如，在n型器件中，结扎器件可将栅极绑定至低电势，而对于p型器件，结扎器件可将栅极绑定至高电势。
在相关技术办法中，结扎器件(例如，晶体管的栅极)可以有与期望有效器件相同的电荷载流子。在此类情形中，结扎器件可使用与用于制造有效器件的处理步骤类似的处理步骤来制造。即，用于制造结扎器件的栅极、源极和漏极、以及栅极触点的处理步骤、以及结扎器件的特性(例如，阈值电压(Vt)、漏泄电流I截止、栅极长度等)将类似于用于制造有效器件的处理步骤、以及有效器件的特性。例如，如果有效器件是高性能器件，则有效器件的阈值电压(Vt)可能较低。结果，隔离器件也被制造成具有低阈值电压。在没有物理断开的情况下，不可忽视的漏泄电流I截止将由于低阈值电压(例如，在高于该电压的情况下器件被激活)而跨隔离器件存在。
本公开的各个方面提供了用于通过更改有效器件或隔离器件的功函数材料来隔离毗邻器件的技术。用于更改有效器件或隔离器件的功函数材料的工艺流程可包括前端制程(FEOL)工艺、中部制程(MOL)工艺和后端制程(BEOL)工艺。
本公开的诸方面包括用于更改布置在基于鳍的有效器件或基于鳍的隔离器件的有源源极区/漏极区上的功函数材料的创新集成流程。本公开的附加方面可更改布置在基于栅极全包围(GAA)纳米线的器件和其他类似三维结构的有源源极区/漏极区上的功函数材料以减少隔离器件内的漏泄电流。使用经更改功函数材料的毗邻器件隔离可使得能够在先进逻辑技术(诸如七(7)纳米逻辑技术以及之后的逻辑技术)的减小的器件几何形状内进行操作。功函数更改对于有效器件而言是自对准的并且可使用现有材料和工艺能力来执行，而没有附加步骤。本公开的此方面还提供了用于在有效电路区域内形成隔离器件的制造惩罚的减少。
本公开的一个方面更改了有效器件或结扎器件的功函数材料，以使得有效器件和相应的结扎器件具有不同的功函数材料。对于高性能有效器件(其具有低阈值电压)而言，在相应的结扎器件中具有相似的功函数材料(例如，p型功函数金属(PWFM)或n型功函数金属(NWFM))增大了漏泄电流的可能性。通过更改有效器件或结扎器件的功函数材料(这可以在栅极堆叠中完成)，结扎器件的阈值电压从较低阈值电压被修改成较高阈值电压。这可以减少漏泄电流，同时提供该有效器件与其他有效器件(诸如集成电路上的毗邻有效器件)之间的隔离，而不依赖于物理隔离。
图5解说了根据本公开的一方面的包括隔离器件内的经更改功函数材料的基于鳍的集成电路(IC)器件500的横截面视图。代表性地，基于鳍的IC器件500包括围绕鳍550的浅沟槽隔离(STI)区域504，该鳍550包括由基板502(例如，半导体基板、绝缘体上覆硅(SOI)基板、埋氧化物(BOX)层等)支撑的掺杂鳍下部分570和有效鳍部分580。SOI基板可被完全耗尽。每个有效鳍部分580被布置在一个掺杂鳍下部分570(例如，鳍550的掺杂部分)上。当掺杂鳍下部分570是n型(例如，NFET)时，掺杂鳍下部分570由磷掺杂硅(SiP)、碳磷掺杂硅(SiCP)、磷掺杂硅锗(SiGeP)、磷掺杂锗(GeP)、或其他类似三/五族(III/V)材料构成。当掺杂鳍下部分570是p型(例如，PFET)时，掺杂鳍下部分570由硼掺杂硅锗(SiGeB)、硼掺杂锗(GeB)、或其他类似掺杂材料构成。
在此安排中，基于鳍的IC器件500包括有效器件(例如，有效栅极510)和隔离器件(例如，结扎栅极540)。有效栅极510包括n型区域520内的具有n型功函数材料(NWFM)524的第一部分。有效栅极510还包括p型区域530内的具有p型功函数材料(PWFM)534的第二部分。类似地，结扎栅极540可形成在n型区域520或p型区域530内。然而，在本公开的此方面，结扎栅极540的功函数材料被更改。
例如，尽管结扎栅极540中的一个结扎栅极在n型区域520中，但功函数材料是p型功函数材料(例如，PWFM 534)。同样，尽管结扎栅极540中的另一个结扎栅极在p型区域530中，但功函数材料是n型功函数材料(例如，NWFM 524)。在本公开的此方面，更改结扎栅极540的功函数材料将该结扎器件的阈值从较低阈值电压改变成了较高阈值电压。这可以减小漏泄电流，同时在该有效器件与其他有效器件之间提供改进的电隔离，而无需依赖于隔离器件的物理断开。
在此安排中，有效栅极510包括在有效栅极510的侧壁上的栅极分隔件512(例如，基于氮的低K栅极分隔件)。导电填充材料516(例如，钨(W)或钴(Co))被布置在有效鳍部分580的功函数材料(例如，NWFM 524或PWFM 534)上。功函数材料(例如，NWFM 524或PWFM534)被沉积在栅极分隔件512上的高k介电层514上。基于鳍的IC器件500可如图6A-6J和7A-7I所示地形成。根据本公开的诸方面，IC器件可包括基于栅极全包围(GAA)纳米线的有效器件、基于鳍的有效器件、或其他类似三维有效器件。参照图10A和10B来描述如图6A-7I所示的用于形成基于鳍的IC器件500的过程。
图10A解说了根据本公开的一方面的用于制造包括具有经更改功函数材料的隔离器件的IC器件的方法1000。图10A和10B中所描述的过程使得能够形成如图5、8和9所示的基于鳍的IC器件500。在框1002，示出在完成晶片蚀刻以形成鳍550之后的传入晶片(例如，半导体基板)。例如，如图6A所示，硬掩模554(例如，氮化硅(SiN))和氧化物层552被安排在鳍550(例如，基底鳍部分)上。尽管是参照基于鳍的器件来解说的，但对功函数材料的更改可应用于其他类似三维半导体结构，诸如图8所示的基于GAA纳米线的IC器件。
再次参照图10A，在框1004，对IC器件的n型鳍下区域和p型鳍下区域进行掺杂。例如，如图6B所示，p型掺杂氧化物532(例如，硼)被形成在n型区域520和p型区域530两者内的鳍550、氧化物层552和硬掩模554的侧壁上。在图6C中，硬掩模554被沉积在p型区域530内的p型掺杂氧化物532上。在图6D中，从n型区域520移除p型掺杂氧化物532以暴露鳍550中的一个鳍；p型掺杂氧化物532保留在p型区域530中的鳍550上。
在图6E中，n型掺杂氧化物522(例如，磷或砷的氧化物)被形成在n型区域520内的鳍550、氧化物层552和硬掩模554的侧壁上。另外，n型掺杂氧化物522被沉积在p型区域530内的p型掺杂氧化物532上。图6B-6E所示的过程可使用固态掺杂剂或其他类似阱掺杂剂来执行。这种技术避免了将离子注入到器件的阱中，同时减少鳍下漏泄。通过不执行阱离子注入消除了鳍沟道掺杂。在本公开的一个方面，通过在沟道下面放置阱掺杂剂来用阱掺杂剂代替阱注入。在本公开的此方面，有效器件和隔离器件在器件的有源部分中展现出低沟道掺杂剂浓度。掺杂剂可使用外延工艺来生长。替换地，掺杂剂可以是固态掺杂剂或其他类似阱掺杂剂，其被放置在沟道下面以替代器件的阱内的离子注入。
再次参照图10A，在框1006，沉积浅沟槽隔离(STI)材料并对其进行蚀刻以在掺杂鳍下区域的硬掩模上停止。如图6F所示，沉积浅沟槽隔离材料以形成STI区域504。STI区域504被蚀刻以在鳍550的硬掩模554上停止。如图6G所示，STI区域504、p型掺杂氧化物532和n型掺杂氧化物522被蚀刻以暴露硬掩模554。在框1008，蚀刻硬掩模和氧化物以及STI区域以暴露有效鳍部分。如图6H所示，硬掩模554从鳍550中被移除。在图6I中，STI区域504和氧化物层552被蚀刻以暴露鳍550的有效鳍部分580。
再次参照图10A，在框1010，对基于鳍的IC器件500进行退火来将掺杂剂推进到掺杂鳍下区域中，以形成鳍的掺杂鳍下部分。如图6J所示，n型掺杂氧化物522被推进到鳍550的基底部分中以在n型区域520内形成鳍550的掺杂鳍下部分570，从而形成n型扩散掺杂剂526。另外，p型掺杂氧化物532被推进到掺杂鳍下区域中以在p型区域530内形成鳍550的掺杂鳍下部分570，从而形成p型扩散掺杂剂536。用n型扩散掺杂剂526和p型扩散掺杂剂536来替代平面器件中所使用的离子注入以控制鳍下漏泄。n型扩散掺杂剂526和p型扩散掺杂剂536还可提供n型区域520与p型区域530之间的隔离。如图7A-7I所示，执行栅极形成，其中隔离器件的功函数材料被更改以提高隔离器件的阈值电压，从而减小隔离器件的漏泄电流。
再次参照图10A，在框1012，图案化晶片以在IC器件的有效鳍部分上形成虚设多晶栅极。如图7A所示，描绘了在完成虚设多晶栅极图案化过程以形成虚设多晶栅极(例如，硅(Si))之后的传入晶片。在此示例中，在有效栅极510的图案化期间将硬掩模501(例如，氮化硅(SiN))安排在有效栅极510上。有效栅极510由STI区域504支撑，该STI区域504由基板502支撑。在框1014，在虚设栅极和硬掩模的侧壁上形成栅极分隔件(例如，基于氮的低K栅极分隔件)。例如，如图7B所示，栅极分隔件512被形成在有效栅极510和硬掩模501的侧壁上。另外，氧化物572被沉积在有效鳍部分580上。
图10B进一步解说了图10A的根据本公开的一方面的用于制造包括具有经更改功函数材料的隔离器件的IC器件的方法1000。在框1020，在该IC器件上沉积层间电介质(ILD)并且对该ILD材料执行化学机械抛光(CMP)工艺以在虚设多晶栅极上停止并暴露虚设多晶栅极。如图7C所示，对ILD 506执行CMP工艺以暴露有效栅极510。在框1022，移除虚设栅极并且刷新有效鳍部分上的氧化物层。如图7D所示，移除有效栅极510并且刷新有效鳍部分580上的氧化物572(例如，氧化硅(Si02))以暴露鳍550的有效鳍部分580。在框1024，执行栅极替换过程以用有效栅极替换虚设栅极(例如，如图7E所示)。
如图7E所示，高K介电层514被沉积在有效栅极510和结扎栅极540两者的有效鳍部分580的暴露部分上。第一功函数材料(WFM)(例如，NWFM 524)被沉积在有效栅极510和结扎栅极540两者的n型区域520和p型区域530两者内的有效鳍部分580上。在此安排中，部分地移除该功函数材料以交替地在n型区域520和p型区域530之一中形成第二功函数材料(WFM)(例如，PWFM 534)，如图7F-7I所示。
再次参照图10B，在框1026，在栅极堆叠的功函数材料上沉积间隙填充材料并且在该间隙填充材料上形成光刻掩模。如图7F所示，间隙填充材料508被沉积在n型区域520和p型区域530两者内的n型功函数材料(例如，NWFM 524)上。在图7G中，光刻掩模509被沉积在间隙填充材料508上以定义间隙填充材料508内的开口掩模，以用于交替地暴露n型区域520和p型区域530之一上的功函数材料(例如，NWFM 524)。在框1028，执行去模(strip resist)以形成掩模开口并且随后发生对暴露功函数材料的部分蚀刻。如图7H所示，去模过程移除了光刻掩模509并且形成了交替地暴露n型区域520和p型区域530之一上的功函数材料(例如，NWFM 524)的掩模开口560。例如，对n型功函数材料(例如，NWFM 524)的一部分的部分蚀刻形成了p型区域530内的p型功函数材料(例如，PWFM 534)。
再次参照图10B，在框1030，移除间隙填充材料。在图7I中，间隙填充材料508被移除以通过掩模开口560暴露有效栅极510和结扎栅极540两者的功函数材料(例如，NWFM 524或PWFM 534)。在框1032，通过掩模开口在暴露的功函数材料上沉积导电填充材料，以及对该导电填充材料的CMP工艺完成该IC器件。如图8所示，导电填充材料816(例如，钨(W)或钴(Co))被沉积在n型功函数材料(例如，NWFM 824)和p型功函数材料(PWFM 834)上以完成有效栅极810和结扎栅极840的形成。最后，执行CMP工艺以在ILD 806上停止。
如图8所示，基于栅极全包围(GAA)纳米线的IC器件800包括围绕掺杂区域870且由基板802支撑的STI区域804。有源区880被布置在掺杂区域870上。当掺杂区域870是n型(例如，NFET)时，掺杂区域870由磷掺杂材料构成。当掺杂区域870是p型(例如，PFET)时，掺杂区域870由硼掺杂材料构成。基于GAA纳米线的IC器件800包括有效器件(例如，有效栅极810)和隔离器件(例如，结扎栅极840)。有效栅极810包括n型区域820内的具有n型功函数材料(NWFM)824的第一部分、以及p型区域830内的在高K介电层814上具有p型功函数材料(PWFM)834的第二部分。结扎栅极840可形成在n型区域820或p型区域830内。
在本公开的一个方面，结扎栅极840的功函数材料被更改。例如，尽管结扎栅极840之一在n型区域820中，但功函数材料是p型功函数材料(例如，PWFM 834)。同样，尽管结扎栅极840中的另一个结扎栅极在p型区域830中，但功函数材料是n型功函数材料(例如，NWFM824)。在本公开的此方面，更改结扎栅极840的功函数材料提高了结扎栅极840的阈值电压。这可以减小结扎栅极840的漏泄电流，同时在该有效器件与其他有效器件之间提供改善的电隔离，而不依赖于隔离器件(例如，结扎栅极840)的物理断开。
在此安排中，有效栅极810包括在有效栅极810的侧壁上的栅极分隔件812(例如，基于氮的低K栅极分隔件)。导电填充材料816(例如，钨(W)或钴(Co))被布置在有源区880的功函数材料(例如，NWFM 824或PWFM 834)上。该功函数材料被沉积在栅极分隔件812的高k介电层814上。基于鳍的IC器件500可如图6A-6J和7A-7I所示地形成。基于鳍的IC器件500可包括基于栅极全包围(GAA)纳米线的有效器件、基于鳍的有效器件、或其他类似三维有效器件。参照图10A和10B来描述用于形成基于鳍的IC器件500的过程，如图6A-7I所示。对于基于GAA纳米线的IC器件(例如，如图8所示)，可根据本公开的诸方面来修改此过程。
本公开的诸方面包括用于更改布置在基于鳍的有效器件或基于鳍的隔离器件的有源源极/漏极区上的功函数材料的创新集成流程。本公开的附加方面可更改布置在基于栅极全包围(GAA)纳米线的器件和其他类似三维结构的有源源极/漏极区上的功函数材料以减小该隔离器件内的漏泄电流。使用经更改功函数材料的毗邻器件隔离可使得能够在先进逻辑技术(诸如七(7)纳米逻辑技术和之后的逻辑技术)的减小的器件几何形状内进行操作。功函数更改对于有效器件而言是自对准的并且可使用现有材料和工艺能力来执行，而没有附加步骤。本公开的此方面还提供了用于在有效电路区域内形成隔离器件的制造惩罚的减少。
本公开的一个方面更改了有效器件或结扎器件的功函数材料，以使得有效器件和相应的结扎器件具有不同的功函数材料。对于高性能有效器件(其具有低阈值电压)而言，在相应的结扎器件中具有相似的功函数材料(例如，p型功函数金属(PWFM)或n型功函数金属(NWFM))增大了漏泄电流的可能性。通过更改有效器件或结扎器件的功函数材料(这可以在栅极堆叠中完成)，结扎器件的阈值从较低阈值电压改变成较高阈值电压。这可以减小漏泄电流，并且还可以提供该有效器件与其他有效器件(诸如集成电路上的毗邻有效器件)之间的隔离。
根据本公开的一方面，描述了一种基于鳍的结构。在一种配置中，该基于鳍的结构包括用于在基于鳍的结构的各鳍之间进行隔离的装置。该隔离装置可以是隔离器件(例如，结扎栅极540/840)。在另一方面，前述装置可以是被配置成执行由前述装置叙述的功能的任何模块或任何装备或材料。
图11是示出其中可有利地采用本公开的一方面的示例性无线通信系统1100的框图。出于解说目的，图11示出了三个远程单元1120、1130和1150以及两个基站1140。将认识到，无线通信系统可具有远多于此的远程单元和基站。远程单元1120、1130和1150包括IC器件1125A、1125C和1125B，这些IC器件包括所公开的具有经更改功函数的隔离器件。将认识到，其他设备也可包括所公开的隔离器件，诸如基站、交换设备、和网络装备。图11示出了从基站1140到远程单元1120、1130和1150的前向链路信号1180，以及从远程单元1120、1130和1150到基站1140的反向链路信号1190。
在图11中，远程单元1120被示为移动电话，远程单元1130被示为便携式计算机，并且远程单元1150被示为无线本地环路系统中的固定位置远程单元。例如，远程单元可以是移动电话、手持式个人通信系统(PCS)单元、便携式数据单元(诸如个人数据助理)、启用GPS的设备、导航设备、机顶盒、音乐播放器、视频播放器、娱乐单元、固定位置数据单元(诸如仪表读数装备)、或者存储或检索数据或计算机指令的其他设备、或者其组合。尽管图11解说了根据本公开的各方面的远程单元，但本公开不限于所解说的这些示例性单元。本公开的诸方面可以合适地在包括所公开的隔离器件的许多设备中使用。
图12是解说用于IC结构(诸如以上公开的隔离器件)的电路、布局以及逻辑设计的设计工作站的框图。设计工作站1200包括硬盘1201，该硬盘1201包含操作系统软件、支持文件、以及设计软件(诸如Cadence或OrCAD)。设计工作站1200还包括促成对电路1210或IC器件1212(包括隔离器件)的设计的显示器1202。提供存储介质1204以用于有形地存储电路1210或IC器件1212的设计。电路1210或IC器件1212的设计可以用文件格式(诸如GDSII或GERBER)存储在存储介质1204上。存储介质1204可以是CD-ROM、DVD、硬盘、闪存、或者其他合适的设备。此外，设计工作站1200包括用于从存储介质1204接受输入或者将输出写到存储介质1204的驱动装置1203。
存储介质1204上记录的数据可指定逻辑电路配置、用于光刻掩模的图案数据、或者用于串写工具(诸如电子束光刻)的掩模图案数据。该数据可进一步包括与逻辑仿真相关联的逻辑验证数据，诸如时序图或网电路。在存储介质1204上提供数据通过减少用于设计半导体晶片的工艺数目来促成电路1210或基于鳍的结构1212的设计。
对于固件和/或软件实现，这些方法体系可以用执行本文所描述功能的模块(例如，规程、函数等等)来实现。有形地体现指令的机器可读介质可被用来实现本文所述的方法体系。例如，软件代码可被存储在存储器中并由处理器单元来执行。存储器可以在处理器单元内或在处理器单元外部实现。如本文所用的，术语“存储器”是指长期、短期、易失性、非易失性类型存储器、或其他存储器，而并不限于特定类型的存储器或存储器数目、或记忆存储在其上的介质的类型。
如果以固件和/或软件实现，则功能可作为一条或多条指令或代码存储在计算机可读介质上。示例包括编码有数据结构的计算机可读介质和编码有计算机程序的计算机可读介质。计算机可读介质包括物理计算机存储介质。存储介质可以是能被计算机存取的可用介质。作为示例而非限定，此类计算机可读介质可包括RAM、ROM、EEPROM、CD-ROM或其他光盘存储、磁盘存储或其他磁存储设备、或能被用来存储指令或数据结构形式的期望程序代码且能被计算机访问的其他介质；如本文中所使用的盘(disk)和碟(disc)包括压缩碟(CD)、激光碟、光碟、数字多用碟(DVD)、软盘和蓝光碟，其中盘常常磁性地再现数据，而碟用激光光学地再现数据。上述的组合应当也被包括在计算机可读介质的范围内。
除了存储在计算机可读介质上，指令和/或数据还可作为包括在通信装置中的传输介质上的信号来提供。例如，通信装置可包括具有指示指令和数据的信号的收发机。这些指令和数据被配置成使一个或多个处理器实现权利要求中叙述的功能。
尽管已详细描述了本公开及其优势，但是应当理解，可在本文中作出各种改变、替代和变更而不会脱离如由所附权利要求所定义的本公开的技术。例如，诸如“上方”和“下方”之类的关系术语是关于基板或电子器件使用的。当然，如果该基板或电子器件被颠倒，则上方变成下方，反之亦然。此外，如果是侧面取向的，则上方和下方可指代基板或电子器件的侧面。而且，本申请的范围并非旨在被限定于说明书中所描述的过程、机器、制造、物质组成、装置、方法和步骤的特定配置。如本领域的普通技术人员将容易从本公开领会到的，根据本公开，可以利用现存或今后开发的与本文所描述的相应配置执行基本相同的功能或实现基本相同结果的过程、机器、制造、物质组成、装置、方法或步骤。因此，所附权利要求旨在将这样的过程、机器、制造、物质组成、装置、方法或步骤包括在其范围内。
技术人员将进一步领会，结合本文的公开所描述的各种解说性逻辑框、模块、电路、和算法步骤可被实现为电子硬件、计算机软件、或两者的组合。为清楚地解说硬件与软件的这一可互换性，各种解说性组件、块、模块、电路、以及步骤在上面是以其功能性的形式作一般化描述的。此类功能性是被实现为硬件还是软件取决于具体应用和施加于整体系统的设计约束。技术人员可针对每种特定应用以不同方式来实现所描述的功能性，但此类实现决策不应被解读为致使脱离本公开的范围。
结合本文的公开所描述的各种解说性逻辑框、模块、以及电路可用设计成执行本文中描述的功能的通用处理器、数字信号处理器(DSP)、专用集成电路(ASIC)、现场可编程门阵列(FPGA)或其他可编程逻辑器件、分立的门或晶体管逻辑、分立的硬件组件、或其任何组合来实现或执行。通用处理器可以是微处理器，但在替换方案中，处理器可以是任何常规的处理器、控制器、微控制器、或状态机。处理器还可被实现为计算设备的组合(例如，DSP与微处理器的组合、多个微处理器、与DSP核心协同的一个或多个微处理器，或者任何其他此类配置)。
结合本公开所描述的方法或算法的步骤可直接在硬件中、在由处理器执行的软件模块中、或在这两者的组合中体现。软件模块可驻留在RAM、闪存、ROM、EPROM、EEPROM、寄存器、硬盘、可移动盘、CD-ROM或本领域中所知的任何其他形式的存储介质中。示例性存储介质耦合到处理器以使得该处理器能从/向该存储介质读写信息。在替换方案中，存储介质可以被整合到处理器。处理器和存储介质可驻留在ASIC中。ASIC可驻留在用户终端中。在替换方案中，处理器和存储介质可作为分立组件驻留在用户终端中。
在一个或多个示例性设计中，所描述的功能可以在硬件、软件、固件、或其任何组合中实现。如果在软件中实现，则各功能可以作为一条或多条指令或代码存储在计算机可读介质上或藉其进行传送。计算机可读介质包括计算机存储介质和通信介质两者，包括促成计算机程序从一地向另一地转移的任何介质。存储介质可以是可被通用或专用计算机访问的任何可用介质。作为示例而非限定，这样的计算机可读介质可以包括RAM、ROM、EEPROM、CD-ROM或其他光盘存储、磁盘存储或其他磁存储设备、或能被用来携带或存储指令或数据结构形式的指定程序代码手段且能被通用或专用计算机、或者通用或专用处理器访问的任何其他介质。任何连接也被正当地称为计算机可读介质。例如，如果软件是使用同轴电缆、光纤电缆、双绞线、数字订户线(DSL)、或诸如红外、无线电、以及微波之类的无线技术从web网站、服务器、或其他远程源传送而来，则该同轴电缆、光纤电缆、双绞线、DSL、或诸如红外、无线电、以及微波之类的无线技术就被包括在介质的定义之中。如本文中所使用的盘(disk)和碟(disc)包括压缩碟(CD)、激光碟、光碟、数字多用碟(DVD)和蓝光碟，其中盘(disk)往往以磁的方式再现数据而碟(disc)用激光以光学方式再现数据。上述的组合应当也被包括在计算机可读介质的范围内。
提供对本公开的先前描述是为使得本领域任何技术人员皆能够制作或使用本公开。对本公开的各种修改对本领域技术人员而言将容易是显而易见的，并且本文中所定义的普适原理可被应用到其他变型而不会脱离本公开的精神或范围。因此，本公开并非旨在被限定于本文中所描述的示例和设计，而是应被授予与本文中所公开的原理和新颖性特征相一致的最广范围。

Claims (18)

1.一种集成电路IC器件，包括：
在第一类型区域中的第一类型的第一有效晶体管，其具有在所述第一有效晶体管的有源部分中的第一类型功函数材料和沟道掺杂剂浓度，所述第一有效晶体管的有源部分包括第一单片鳍和第一鳍下，所述第一鳍下整合到基板；以及
在所述第一类型区域中的所述第一类型的第一隔离晶体管，其具有在所述第一隔离晶体管的有源部分中的第二类型功函数材料和所述沟道掺杂剂浓度，所述第一隔离晶体管的有源部分包括第二单片鳍和第二鳍下，所述第二鳍下整合到所述基板，所述第一隔离晶体管毗邻所述第一有效晶体管。
2.如权利要求1所述的集成电路IC器件，其特征在于，进一步包括：
在第二类型区域中的第二类型的第二有效晶体管，其具有所述第二类型功函数材料；以及
在所述第二类型区域中的所述第二类型的第二隔离晶体管，其具有所述第一类型功函数材料，所述第二有效晶体管毗邻所述第二隔离晶体管。
3.如权利要求1所述的集成电路IC器件，其特征在于，进一步包括在所述第一类型区域中的毗邻所述第一隔离晶体管的第三有效晶体管，所述第三有效晶体管通过所述第一隔离晶体管与所述第一有效晶体管电隔离，所述第一隔离晶体管具有比所述第一有效晶体管和所述第三有效晶体管更高的阈值电压。
4.如权利要求1所述的集成电路IC器件，其特征在于，所述第一隔离晶体管的栅极被偏置成将所述第一隔离晶体管置于截止状态。
5.如权利要求1所述的集成电路IC器件，其特征在于，所述第一类型是n型且所述第一类型区域是n型区域且所述第二类型功函数材料是p型功函数材料，并且
其中所述第一隔离晶体管在所述n型区域中被布置成具有所述p型功函数材料以提供比所述第一有效晶体管更高的阈值电压。
6.如权利要求1所述的集成电路IC器件，其特征在于，所述第一有效晶体管和所述第一隔离晶体管包括鳍式场效应晶体管FinFET且所述有源部分包括所述鳍式场效应晶体管FinFET的鳍。
7.如权利要求6所述的集成电路IC器件，其特征在于，第一有效鳍式场效应晶体管FinFET和第一隔离鳍式场效应晶体管FinFET包括掺杂鳍下部分上的有效鳍部分，所述掺杂鳍下部分掺杂有固态掺杂剂。
8.如权利要求1所述的集成电路IC器件，其特征在于，所述第一有效晶体管和所述第一隔离晶体管包括栅极全包围纳米线场效应晶体管FET。
9.如权利要求1所述的集成电路IC器件，其特征在于，所述集成电路IC器件被集成到移动电话、机顶盒、音乐播放器、视频播放器、娱乐单元、导航设备、计算机、手持式个人通信系统PCS单元、便携式数据单元、和/或固定位置数据单元中。
10.一种集成电路IC器件，包括：
在第一类型区域中的第一类型的第一有效晶体管，其具有在所述第一有效晶体管的有源部分中的第一类型功函数材料和沟道掺杂剂浓度，所述有源部分包括第一单片鳍和第一鳍下，所述第一鳍下整合到基板；以及
用于隔离所述第一有效晶体管的第一装置，所述用于隔离的第一装置毗邻所述第一有效晶体管并且包括第二单片鳍和第二鳍下，所述第二鳍下整合到所述基板。
11.如权利要求10所述的集成电路IC器件，其特征在于，进一步包括：
在第二类型区域中的第二类型的第二有效晶体管，其具有第二类型功函数材料；以及
用于隔离所述第二有效晶体管的第二装置，所述第二有效晶体管毗邻所述用于隔离的第二装置。
12.如权利要求10所述的集成电路IC器件，其特征在于，进一步包括在所述第一类型区域中的毗邻所述用于隔离的第一装置的第三有效晶体管，所述第三有效晶体管通过所述用于隔离的第一装置与所述第一有效晶体管电隔离，所述用于隔离的第一装置具有比所述第一有效晶体管和所述第三有效晶体管更高的阈值电压。
13.如权利要求10所述的集成电路IC器件，其特征在于，所述用于隔离的第一装置包括在所述第一类型区域中的所述第一类型的第一隔离晶体管，其具有在所述第一隔离晶体管的有源部分中的第二类型功函数材料和所述沟道掺杂剂浓度，并且所述第一隔离晶体管的栅极被偏置成将所述第一隔离晶体管置于截止状态。
14.如权利要求10所述的集成电路IC器件，其特征在于，所述第一类型是n型且所述第一类型区域是n型区域且第二类型功函数材料是p型功函数材料，并且
其中所述用于隔离的第一装置包括第一隔离晶体管，其在所述n型区域中被布置成具有所述p型功函数材料以提供比所述第一有效晶体管更高的阈值电压。
15.如权利要求14所述的集成电路IC器件，其特征在于，所述第一有效晶体管和所述第一隔离晶体管包括鳍式场效应晶体管FinFET且所述有源部分包括所述鳍式场效应晶体管FinFET的鳍。
16.如权利要求15所述的集成电路IC器件，其特征在于，第一有效鳍式场效应晶体管FinFET和第一隔离鳍式场效应晶体管FinFET包括所述掺杂鳍部分上的所述有效鳍部分，所述掺杂鳍部分掺杂有固态掺杂剂。
17.如权利要求10所述的集成电路IC器件，其特征在于，所述用于隔离的第一装置包括第一隔离晶体管，并且其中所述第一有效晶体管和所述第一隔离晶体管包括栅极全包围纳米线场效应晶体管FET。
18.如权利要求10所述的集成电路IC器件，其特征在于，所述集成电路IC器件被集成到移动电话、机顶盒、音乐播放器、视频播放器、娱乐单元、导航设备、计算机、手持式个人通信系统PCS单元、便携式数据单元、和/或固定位置数据单元中。
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