CN107204383B - 累崩型光检测器元件及其制作方法 - Google Patents
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Abstract
本发明公开一种累崩型光检测器元件及其制作方法。其中累崩型光检测器(avalanche photodetector,APD)元件,包含有一具有一正面与一背面的基底、至少一设置于该基底的该正面的APD结构、多个设置至于该基底的该背面的散热结构、以及多个设置于该基底的该背面的岛状反射结构。
Description
技术领域
本发明涉及一种累崩型光检测器(avalanche photo detector,以下简称为APD)元件及其制作方法,尤其是涉及一种具有散热结构(heat sink)的APD元件及其制作方法。
背景技术
APD元件为一种灵敏的半导体光感测器元件,因此常被用于诸如长程光纤通讯(long haul fiber-optic telecommunication)、激光测距仪(Laser rangefinders)、以及单一相片电平侦测及成像(single photo level detection and imaging)等需要高灵敏度的应用。现有的APD元件可至少包含硅与锗:其中锗提供了近红外线波长(波长为850m)波长上的高反应率,而硅能够在低杂讯下放大所产生的光载流子。因此,由硅与锗这两者形成的APD元件为一可侦测近红外线(near-infrared)光信号的装置,其已广泛应用于近红外线的光纤通讯中。当然,可用以形成APD元件的材料不限于硅与锗,还可包含如砷化铟镓(InGaAs)、磷砷化铟镓(InGaAsP)、磷化铟(InP)等III-V族元素及其组合。除850nm之外,APD元件可侦测的光波长也可依需要达到1310nm或1577nm。
发明内容
因此,本发明的一目的在于提供一种APD元件及其制作方法,以解决现有技术存在的问题。
为解决上述问题,本发明提供一种APD元件,该APD元件包含有一具有一正面与一背面的基底、至少一设置于该基底的该正面的APD结构、多个设置至于该基底的该背面的散热结构(heat sink)、以及多个设置于该基底的该背面的岛状反射结构。
本发明还提供一种APD元件的制作方法,该制作方法首先提供一基底,且该基底包含有一正面与一背面。接下来,于该基底的该正面形成一APD结构,随后图案化该基底的该背面,以于该基底的该背面形成多个散热结构,以及形成于该多个散热结构之间的多个凹槽。之后,形成多个岛状反射结构,且该多个岛状反射结构分别形成于该多个凹槽的底部。
根据本发明所提供的制作方法所得到的APD元件,基底的正面包含有至少一APD结构,而基底的背面则包含有反射结构与散热结构。反射结构可用以将穿透APD结构的光线反射回APD结构,故可增加APD元件整体的反应率(responsivity)以及灵敏度(sensitivity)。而散热结构则可将APD结构在光感测时产生的热有效排除,故可确保APD元件整体在运作时不致发生过热等影响元件效能的状况。
附图说明
图1至图7为本发明所提供的一APD元件的制作方法的第一较佳实施例的示意图;
图8至图11为本发明所提供的APD元件的背面的上视图;
图12为本发明所提供的APD元件的一第二较佳实施例的示意图。
主要元件符号说明
100 基底
100B 基底的背面
100F 基底的正面
102 硅基底层
104 底部氧化层
106 半导体层
108 n型掺杂区
110 半导体平台
112 n型掺杂半导体层
114 本质半导体层
116 p型掺杂半导体层
118 图案化氧化层
118O 开口
120 外延半导体层
122 非晶硅层
124 n型重掺杂区
130 累崩型光感测器结构
140 介电层
140C 开口
142 导电结构
144 抗反射层
150 散热结构
152 凹槽
160 岛状反射结构
160R 连续性反射膜
162 反射层
200 累崩型光感测器元件
具体实施方式
请参阅图1至图7,图1至图7为本发明所提供的一APD元件的制作方法的一第一较佳实施例的示意图。如图1所示,本发明所提供的APD结构的制作方法首先提供一基底100,且基底100定义有一正面100F与一背面100B。在本较佳实施例中,基底100较佳为一硅覆绝缘(silicon-on-insulator,以下简称为SOI)基底,但不限于此。一般来说,SOI基底如图1所示,由下而上可依序包含一硅基底层102、一底部氧化(bottom oxide,以下简称为BOX)层104、以及一形成于BOX层104上的半导体层106,例如一具单晶结构的硅层。此外,在本较佳实施例中,BOX层104上的半导体层106中还包含一n型掺杂区108。另外须注意的是,在半导体层106上形成有一半导体平台(mesa)110,此半导体平台由下而上可依序包含一n型掺杂半导体层112、一本质(intrinsic)半导体层114、以及一p型掺杂半导体层116。在本较佳实施例中,n型掺杂半导体层112的一掺杂浓度低于半导体层106的一掺杂浓度。此外,本质半导体层114指该半导体层为一未掺杂的半导体膜层,也就是说,本质半导体层114内并未包含任何型态的导电掺杂质(conductive dopant)。然而,熟悉该项技术的人士应知,在本发明的其他实施例中,上述半导体平台110内膜层的组合以及浓度关系可依产品需要调整,故不限于此。
请参阅图2与图3。接下来,可于基底100的正面100F形成一图案化氧化层118。如图2所示,图案化氧化层118包含一开口118O,且半导体平台110暴露于开口118O的底部。接下来,于开口118O内形成一外延半导体层120。在本较佳实施例中,外延半导体层120可通过选择性外延成长(selective epitaxial growth,以下简称为SEG)方法形成于开口118O的底部,但不限于此。是以,如图3所示,开口118O内所形成的外延半导体层120以及半导体平台110所包含的p型掺杂半导体层116、本质半导体层114与n型掺杂半导体层112构成一APD结构130。
请继续参阅图3。在利用SEG方法形成外延半导体层120并形成APD结构130之后,可同位地进行一沈积制作工艺,于基底100的正面形成一非晶硅(amorphous silicon)层122。非晶硅层122的一厚度可以是1埃(angstroms,),但不限于此。
请参阅图4。在形成非晶硅层122之后,可于基底100的正面100F形成一图案化保护层(图未示),且图案化保护层覆盖并保护半导体平台110。随后进行一蚀刻制作工艺,用以移除未被图案化保护层覆盖的非晶硅层122,而暴露出半导体层106与部分n型掺杂区108。而在蚀刻制作工艺之后,可进行一离子注入制作工艺,而于暴露出来的半导体层106内形成一n型重掺杂区124。在本较佳实施例中,n型重掺杂区124的一掺杂浓度大于n型掺杂区108的掺杂浓度,而n型掺杂区108的掺杂浓度如前所述大于半导体平台110内的n型掺杂半导体层112的掺杂浓度。请继续参阅图4。在形成n型重掺杂区之后124,可再形成一图案化保护层(图未示),且图案化保护层覆盖并保护APD结构130以及n型重掺杂区124。随后进行一蚀刻制作工艺,用以移除未被图案化保护层覆盖的半导体层106,直至暴露出半导体层106底部的BOX层104,如图4所示。
请参阅图5。接下来,于基底100的正面100F形成一介电层140。在本较佳实施例中,介电层140可以是内层介电(interlayer dielectric,ILD层,但不限于此。随后,于介电层140内形成多个开口140C,且开口140C如图5所示,暴露出n型重掺杂区124以及部分外延半导体层120上方的非晶硅层122。此外须注意的是,在形成介电层140之前,或在形成介电层140以及开口140C之后,可进行一金属硅化物制作工艺,而于n型重掺杂区124表面以及部分外延半导体层120上方的非晶硅层122表面形成金属硅化物(图未示)。
请参阅图6。随后,于开口140C内分别形成一导电结构142。如图6所示,部分导电结构140与APD结构130电连接,且部分导电结构140与n型掺杂区108内的n型重掺杂区124电连接。在本较实施例中,与APD结构130电连接的导电结构140还与一操作电压VDD电连接,而与n型重掺杂区124电连接的导电结构142则还与一接地电压VSS电连接。在本较佳实施例中,导电结构142可以是一内连线结构(interconnection)的第一层金属层,但不限于此。在形成导电结构140之后,于基底100的正面100F形成一覆盖APD结构130以及基底100的正面100F的抗反射(anti-reflection)层144。
请参阅图7。在完成上述APD结构130、介电层140与导电结构142等组成元件的制作后。可于基底100的正面100F形成一保护层(图未示)以及承载基板(图未示)。随后翻转基底100,而对基底100的背面100B进行图案化。如图7所示,本较佳实施例图案化基底100的背面100B,以于基底100的背面100B形成多个散热结构150,以及形成于散热结构150之间的多个凹槽152。另外须注意的是,在本较佳实施例中,图案化制作工艺可由SOI基底100的背面100B向正面100F方向蚀刻SOI基底100的硅基底层102,而使得BOX层104暴露于凹槽152的底部。然而,熟悉该项技术的人士应知,在本发明的其他实施例中,可调整图案化制作工艺的参数,使得硅基底层102未被完全移除,而暴露于凹槽152的底部。
请继续参阅图7。在形成散热结构150以及散热结构150之间的凹槽152之后,还可于凹槽152的底部分别形成一金属层,且金属层作为APD结构130的反射结构。如图7所示,在本较佳实施例中,金属层为设置于凹槽152内的岛状反射结构160,且散热结构150的一厚度大于岛状反射结构160的一厚度,因此岛状反射结构160通过散热结构150彼此分离。简单地说,本较佳实施例所提供的散热结构150包含半导体材料,且该半导体材料与至少部分基底100相同,而反射结构160则包含金属材料。如前所述,由于散热结构150通过图案化基底100的硅基底层102所得,故散热结构150的材料即为基底100的硅基底层102的材料。至此,完成一包含有APD结构130、反射结构160与散热结构150的APD元件200,如图7所示。
接下来请参阅图8至图11,图8至图11为本发明所提供的APD结构200的背面的上视图,图7则可以是图8至图11中沿A-A’切线所得的剖视图。更重要的是,图8至图11分别绘示了本发明所提供的散热结构150与岛状反射结构160不同的实施型态。如8图所示,在本发明的一实施例中,至少一岛状反射结构160设置于APD元件200的中心点,且如图7所示,与APD结构130对齐,而散热结构150则环绕此一中心岛状反射结构160,并呈一向外放射图案,其他的岛状反射结构160则如图8所示分别由此一具有向外放射图案的散热结构150分隔。如图9所示,在本发明的另一实施例中,散热结构150包含有一同心圆图案,而岛状反射结构160则分别设置于同心圆图案中,并分别由散热结构150分隔。在该实施例中,较佳有至少一岛状反射结构160与APD结构130对齐,如图7所示。如图10所示,在本发明的另一实施例中,散热结构150包含有一网孔(mesh)图案,而岛状反射结构160则分别设置于网眼之中,并分别由散热结构150分隔。在该实施例中,较佳有至少一岛状反射结构160与APD结构130对齐,如图7所示。如图11所示,在本发明的又一实施例中,散热结构150包含有一放射状图案图案,而岛状反射结构160则分别由散热结构150分隔。
请重新参阅图7。根据本发明所提供的APD元件及其制作方法,主要是在基底100的正面100F完成APD结构130的制作后,于基底100的背面100B形成散热结构150以及岛状反射结构160。如图7所示,岛状反射结构160较佳对应于APD结构130。因此,穿透APD结构130的光线可通过岛状反射结构160返回APD结构130,故可增加APD元件200整体的反应率与灵敏度。举例来说,APD元件200的灵敏度可增加2dBm,但不限于此。更重要的是,岛状反射结构160虽然增加了光的反射,但其阻挡了APD结构130与空气的接触,故影响了操作中产生的热能的传递。而本较佳实施例则通过散热结构150的设置,增加了散热路径B的数量以及与空气的接触面积,故可确保APD结构130在操作中不致产生过热的问题,更确保了APD元件200的整体效能。
另外请参阅图12,图12为本发明所提供的APD元件的一第二较佳实施例的示意图。首先须注意的是,第二较佳实施例与第一较佳实施例中,相同的组成元件具有相同的符号说明,且可包含相同的材料选择,并通过相同的方法形成,故该多个细节于此皆不再赘述。第二较佳实施例与第一较佳实施例不同之处在于,在形成散热结构150以及凹槽152之后,不但于凹槽152的底部形成岛状反射结构160,本较佳实施例更是于基底100的背面100B形成多个反射层160,且反射层160如图12所示,覆盖凹槽152的侧壁与散热结构150的顶部表面。此外,反射层162还接触岛状反射结构160,以于基底100的背面100B形成一连续性反射膜160R。
在本较佳实施例中,由岛状反射结构160与反射层162构成的连续性反射膜160R可使得穿透APD结构130的光线返回APD结构130,故可增加APD元件200整体的反应率与灵敏度。而本较佳实施例则通过散热结构150的设置,增加了散热的路径数量,故可确保APD结构130在操作中不致产生过热的问题,更确保了APD元件200的效能。
综上所述,根据本发明所提供的制作方法所得到的APD元件,基底的正面包含有至少一APD结构,而基底的背面包含有多个反射结构与多个散热结构。本发明所提供的该多个反射结构可用以将穿透APD元件的光线反射回APD元件,故可增加APD元件的反应率以及灵敏度。而本发明所提供的该多个散热结构则可将APD元件在光感测时产生的热有效排除,故可确保APD元件在运作时不致发生过热等影响元件效能的状况。
以上所述仅为本发明的较佳实施例,凡依本发明权利要求所做的均等变化与修饰,皆应属本发明的涵盖范围。
Claims (20)
1.一种累崩型光感测器元件,包含有:
基底,包含有一正面与一背面;
至少一累崩型光感测器结构,设置于该基底的该正面;
多个散热结构(heat sink),设置至于该基底的该背面;以及
多个岛状反射结构,设置于该基底的该背面。
2.如权利要求1所述的累崩型光感测器元件,其中该多个散热结构包含一半导体材料,而该多个岛状反射结构包含有金属材料。
3.如权利要求2所述的累崩型光感测器元件,其中该半导体材料与至少部分该基底相同。
4.如权利要求1所述的累崩型光感测器元件,其中该多个散热结构包含有同心圆图案、放射状图案、或网孔(mesh)图案。
5.如权利要求1所述的累崩型光感测器元件,其中该多个岛状反射结构通过该多个散热结构彼此分离。
6.如权利要求1所述的累崩型光感测器元件,其中该多个散热结构的一厚度大于该多个岛状反射结构的一厚度。
7.如权利要求1所述的累崩型光感测器元件,还包含多个凹槽,定义于该多个散热结构之间。
8.如权利要求7所述的累崩型光感测器元件,其中该多个岛状反射结构分别设置于该多个凹槽的底部。
9.如权利要求8所述的累崩型光感测器元件,还包含多个反射层,形成于该多个凹槽的侧壁与该多个散热结构的顶部表面。
10.如权利要求9所述的累崩型光感测器元件,其中该多个反射层接触该多个岛状反射结构,以形成一连续性反射膜。
11.如权利要求1所述的累崩型光感测器元件,其中该累崩型光感测器结构包含有至少一n型掺杂半导体层、一本质(intrinsic)半导体层、一p型掺杂半导体层、以及一外延半导体层。
12.一种累崩型光感测器元件的制作方法,包含有:
提供一基底,该基底包含有一正面与一背面;
于该基底的该正面形成一累崩型光感测器结构;
图案化该基底的该背面,以于该基底的该背面形成多个散热结构,以及形成于该多个散热结构之间的多个凹槽;以及
形成多个岛状反射结构,且该多个岛状反射结构分别形成于该多个凹槽的底部。
13.如权利要求12所述的累崩型光感测器元件的制作方法,其中形成该累崩型光感测器结构的步骤还包含:
于该基底的该正面形成一半导体平台(mesa);以及
于该半导体平台上形成一外延半导体层。
14.如权利要求13所述的累崩型光感测器元件的制作方法,其中该半导体平台包含有至少一n型掺杂半导体层、一本质半导体层、以及一p型掺杂半导体层。
15.如权利要求12所述的累崩型光感测器元件的制作方法,还包含以下步骤,进行于形成该累崩型光感测器结构之后:
于该基底的该正面形成一覆盖该累崩型光感测器结构的介电层;
于该介电层内形成多个导电结构,且该多个导电结构与该累崩型光感测器结构电连接;以及
于该基底的该正面形成一抗反射(anti-reflection)层。
16.如权利要求12所述的累崩型光感测器元件的制作方法,其中该多个散热结构包含一半导体材料,而该多个岛状反射结构包含有金属材料。
17.如权利要求12所述的累崩型光感测器元件的制作方法,其中该多个散热结构包含有同心圆图案、放射状图案、或网孔图案。
18.如权利要求12所述的累崩型光感测器元件的制作方法,其中该多个岛状反射结构通过该多个散热结构彼此分离。
19.如权利要求12所述的累崩型光感测器元件的制作方法,还包含于该基底的该背面形成多个反射层,且该多个反射层覆盖该多个凹槽的侧壁与该多个散热结构的顶部表面。
20.如权利要求19所述的累崩型光感测器元件的制作方法,其中该多个反射层接触该多个岛状反射结构,以于该基底的该背面形成一连续性反射膜。
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