CN107204299B - The manufacturing method and semiconductor device of semiconductor device - Google Patents
The manufacturing method and semiconductor device of semiconductor device Download PDFInfo
- Publication number
- CN107204299B CN107204299B CN201710133174.9A CN201710133174A CN107204299B CN 107204299 B CN107204299 B CN 107204299B CN 201710133174 A CN201710133174 A CN 201710133174A CN 107204299 B CN107204299 B CN 107204299B
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- Prior art keywords
- lead
- wiring part
- recess portion
- semiconductor device
- electronic pads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Embodiments of the present invention provide the manufacturing method and semiconductor device of a kind of semiconductor device of useless deformation for being able to suppress lead.The manufacturing method of the semiconductor device of embodiment has following steps: for lead frame, the 1st lead is pressed on one side, it is on one side that the another side of opposite side will push against component and be pressed against wiring part and make its deformation with the one side for forming the 1st recess portion from lead frame, the end on the extending direction of the 1st lead and the interconnecting piece of wiring part are sheared using the 1st recess portion as basic point, and separate wiring part from end, the lead frame includes the 1st lead, the 2nd lead and the wiring part that will be connected between the end on the extending direction of the 2nd lead and the 1st lead；And the 1st lead extending direction on end and wiring part between interconnecting piece the end inside than width direction region have the 1st recess portion.
Description
[related application]
Present application is enjoyed based on Japanese patent application case 2016-53321 (applying date: on March 17th, 2016)
The priority of application case.Present application all the elements comprising basic application case by referring to the basis application case.
Technical field
Embodiments of the present invention are related to the manufacturing method and semiconductor device of a kind of semiconductor device.
Background technique
In the semiconductor device for having the lead and semiconductor chip comprising outer lead and lead, closing line is utilized
And it will be electrically connected between the electronic pads of semiconductor chip and lead.Therefore, the distance between electronic pads and outer lead are longer, then
It is more necessary to extend to lead near electronic pads from outer lead longlyer.
Longer lead is easily deformed in the manufacturing process of semiconductor device.If lead deforms, such as
There are semiconductor chips to be easy the case where removing from lead, or generation connects between closing line and lead in routing engagement
Connect bad situation.
Summary of the invention
Embodiments of the present invention provide a kind of manufacturer of the semiconductor device of useless deformation for being able to suppress lead
Method and semiconductor device.
The manufacturing method of the semiconductor device of embodiment has following steps: for lead frame, pressing in the 1st on one side
Lead is that the another side of opposite side will push against component and be pressed against and matches with the one side for forming the 1st recess portion from lead frame on one side
Line portion and make its deformation, using the 1st recess portion as basic point shear the 1st lead extending direction on end and wiring part connection
Portion, and separate wiring part from end, the lead frame includes: the 1st lead, comprising the 1st outer lead and from the 1st outer lead
The 1st lead extended；2nd lead includes the 2nd outer lead and the 2nd lead extended from the 2nd outer lead；Wiring part, by
It is connected between end on the extending direction of 2 leads and the 1st lead；And support portion, it is connected to outside the 1st outer lead and the 2nd
Lead；And the 1st lead extending direction on end and wiring part between interconnecting piece it is interior in the end than width direction
The region of side has the 1st recess portion；Semiconductor chip comprising the 1st electronic pads and the 2nd electronic pads is equipped on via adhesion coating
On the another side of lead frame；Form the 1st closing line that is electrically connected the 1st electronic pads with the 1st lead and by the 2nd electronic pads and
2nd closing line of the 2nd lead electrical connection；It is formed the 1st lead, the 2nd lead, wiring part, semiconductor chip, the 1st engagement
Line and the sealing resin layer of the 2nd engagement linear sealing；Interconnecting piece between support portion and the 1st outer lead and the 2nd outer lead is cut
It is disconnected.
Detailed description of the invention
Fig. 1 is the schematic top plan view for indicating the structure example of lead frame.
Fig. 2 is the schematic diagram for indicating a part of lead frame.
Fig. 3 is the schematic cross-sectional view for being illustrated to lead frame procedure of processing.
Fig. 4 is the schematic cross-sectional view for being illustrated to lead frame procedure of processing.
Fig. 5 is the schematic diagram for indicating a part of the lead frame after lead frame procedure of processing.
Fig. 6 is the schematic top plan view for indicating the structure example of semiconductor device.
Fig. 7 is the schematic top plan view for indicating a part of semiconductor device.
Fig. 8 is the schematic cross-sectional view for indicating the structure example of a part of semiconductor device.
Specific embodiment
Hereinafter, being illustrated referring to attached drawing to embodiment.The thickness and plane meter for each component recorded in attached drawing
The ratio etc. of the thickness of very little relationship, each component there is a situation where different from material object.In addition, in embodiments, to reality
Identical constituent element marks identical symbol and suitably omits the description in matter.
As manufacturer's rule of semiconductor device, referring to figs. 1 to Fig. 8, to as TSOP (Thin Small
OutlinePackage, Outline Package) manufacturer's rule of semiconductor device be illustrated.The system of semiconductor device
The method example of making has lead frame preparation process, lead frame procedure of processing, chip carrying step, routing engagement step, resin
Sealing step, exterior coating step and finishing molding (T/F) step.The sequence of each step is not limited to described enumerate sequentially.
Fig. 1 is the schematic top plan view for indicating the structure example of lead frame.Fig. 1 shows include X-axis and Y-axis orthogonal to X-axis
Lead frame X-Y plane.
In lead frame preparation process, as shown in Figure 1, preparing comprising more leads 11 and supporting the branch of more leads 11
The lead frame 1 of support part 12.Lead frame 1 is the metal plate for carrying the elements such as semiconductor chip.As lead frame 1, such as
The lead frame using the alloy of the iron such as copper, copper alloy or 42 alloys and nickel etc. can be enumerated.Lead frame 1 utilizes Punching Technology
Deng and through being pre-machined.
The lead that more leads 11 respectively contain outer lead and extend from the outer lead.Lead is walked in resin seal
The part supported after rapid by sealing resin layer.In lead, in the region of the progress routing engagement of the upper surface side of lead frame 1
The coating such as silver are set.Outer lead is after resin-sealing step from sealing resin layer part outstanding.More leads 11 it is outer
Lead is respectively for example disposed in parallel in X-Y plane along Y-axis.
As more leads 11, such as input/output signal (IO), data strobe signal (DQS), lead can be enumerated and enabled
Signal (RE), await orders/busy signal (RB), chip enable signal (CE), address latch enable signal (ALE), the enabled letter of write-in
Signals lead or the power supply (VCC), power supply (VPP), power supply such as number (WE), write protect signal (RP) or zero quotient's signal (ZQ)
(VSS) the power supplys lead etc. such as.As the signal, it is possible to use differential wave.At least one of more leads 11 can also be
The lead of not connected (NC).Putting in order for various leads is set according to the specification of semiconductor device or standard etc..
Support portion 12 is arranged in a manner of surrounding more leads 11.The one of the outer lead of support portion 12 and more leads 11
The respective connection at end.In addition, support portion 12 also can support drawing for another semiconductor device in addition to supporting more leads 11
Line.
Fig. 2 is a part (region of the lead frame shown in FIG. 1 when indicating from the lower face side of lead frame 1
100 a part) schematic diagram.In Fig. 2, the lower surface of lead frame 1 is illustrated in upper surface side, by lead frame 1
Upper surface figure is shown in lower face side.Z axis in Fig. 2 is orthogonal with X-axis and Y-axis, is equivalent to the thickness direction of lead frame 1.In Fig. 2
In, as the lead of more leads 11, illustrate lead 111, lead 112, lead 113 and lead 114.
Lead 111 and lead 112 are, for example, input/output signal (IO) or data strobe signal signal (DQS) with drawing
Line.Lead 113 and lead 114 are, for example, that power supply (VSS) uses lead.At this moment, by lead 111 and lead 112
Between be arranged lead 113 and be able to suppress the interference between the signal of lead 111 and the signal of lead 112.
Lead frame shown in FIG. 1 have by the extending direction of lead 111 to lead 113 end and lead
The wiring part 115 of 114 a part connection.That is, lead 111 to lead 113 be using support portion 12 and wiring part 115 and
It is fixed.As long as the shape that lead 111 to lead 113 can be connect by the shape of wiring part 115 with lead 114 is then simultaneously
It is not particularly limited.In addition, wiring part 115 can also be considered as to a part of lead 114.
Lead 111 to lead 114 and wiring part 115 has the upper surface side that lead frame 1 is arranged in (under Fig. 2
Surface side) coating 20.Coating 20 is, for example, to be handled and formed by using the plating of the plating material comprising silver etc..In order to
Following routings ensure that lead 111 to the bond strength between lead 114 and closing line, or makes and semiconductor chip when engaging
Connection resistance become smaller, coating 20 be arranged in carry out routing engagement region.
The interconnecting piece of end and wiring part 115 on lead 111 to the extending direction (Y direction) of lead 113 exists
The upper surface side of lead frame 1 has recess portion (groove) 116a.Recess portion 116a setting is respective to lead 113 in lead 111
Ratio width direction (X-direction) end inside region.
The interconnecting piece of lead 114 and wiring part 115 has recess portion (groove) 116b in the upper surface side of lead frame 1.
Recess portion 116b shown in Fig. 2 extends to the other end from the one end of lead 114 in the direction of the width, and but not limited to this,
It can be likewise arranged on recess portion 116a interior than the end of the interconnecting piece of lead 114 and wiring part 115 in the direction of the width
The region of side.In addition, recess portion 116b is settable multiple.
In Fig. 2, it can also be other that recess portion 116a and recess portion 116b have V-shape on the section comprising Y-Z plane
Shape.In addition, the depth on the thickness direction of the lead frame 1 of recess portion 116b is preferably smaller than the lead frame 1 of recess portion 116a
Depth on thickness direction.
Recess portion 116a and recess portion 116b is, for example, to be formed by coining processing, laser processing or blade processing etc..Recess portion
116a and recess portion 116b are preferably formed before blanking process.If forming recess portion 116a and recess portion after Punching Technology
Then there is the case where lead frame 1 generates useless deformation in 116b.
The opposite side in the lower face side of lead frame 1, the i.e. face with coating 20 is arranged in recess portion 116a and recess portion 116b
Face.Coating 20 is formed after forming recess portion 116a and recess portion 116b.Therefore, if with recess portion 116a and recess portion 116b
Face form coating 20, then there is plating material and accumulated in recess portion 116a and recess portion 116b, make reliability because electric field collection is medium
The case where reduction.
Fig. 3 and Fig. 4 is the schematic cross-sectional view for being illustrated to lead frame procedure of processing.Fig. 3 and Fig. 4 indicates lead
The section Y-Z comprising Y-axis and Z axis of frame 1.In Fig. 3 and Fig. 4, as an example, diagram includes the section of lead 113.
In lead frame procedure of processing, on the platform 51 comprising recess portion 51a, so that at recess portion 116a and recess portion 116b
Mode in downside (51 side of platform) loads lead frame 1, and the both ends of wiring part 115 are pressed using pressing component 52.At this moment, make
Wiring part 115 is Chong Die with recess portion 51a.
Secondly, declining push part 53 to 51 side of platform along Z axis, being formed from lead frame 1 of component 53 will push against
The another side of the opposite side of the one side of recess portion 116a and recess portion 116b is pressed against wiring part 115 and makes at least the one of wiring part 115
Part deforms, and the end on the extending direction of lead 113 and the connection between wiring part 115 are sheared using recess portion 116a as basic point
Portion.Part with recess portion 116a is easier to be sheared than other regions.In addition, since recess portion 116a is arranged than lead
113 end inside in the direction of the width, so extending to the end in the width direction of lead 113 with recess portion 116a
Situation is compared, and the flash generated by shearing is inhibited.
Wiring part 115 from the end on the extending direction of lead 113 in a manner of separating recess portion 116b as basic point
Bending.Part with recess portion 116b is easily bent than other regions.Therefore, it is able to suppress useless deformation.
Fig. 5 is the schematic diagram for indicating the structure example in the deformed region 100 of slave upper surface side observation of lead frame 1.
In Fig. 5, the upper surface figure of lead frame 1 is shown in upper surface side, the lower surface of lead frame 1 is illustrated in lower face side.
Wiring part 115 after shearing interconnecting piece includes: the 1st end is connected to lead 114；And the 2nd end, from X-Y
It is adjacent with the end on the extending direction of lead 111 to lead 113 when the vertical direction of plane (Z-direction) is observed.The
2 ends are to draw along the section comprising thickness direction of lead 114 with interior when from the direction vertical with the section Y-Z
The mode isolated to lead 113 of line 111 is bent using recess portion 116b as basic point to prescribed direction.
2nd end of end and wiring part 115 on lead 111 to the extending direction of lead 113 is each by cutting
It cuts recess portion 116a and there is recess portion 117 in the region of the end inside than width direction.The shape of deformed wiring part 115
It is not particularly limited, it can also be as shown in figure 5, wiring part 115 includes parallel with the extending direction of lead 111 to lead 113
Region.By above step, it is separated from each other a part of lead 111 to a part of lead 114.Similarly, make
A part of the lead of other connections is separated from each other also by the step.
It is thinning to the interconnecting piece between lead 113 and wiring part 115 by making lead 111, and can make shearing must
The loading needed becomes smaller.It is used as push part 53 as a result, semiconductor chip when institute can be carried using being arranged in chip carrying step
One of multiple engaging heads of the chip bonding device used.
In order to keep lead 111 electrically separated to lead 114, consideration removes the one of the interconnecting piece using Punching Technology
Partial method.In the case where removing a part of the interconnecting piece using Punching Technology, lead 111 to lead
Shearing position necessary to one in 113 is two positions or more.Therefore, loading necessary to being punched is greater than the interconnecting piece
Shearing necessary to loading.So in order to be punched out processing, it is necessary to be arranged different from the mechanism for shearing the interconnecting piece
, dipper crowding gear that higher loading can be applied.Therefore, the composition of processing unit (plant) becomes complicated.In addition, being punched out processing
When, chip (part being removed) can be generated when a part to lead frame is punched out.The chip of lead can become system
The pollution sources of environment are made, and need to be used to be discharged the mechanism of the chip of lead, therefore preferably do not generate chip.
It is that lead frame is transported to chip after processing to connect using Punching Technology to process lead frame
It attaches together and sets and carry semiconductor chip, because hot lead is easy to deform in conveying.Therefore, it is necessary to which consolidating for fixed more leads is arranged
Determine band.Since fixing belt is easy to absorb moisture, so being easy to shell from the resin of lead or the sealing semiconductor chips of subsequent setting
From.In addition, lead frame substantially thickens if having fixing belt.Therefore, the lead frame number that case can accommodate
It reduces, so conveying cost increases.In turn, fixing belt is easy to happen the migration of dendritic crystalline.In the presence of in case of migrating, then can draw
Play the situation of short circuit between lead etc..
In view of this, using chip bonding device shear the interconnecting piece and make each lead a part separation
In the case of, semiconductor chip can be carried using identical chip bonding device after lead frame procedure of processing.Therefore, can
The conveying of lead frame is set to tail off.Even if being not provided with the useless deformation that fixing belt is also able to suppress lead as a result,.In addition, energy
Fee of material and the processing charges of fixing belt are cut down, enough so as to cut down manufacturing cost.In turn, made since wiring part can be retained
A part separation of each lead, therefore the chip of lead can be made to tail off compared with Punching Technology.
Fig. 6 is the structure example for indicating to be able to use the semiconductor device of manufacturer's rule manufacture of the semiconductor device
Schematic top plan view.The X-Y plane of Fig. 6 expression semiconductor device.Fig. 7 is Fig. 6 institute indicated from the upper surface side of lead 11
The schematic top plan view of a part (a part in region 101) of the semiconductor device shown.Fig. 8 is semiconductor device shown in fig. 6
A part (a part in region 101) schematic cross-sectional view.Fig. 8 shows the sections comprising lead 113 as an example.This
Outside, in Fig. 7 and Fig. 8, for convenient, perspective map shows the inside of sealing resin layer 4.For the portion common with Fig. 1 to Fig. 5
Divide the explanation of appropriate reference Fig. 1 to Fig. 5.
In chip carrying step, carries on the lead of lead 111 to the more leads 11 such as lead 114 and partly lead
Body chip 2.As shown in fig. 7, semiconductor chip 2 has the multiple electrode pads 21 comprising electronic pads 211 to electronic pads 215.It is multiple
Electronic pads 21 expose on the surface of semiconductor chip 2.Multiple electrode pads 21 can also be along the setting on one side of semiconductor chip 2.Pass through
Along the multiple electrode pads of setting on one side 21 of semiconductor chip 2, and chip size can be made to become smaller.As semiconductor chip 2, such as
Semiconductor chip used in the memory components or Memory Controller etc. such as NAND (Not AND, with non-) type flash memory can be enumerated.
Semiconductor chip 2 is end and wiring part on the extending direction using such as lead 111 to lead 113
Chip bonding device used in the shearing of interconnecting piece between 115 and carry.
Semiconductor chip 2 be using in multiple engaging heads different from push part 53 another and be equipped on lead
111 on lead 114.Semiconductor chip 2 is organic via crystal grain attachment film (die attach film) etc. with insulating properties
Adhesion coating 6 and be equipped on lead 111 and form recess portion 116a and recessed into the lead of the more leads 11 such as lead 114
The another side of the opposite side of the one side of portion 116b.At this moment, the lead of more leads 11 is adhered to organic adhesion coating 6.As a result, by
In the lead for securing more leads 11, so the useless deformation of lead is able to suppress in the step of behind.
Semiconductor chip 2 is preferably after by lead 111 to the interconnecting piece shearing between lead 113 and wiring part 115
It carries.If shearing the interconnecting piece after carrying semiconductor chip, there is the case where damage is caused to semiconductor chip.Example
Lead frame 1 is such as being configured into (loading) after chip bonding device, is shearing interconnecting piece.Thereafter, it is not gone from chip bonding device
Except (unloading) lead frame 1, and following semiconductor chips 2 are equipped on lead frame 1.After carrying semiconductor chip 2, by lead
Frame 1 removes (unloading) from chip bonding device, executes subsequent step, for example following routing engagement steps.
In routing engagement step, the more piece-root grafting zygonemas 3 for being electrically connected multiple electrode pads 21 with more leads 11 are formed.?
In Fig. 7, illustrate the closing line 31 that lead 111 be electrically connected with electronic pads 211 via coating 20, by lead 112 with it is electric
Lead 113 is electrically connected with electronic pads 213 via coating 20 by closing line 32 that polar cushion 212 is electrically connected via coating 20
Closing line 33, the closing line 34 that is electrically connected lead 114 and electronic pads 214 via coating 20 and by lead 114 with
The closing line 35 that electronic pads 215 are electrically connected via coating 20.
As closing line 3, such as gold thread, silver wire, copper wire can be enumerated etc..It the surface of copper wire can be coating using palladium film.Engagement
Line 3 is electrically connected to lead and electronic pads by routing engagement.
In resin-sealing step, formation is led by the lead of lead 111 to the more leads 11 such as lead 114, partly
The sealing resin layer 4 that body chip 2 and closing line 31 are sealed to more piece-root grafting zygonemas 3 such as closing line 35.Sealing resin layer 4 is to cover
The mode of the upper surface and the lower surface of the lead of Gai Duogen lead is arranged.In addition, as shown in figure 8, sealing resin layer 4 is also filled
In the end on the extending direction of lead 111 to lead 113 and between wiring part 115.
Sealing resin layer 4 contains SiO2Equal inorganic fills material.In addition, inorganic fill material, which removes, includes SiO2In addition, also may include
Such as aluminium hydroxide, calcium carbonate, aluminium oxide, boron nitride, titanium oxide or barium titanate etc..Inorganic fill material is for example, granular, has
Adjust the viscosity of sealing resin layer 4 or the function of hardness etc..The content of inorganic fill material in sealing resin layer 4 is, for example, 60%
Above and 90% or less.As sealing resin layer 4, for example, can be used inorganic fill material and insulating properties organic resin material it is mixed
Close object.As organic resin material, such as epoxy resin can be enumerated.
As the formation method of sealing resin layer 4, such as the mixture using inorganic fill material and organic resin etc. can be enumerated
Metaideophone forming process, compression forming method, injection molding method, sheet material forming method or resin drop-coating etc..
In coating step, plating processing is implemented to the surface of more leads 11.Such as use the welding material comprising tin etc.
Expect and carries out the plating processing such as being electroplated.By implementing plating processing, and it is able to suppress the oxidation of such as more leads 11.
Finishing molding (T/F) step includes the interconnecting piece between more leads 11 of cutting and support portion 12 and cuts out semiconductor
The step of device 10 (pre-shaping step) and deform the outer lead of more leads 11 according to the final shape of semiconductor device 10
The step of (forming step).
More than utilization step and semiconductor device 10 can be manufactured.As shown in Figure 6 to 8, semiconductor device 10 has:
More leads 11, the lead for separately including outer lead and extending from outer lead；Semiconductor chip 2, via organic adhesion coating 6
Be equipped on more leads 11 (such as lead 114 with curved prescribed direction be opposite side face at least part it
On), and there are multiple electrode pads 21；Multiple electrode pads 21 are connect by more piece-root grafting zygonemas 3 with more leads 11；And sealing resin
Layer 4, the lead of more leads 11, semiconductor chip 2 and more piece-root grafting zygonemas 3 are sealed.In addition, lead 111 is to lead
2nd end of end and the wiring part 115 adjacent with the end on 113 extending direction is respectively contained as clipped recessed
The recess portion 117 of a part of portion 116a.In addition, semiconductor chip 2 can also be equipped on semiconductor chip 2 shown in Fig. 8 with take
Section is the face of more leads 11 of opposite side.In addition, Fig. 6 is TSOP to semiconductor device 10 shown in Fig. 8, there can also be it
His packaging structure.
The embodiment is proposed as example, is not intended to limit the range of invention.These novel embodiment party
Formula can be implemented with various other ways, without departing from the spirit of the invention, can carry out various omissions, displacement, change.This
A little embodiments and its variation are included in the range or purport of invention, and be included in invention documented by claims and
In its equivalency range.
[explanation of symbol]
1 lead frame
2 semiconductor chips
3 closing lines
4 sealing resin layers
6 organic adhesion coatings
10 semiconductor devices
11 leads
12 support portions
20 coating
21 electronic pads
31~35 closing lines
51 platforms
51a recess portion
52 pressing components
53 push part
100 regions
101 regions
111~114 leads
115 wiring parts
116a recess portion
116b recess portion
211~215 electronic pads
Claims (5)
1. a kind of manufacturing method of semiconductor device, it is characterised in that have following steps: for lead frame, pressing on one side
1 lead will push against component pressure with the one side for forming the 1st recess portion from the lead frame on one side for the another side of opposite side
Arrive to wiring part and make its deformation, sheared using the 1st recess portion as basic point end on the extending direction of the 1st lead with
The interconnecting piece of the wiring part, and separate the wiring part from the end, the lead frame includes: the 1st lead, packet
Containing the 1st outer lead and the 1st lead extended from the 1st outer lead；2nd lead, comprising the 2nd outer lead and from described
The 2nd lead that 2nd outer lead extends；The wiring part, by the extending direction of the 2nd lead and the 1st lead
On end between connect；And support portion, it is connected to the 1st outer lead and the 2nd outer lead；And the 1st lead
Extending direction on end and the wiring part between interconnecting piece have in the region of the end inside than width direction
1st recess portion；
Semiconductor chip comprising the 1st electronic pads and the 2nd electronic pads is equipped on to the institute of the lead frame via adhesion coating
It states on another side；
Formed the 1st closing line that is electrically connected the 1st electronic pads with the 1st lead and by the 2nd electronic pads with it is described
2nd closing line of the 2nd lead electrical connection；
It is formed the 1st lead, the 2nd lead, the wiring part, the semiconductor chip, the 1st engagement
Line and the sealing resin layer of the 2nd engagement linear sealing；
By the interconnecting piece cutting between the support portion and the 1st outer lead and the 2nd outer lead.
2. the manufacturing method of semiconductor device according to claim 1, it is characterised in that: the push part is that setting exists
By the semiconductor-chip-mounting in one of multiple engaging heads of the chip bonding device on the lead frame.
3. the manufacturing method of semiconductor device according to claim 1 or 2, it is characterised in that: the 2nd lead and institute
The second recesses that there is the interconnecting piece between wiring part depth to be less than the 1st recess portion are stated, and
In the separating step, the wiring part is to prolong the second recesses with the 1st lead as basic point
The mode for stretching the end separation on direction is bent.
4. the manufacturing method of semiconductor device according to claim 3, it is characterised in that:
1st lead includes the 1st coating that another surface side is arranged in,
2nd lead includes the 2nd coating that another surface side is arranged in,
The second recesses are arranged in a surface side,
1st closing line is electrically connected to the 1st lead via the 1st coating, and
2nd closing line is electrically connected to the 2nd lead via the 2nd coating.
5. a kind of semiconductor device, characterized by comprising:
1st lead includes the 1st outer lead and the 1st lead extended from the 1st outer lead；
2nd lead includes the 2nd outer lead and the 2nd lead extended from the 2nd outer lead；
Wiring part, the extension side comprising being connected to the 1st end of a part of the 2nd lead and with the 1st lead
The 2nd adjacent end of upward end, and the 2nd end is on the section comprising thickness direction of the 2nd lead
The mode separated with the end on the extending direction of the 1st lead is bent to prescribed direction；
Semiconductor chip has the 1st electronic pads and the 2nd electronic pads, and is equipped on the described 1st and the described 2nd via adhesion coating
On at least part with the face that the prescribed direction is opposite side of at least one of lead；
1st closing line will be electrically connected between the 1st lead and the 1st electronic pads；
2nd closing line will be electrically connected between the 2nd lead and the 2nd electronic pads；And
Sealing resin layer, by the 1st lead, the 2nd lead, the wiring part, the semiconductor chip, described
1 closing line and the 2nd engagement linear sealing；And
Each comfortable end than width direction in 2nd end of end and the wiring part on the extending direction of the 1st lead
The region of portion inside has recess portion.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2016053321A JP2017168703A (en) | 2016-03-17 | 2016-03-17 | Manufacturing method of semiconductor device and semiconductor device |
| JP2016-053321 | 2016-03-17 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107204299A CN107204299A (en) | 2017-09-26 |
| CN107204299B true CN107204299B (en) | 2019-10-25 |
Family
ID=59904888
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710133174.9A Active CN107204299B (en) | 2016-03-17 | 2017-03-08 | The manufacturing method and semiconductor device of semiconductor device |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP2017168703A (en) |
| CN (1) | CN107204299B (en) |
| TW (1) | TWI646608B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109841590A (en) * | 2017-11-28 | 2019-06-04 | 恩智浦美国有限公司 | Lead frame for the IC apparatus with J lead and gull wing lead |
| CN109904136A (en) * | 2017-12-07 | 2019-06-18 | 恩智浦美国有限公司 | Lead frame for the IC apparatus with J lead and gull wing lead |
| US10566713B2 (en) * | 2018-01-09 | 2020-02-18 | Semiconductor Components Industries, Llc | Press-fit power module and related methods |
| CN110707063A (en) * | 2018-07-10 | 2020-01-17 | 恩智浦美国有限公司 | Lead frame with bendable leads |
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- 2017-03-08 CN CN201710133174.9A patent/CN107204299B/en active Active
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| US6867072B1 (en) * | 2004-01-07 | 2005-03-15 | Freescale Semiconductor, Inc. | Flipchip QFN package and method therefor |
| CN201392831Y (en) * | 2009-04-03 | 2010-01-27 | 宁波康强电子股份有限公司 | Copper strip for manufacturing lead wire frames |
| CN201523004U (en) * | 2009-10-11 | 2010-07-07 | 天水华天科技股份有限公司 | Small carrier four-surfaced flat packaging part without pins |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201810461A (en) | 2018-03-16 |
| CN107204299A (en) | 2017-09-26 |
| JP2017168703A (en) | 2017-09-21 |
| TWI646608B (en) | 2019-01-01 |
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